drivers/rtc/rtc-sa1100.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
0004  *
0005  * Copyright (c) 2000 Nils Faerber
0006  *
0007  * Based on rtc.c by Paul Gortmaker
0008  *
0009  * Original Driver by Nils Faerber <nils@kernelconcepts.de>
0010  *
0011  * Modifications from:
0012  *   CIH <cih@coventive.com>
0013  *   Nicolas Pitre <nico@fluxnic.net>
0014  *   Andrew Christian <andrew.christian@hp.com>
0015  *
0016  * Converted to the RTC subsystem and Driver Model
0017  *   by Richard Purdie <rpurdie@rpsys.net>
0018  */
0019
0020 #include <linux/platform_device.h>
0021 #include <linux/module.h>
0022 #include <linux/clk.h>
0023 #include <linux/rtc.h>
0024 #include <linux/init.h>
0025 #include <linux/fs.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/slab.h>
0028 #include <linux/string.h>
0029 #include <linux/of.h>
0030 #include <linux/pm.h>
0031 #include <linux/bitops.h>
0032 #include <linux/io.h>
0033
0034 #define RTSR_HZE        BIT(3)  /* HZ interrupt enable */
0035 #define RTSR_ALE        BIT(2)  /* RTC alarm interrupt enable */
0036 #define RTSR_HZ         BIT(1)  /* HZ rising-edge detected */
0037 #define RTSR_AL         BIT(0)  /* RTC alarm detected */
0038
0039 #include "rtc-sa1100.h"
0040
0041 #define RTC_DEF_DIVIDER     (32768 - 1)
0042 #define RTC_DEF_TRIM        0
0043 #define RTC_FREQ        1024
0044
0045
0046 static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
0047 {
0048     struct sa1100_rtc *info = dev_get_drvdata(dev_id);
0049     struct rtc_device *rtc = info->rtc;
0050     unsigned int rtsr;
0051     unsigned long events = 0;
0052
0053     spin_lock(&info->lock);
0054
0055     rtsr = readl_relaxed(info->rtsr);
0056     /* clear interrupt sources */
0057     writel_relaxed(0, info->rtsr);
0058     /* Fix for a nasty initialization problem the in SA11xx RTSR register.
0059      * See also the comments in sa1100_rtc_probe(). */
0060     if (rtsr & (RTSR_ALE | RTSR_HZE)) {
0061         /* This is the original code, before there was the if test
0062          * above. This code does not clear interrupts that were not
0063          * enabled. */
0064         writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
0065     } else {
0066         /* For some reason, it is possible to enter this routine
0067          * without interruptions enabled, it has been tested with
0068          * several units (Bug in SA11xx chip?).
0069          *
0070          * This situation leads to an infinite "loop" of interrupt
0071          * routine calling and as a result the processor seems to
0072          * lock on its first call to open(). */
0073         writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
0074     }
0075
0076     /* clear alarm interrupt if it has occurred */
0077     if (rtsr & RTSR_AL)
0078         rtsr &= ~RTSR_ALE;
0079     writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
0080
0081     /* update irq data & counter */
0082     if (rtsr & RTSR_AL)
0083         events |= RTC_AF | RTC_IRQF;
0084     if (rtsr & RTSR_HZ)
0085         events |= RTC_UF | RTC_IRQF;
0086
0087     rtc_update_irq(rtc, 1, events);
0088
0089     spin_unlock(&info->lock);
0090
0091     return IRQ_HANDLED;
0092 }
0093
0094 static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0095 {
0096     u32 rtsr;
0097     struct sa1100_rtc *info = dev_get_drvdata(dev);
0098
0099     spin_lock_irq(&info->lock);
0100     rtsr = readl_relaxed(info->rtsr);
0101     if (enabled)
0102         rtsr |= RTSR_ALE;
0103     else
0104         rtsr &= ~RTSR_ALE;
0105     writel_relaxed(rtsr, info->rtsr);
0106     spin_unlock_irq(&info->lock);
0107     return 0;
0108 }
0109
0110 static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
0111 {
0112     struct sa1100_rtc *info = dev_get_drvdata(dev);
0113
0114     rtc_time64_to_tm(readl_relaxed(info->rcnr), tm);
0115     return 0;
0116 }
0117
0118 static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
0119 {
0120     struct sa1100_rtc *info = dev_get_drvdata(dev);
0121
0122     writel_relaxed(rtc_tm_to_time64(tm), info->rcnr);
0123
0124     return 0;
0125 }
0126
0127 static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0128 {
0129     u32 rtsr;
0130     struct sa1100_rtc *info = dev_get_drvdata(dev);
0131
0132     rtsr = readl_relaxed(info->rtsr);
0133     alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
0134     alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
0135     return 0;
0136 }
0137
0138 static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0139 {
0140     struct sa1100_rtc *info = dev_get_drvdata(dev);
0141
0142     spin_lock_irq(&info->lock);
0143     writel_relaxed(readl_relaxed(info->rtsr) &
0144         (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
0145     writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar);
0146     if (alrm->enabled)
0147         writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
0148     else
0149         writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
0150     spin_unlock_irq(&info->lock);
0151
0152     return 0;
0153 }
0154
0155 static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
0156 {
0157     struct sa1100_rtc *info = dev_get_drvdata(dev);
0158
0159     seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
0160     seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
0161
0162     return 0;
0163 }
0164
0165 static const struct rtc_class_ops sa1100_rtc_ops = {
0166     .read_time = sa1100_rtc_read_time,
0167     .set_time = sa1100_rtc_set_time,
0168     .read_alarm = sa1100_rtc_read_alarm,
0169     .set_alarm = sa1100_rtc_set_alarm,
0170     .proc = sa1100_rtc_proc,
0171     .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
0172 };
0173
0174 int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
0175 {
0176     int ret;
0177
0178     spin_lock_init(&info->lock);
0179
0180     info->clk = devm_clk_get(&pdev->dev, NULL);
0181     if (IS_ERR(info->clk)) {
0182         dev_err(&pdev->dev, "failed to find rtc clock source\n");
0183         return PTR_ERR(info->clk);
0184     }
0185
0186     ret = clk_prepare_enable(info->clk);
0187     if (ret)
0188         return ret;
0189     /*
0190      * According to the manual we should be able to let RTTR be zero
0191      * and then a default diviser for a 32.768KHz clock is used.
0192      * Apparently this doesn't work, at least for my SA1110 rev 5.
0193      * If the clock divider is uninitialized then reset it to the
0194      * default value to get the 1Hz clock.
0195      */
0196     if (readl_relaxed(info->rttr) == 0) {
0197         writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
0198         dev_warn(&pdev->dev, "warning: "
0199             "initializing default clock divider/trim value\n");
0200         /* The current RTC value probably doesn't make sense either */
0201         writel_relaxed(0, info->rcnr);
0202     }
0203
0204     info->rtc->ops = &sa1100_rtc_ops;
0205     info->rtc->max_user_freq = RTC_FREQ;
0206     info->rtc->range_max = U32_MAX;
0207
0208     ret = devm_rtc_register_device(info->rtc);
0209     if (ret) {
0210         clk_disable_unprepare(info->clk);
0211         return ret;
0212     }
0213
0214     /* Fix for a nasty initialization problem the in SA11xx RTSR register.
0215      * See also the comments in sa1100_rtc_interrupt().
0216      *
0217      * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
0218      * interrupt pending, even though interrupts were never enabled.
0219      * In this case, this bit it must be reset before enabling
0220      * interruptions to avoid a nonexistent interrupt to occur.
0221      *
0222      * In principle, the same problem would apply to bit 0, although it has
0223      * never been observed to happen.
0224      *
0225      * This issue is addressed both here and in sa1100_rtc_interrupt().
0226      * If the issue is not addressed here, in the times when the processor
0227      * wakes up with the bit set there will be one spurious interrupt.
0228      *
0229      * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
0230      * safe side, once the condition that lead to this strange
0231      * initialization is unknown and could in principle happen during
0232      * normal processing.
0233      *
0234      * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
0235      * the corresponding bits in RTSR. */
0236     writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
0237
0238     return 0;
0239 }
0240 EXPORT_SYMBOL_GPL(sa1100_rtc_init);
0241
0242 static int sa1100_rtc_probe(struct platform_device *pdev)
0243 {
0244     struct sa1100_rtc *info;
0245     void __iomem *base;
0246     int irq_1hz, irq_alarm;
0247     int ret;
0248
0249     irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
0250     irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
0251     if (irq_1hz < 0 || irq_alarm < 0)
0252         return -ENODEV;
0253
0254     info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
0255     if (!info)
0256         return -ENOMEM;
0257     info->irq_1hz = irq_1hz;
0258     info->irq_alarm = irq_alarm;
0259
0260     info->rtc = devm_rtc_allocate_device(&pdev->dev);
0261     if (IS_ERR(info->rtc))
0262         return PTR_ERR(info->rtc);
0263
0264     ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
0265                    "rtc 1Hz", &pdev->dev);
0266     if (ret) {
0267         dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
0268         return ret;
0269     }
0270     ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
0271                    "rtc Alrm", &pdev->dev);
0272     if (ret) {
0273         dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
0274         return ret;
0275     }
0276
0277     base = devm_platform_ioremap_resource(pdev, 0);
0278     if (IS_ERR(base))
0279         return PTR_ERR(base);
0280
0281     if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
0282         of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
0283         info->rcnr = base + 0x04;
0284         info->rtsr = base + 0x10;
0285         info->rtar = base + 0x00;
0286         info->rttr = base + 0x08;
0287     } else {
0288         info->rcnr = base + 0x0;
0289         info->rtsr = base + 0x8;
0290         info->rtar = base + 0x4;
0291         info->rttr = base + 0xc;
0292     }
0293
0294     platform_set_drvdata(pdev, info);
0295     device_init_wakeup(&pdev->dev, 1);
0296
0297     return sa1100_rtc_init(pdev, info);
0298 }
0299
0300 static int sa1100_rtc_remove(struct platform_device *pdev)
0301 {
0302     struct sa1100_rtc *info = platform_get_drvdata(pdev);
0303
0304     if (info) {
0305         spin_lock_irq(&info->lock);
0306         writel_relaxed(0, info->rtsr);
0307         spin_unlock_irq(&info->lock);
0308         clk_disable_unprepare(info->clk);
0309     }
0310
0311     return 0;
0312 }
0313
0314 #ifdef CONFIG_PM_SLEEP
0315 static int sa1100_rtc_suspend(struct device *dev)
0316 {
0317     struct sa1100_rtc *info = dev_get_drvdata(dev);
0318     if (device_may_wakeup(dev))
0319         enable_irq_wake(info->irq_alarm);
0320     return 0;
0321 }
0322
0323 static int sa1100_rtc_resume(struct device *dev)
0324 {
0325     struct sa1100_rtc *info = dev_get_drvdata(dev);
0326     if (device_may_wakeup(dev))
0327         disable_irq_wake(info->irq_alarm);
0328     return 0;
0329 }
0330 #endif
0331
0332 static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
0333             sa1100_rtc_resume);
0334
0335 #ifdef CONFIG_OF
0336 static const struct of_device_id sa1100_rtc_dt_ids[] = {
0337     { .compatible = "mrvl,sa1100-rtc", },
0338     { .compatible = "mrvl,mmp-rtc", },
0339     {}
0340 };
0341 MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
0342 #endif
0343
0344 static struct platform_driver sa1100_rtc_driver = {
0345     .probe      = sa1100_rtc_probe,
0346     .remove     = sa1100_rtc_remove,
0347     .driver     = {
0348         .name   = "sa1100-rtc",
0349         .pm = &sa1100_rtc_pm_ops,
0350         .of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
0351     },
0352 };
0353
0354 module_platform_driver(sa1100_rtc_driver);
0355
0356 MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
0357 MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
0358 MODULE_LICENSE("GPL");
0359 MODULE_ALIAS("platform:sa1100-rtc");