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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
0004 //  http://www.samsung.com
0005 //
0006 //  Copyright (C) 2013 Google, Inc
0007 
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009 
0010 #include <linux/module.h>
0011 #include <linux/i2c.h>
0012 #include <linux/bcd.h>
0013 #include <linux/regmap.h>
0014 #include <linux/rtc.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/mfd/samsung/core.h>
0017 #include <linux/mfd/samsung/irq.h>
0018 #include <linux/mfd/samsung/rtc.h>
0019 #include <linux/mfd/samsung/s2mps14.h>
0020 
0021 /*
0022  * Maximum number of retries for checking changes in UDR field
0023  * of S5M_RTC_UDR_CON register (to limit possible endless loop).
0024  *
0025  * After writing to RTC registers (setting time or alarm) read the UDR field
0026  * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
0027  * been transferred.
0028  */
0029 #define UDR_READ_RETRY_CNT  5
0030 
0031 enum {
0032     RTC_SEC = 0,
0033     RTC_MIN,
0034     RTC_HOUR,
0035     RTC_WEEKDAY,
0036     RTC_DATE,
0037     RTC_MONTH,
0038     RTC_YEAR1,
0039     RTC_YEAR2,
0040     /* Make sure this is always the last enum name. */
0041     RTC_MAX_NUM_TIME_REGS
0042 };
0043 
0044 /*
0045  * Registers used by the driver which are different between chipsets.
0046  *
0047  * Operations like read time and write alarm/time require updating
0048  * specific fields in UDR register. These fields usually are auto-cleared
0049  * (with some exceptions).
0050  *
0051  * Table of operations per device:
0052  *
0053  * Device     | Write time | Read time | Write alarm
0054  * =================================================
0055  * S5M8767    | UDR + TIME |           | UDR
0056  * S2MPS11/14 | WUDR       | RUDR      | WUDR + RUDR
0057  * S2MPS13    | WUDR       | RUDR      | WUDR + AUDR
0058  * S2MPS15    | WUDR       | RUDR      | AUDR
0059  */
0060 struct s5m_rtc_reg_config {
0061     /* Number of registers used for setting time/alarm0/alarm1 */
0062     unsigned int regs_count;
0063     /* First register for time, seconds */
0064     unsigned int time;
0065     /* RTC control register */
0066     unsigned int ctrl;
0067     /* First register for alarm 0, seconds */
0068     unsigned int alarm0;
0069     /* First register for alarm 1, seconds */
0070     unsigned int alarm1;
0071     /*
0072      * Register for update flag (UDR). Typically setting UDR field to 1
0073      * will enable update of time or alarm register. Then it will be
0074      * auto-cleared after successful update.
0075      */
0076     unsigned int udr_update;
0077     /* Auto-cleared mask in UDR field for writing time and alarm */
0078     unsigned int autoclear_udr_mask;
0079     /*
0080      * Masks in UDR field for time and alarm operations.
0081      * The read time mask can be 0. Rest should not.
0082      */
0083     unsigned int read_time_udr_mask;
0084     unsigned int write_time_udr_mask;
0085     unsigned int write_alarm_udr_mask;
0086 };
0087 
0088 /* Register map for S5M8763 and S5M8767 */
0089 static const struct s5m_rtc_reg_config s5m_rtc_regs = {
0090     .regs_count     = 8,
0091     .time           = S5M_RTC_SEC,
0092     .ctrl           = S5M_ALARM1_CONF,
0093     .alarm0         = S5M_ALARM0_SEC,
0094     .alarm1         = S5M_ALARM1_SEC,
0095     .udr_update     = S5M_RTC_UDR_CON,
0096     .autoclear_udr_mask = S5M_RTC_UDR_MASK,
0097     .read_time_udr_mask = 0, /* Not needed */
0098     .write_time_udr_mask    = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
0099     .write_alarm_udr_mask   = S5M_RTC_UDR_MASK,
0100 };
0101 
0102 /* Register map for S2MPS13 */
0103 static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
0104     .regs_count     = 7,
0105     .time           = S2MPS_RTC_SEC,
0106     .ctrl           = S2MPS_RTC_CTRL,
0107     .alarm0         = S2MPS_ALARM0_SEC,
0108     .alarm1         = S2MPS_ALARM1_SEC,
0109     .udr_update     = S2MPS_RTC_UDR_CON,
0110     .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
0111     .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
0112     .write_time_udr_mask    = S2MPS_RTC_WUDR_MASK,
0113     .write_alarm_udr_mask   = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
0114 };
0115 
0116 /* Register map for S2MPS11/14 */
0117 static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
0118     .regs_count     = 7,
0119     .time           = S2MPS_RTC_SEC,
0120     .ctrl           = S2MPS_RTC_CTRL,
0121     .alarm0         = S2MPS_ALARM0_SEC,
0122     .alarm1         = S2MPS_ALARM1_SEC,
0123     .udr_update     = S2MPS_RTC_UDR_CON,
0124     .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
0125     .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
0126     .write_time_udr_mask    = S2MPS_RTC_WUDR_MASK,
0127     .write_alarm_udr_mask   = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
0128 };
0129 
0130 /*
0131  * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
0132  * are swapped.
0133  */
0134 static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
0135     .regs_count     = 7,
0136     .time           = S2MPS_RTC_SEC,
0137     .ctrl           = S2MPS_RTC_CTRL,
0138     .alarm0         = S2MPS_ALARM0_SEC,
0139     .alarm1         = S2MPS_ALARM1_SEC,
0140     .udr_update     = S2MPS_RTC_UDR_CON,
0141     .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
0142     .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
0143     .write_time_udr_mask    = S2MPS15_RTC_WUDR_MASK,
0144     .write_alarm_udr_mask   = S2MPS15_RTC_AUDR_MASK,
0145 };
0146 
0147 struct s5m_rtc_info {
0148     struct device *dev;
0149     struct i2c_client *i2c;
0150     struct sec_pmic_dev *s5m87xx;
0151     struct regmap *regmap;
0152     struct rtc_device *rtc_dev;
0153     int irq;
0154     enum sec_device_type device_type;
0155     int rtc_24hr_mode;
0156     const struct s5m_rtc_reg_config *regs;
0157 };
0158 
0159 static const struct regmap_config s5m_rtc_regmap_config = {
0160     .reg_bits = 8,
0161     .val_bits = 8,
0162 
0163     .max_register = S5M_RTC_REG_MAX,
0164 };
0165 
0166 static const struct regmap_config s2mps14_rtc_regmap_config = {
0167     .reg_bits = 8,
0168     .val_bits = 8,
0169 
0170     .max_register = S2MPS_RTC_REG_MAX,
0171 };
0172 
0173 static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
0174                    int rtc_24hr_mode)
0175 {
0176     tm->tm_sec = data[RTC_SEC] & 0x7f;
0177     tm->tm_min = data[RTC_MIN] & 0x7f;
0178     if (rtc_24hr_mode) {
0179         tm->tm_hour = data[RTC_HOUR] & 0x1f;
0180     } else {
0181         tm->tm_hour = data[RTC_HOUR] & 0x0f;
0182         if (data[RTC_HOUR] & HOUR_PM_MASK)
0183             tm->tm_hour += 12;
0184     }
0185 
0186     tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
0187     tm->tm_mday = data[RTC_DATE] & 0x1f;
0188     tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
0189     tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
0190     tm->tm_yday = 0;
0191     tm->tm_isdst = 0;
0192 }
0193 
0194 static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
0195 {
0196     data[RTC_SEC] = tm->tm_sec;
0197     data[RTC_MIN] = tm->tm_min;
0198 
0199     if (tm->tm_hour >= 12)
0200         data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
0201     else
0202         data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
0203 
0204     data[RTC_WEEKDAY] = 1 << tm->tm_wday;
0205     data[RTC_DATE] = tm->tm_mday;
0206     data[RTC_MONTH] = tm->tm_mon + 1;
0207     data[RTC_YEAR1] = tm->tm_year - 100;
0208 
0209     return 0;
0210 }
0211 
0212 /*
0213  * Read RTC_UDR_CON register and wait till UDR field is cleared.
0214  * This indicates that time/alarm update ended.
0215  */
0216 static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
0217 {
0218     int ret, retry = UDR_READ_RETRY_CNT;
0219     unsigned int data;
0220 
0221     do {
0222         ret = regmap_read(info->regmap, info->regs->udr_update, &data);
0223     } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
0224 
0225     if (!retry)
0226         dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
0227 
0228     return ret;
0229 }
0230 
0231 static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info,
0232         struct rtc_wkalrm *alarm)
0233 {
0234     int ret;
0235     unsigned int val;
0236 
0237     switch (info->device_type) {
0238     case S5M8767X:
0239     case S5M8763X:
0240         ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
0241         val &= S5M_ALARM0_STATUS;
0242         break;
0243     case S2MPS15X:
0244     case S2MPS14X:
0245     case S2MPS13X:
0246         ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
0247                 &val);
0248         val &= S2MPS_ALARM0_STATUS;
0249         break;
0250     default:
0251         return -EINVAL;
0252     }
0253     if (ret < 0)
0254         return ret;
0255 
0256     if (val)
0257         alarm->pending = 1;
0258     else
0259         alarm->pending = 0;
0260 
0261     return 0;
0262 }
0263 
0264 static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
0265 {
0266     int ret;
0267     unsigned int data;
0268 
0269     ret = regmap_read(info->regmap, info->regs->udr_update, &data);
0270     if (ret < 0) {
0271         dev_err(info->dev, "failed to read update reg(%d)\n", ret);
0272         return ret;
0273     }
0274 
0275     data |= info->regs->write_time_udr_mask;
0276 
0277     ret = regmap_write(info->regmap, info->regs->udr_update, data);
0278     if (ret < 0) {
0279         dev_err(info->dev, "failed to write update reg(%d)\n", ret);
0280         return ret;
0281     }
0282 
0283     ret = s5m8767_wait_for_udr_update(info);
0284 
0285     return ret;
0286 }
0287 
0288 static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
0289 {
0290     int ret;
0291     unsigned int data;
0292 
0293     ret = regmap_read(info->regmap, info->regs->udr_update, &data);
0294     if (ret < 0) {
0295         dev_err(info->dev, "%s: fail to read update reg(%d)\n",
0296             __func__, ret);
0297         return ret;
0298     }
0299 
0300     data |= info->regs->write_alarm_udr_mask;
0301     switch (info->device_type) {
0302     case S5M8763X:
0303     case S5M8767X:
0304         data &= ~S5M_RTC_TIME_EN_MASK;
0305         break;
0306     case S2MPS15X:
0307     case S2MPS14X:
0308     case S2MPS13X:
0309         /* No exceptions needed */
0310         break;
0311     default:
0312         return -EINVAL;
0313     }
0314 
0315     ret = regmap_write(info->regmap, info->regs->udr_update, data);
0316     if (ret < 0) {
0317         dev_err(info->dev, "%s: fail to write update reg(%d)\n",
0318             __func__, ret);
0319         return ret;
0320     }
0321 
0322     ret = s5m8767_wait_for_udr_update(info);
0323 
0324     /* On S2MPS13 the AUDR is not auto-cleared */
0325     if (info->device_type == S2MPS13X)
0326         regmap_update_bits(info->regmap, info->regs->udr_update,
0327                    S2MPS13_RTC_AUDR_MASK, 0);
0328 
0329     return ret;
0330 }
0331 
0332 static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm)
0333 {
0334     tm->tm_sec = bcd2bin(data[RTC_SEC]);
0335     tm->tm_min = bcd2bin(data[RTC_MIN]);
0336 
0337     if (data[RTC_HOUR] & HOUR_12) {
0338         tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f);
0339         if (data[RTC_HOUR] & HOUR_PM)
0340             tm->tm_hour += 12;
0341     } else {
0342         tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
0343     }
0344 
0345     tm->tm_wday = data[RTC_WEEKDAY] & 0x07;
0346     tm->tm_mday = bcd2bin(data[RTC_DATE]);
0347     tm->tm_mon = bcd2bin(data[RTC_MONTH]);
0348     tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100;
0349     tm->tm_year -= 1900;
0350 }
0351 
0352 static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data)
0353 {
0354     data[RTC_SEC] = bin2bcd(tm->tm_sec);
0355     data[RTC_MIN] = bin2bcd(tm->tm_min);
0356     data[RTC_HOUR] = bin2bcd(tm->tm_hour);
0357     data[RTC_WEEKDAY] = tm->tm_wday;
0358     data[RTC_DATE] = bin2bcd(tm->tm_mday);
0359     data[RTC_MONTH] = bin2bcd(tm->tm_mon);
0360     data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100);
0361     data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100);
0362 }
0363 
0364 static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
0365 {
0366     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0367     u8 data[RTC_MAX_NUM_TIME_REGS];
0368     int ret;
0369 
0370     if (info->regs->read_time_udr_mask) {
0371         ret = regmap_update_bits(info->regmap,
0372                 info->regs->udr_update,
0373                 info->regs->read_time_udr_mask,
0374                 info->regs->read_time_udr_mask);
0375         if (ret) {
0376             dev_err(dev,
0377                 "Failed to prepare registers for time reading: %d\n",
0378                 ret);
0379             return ret;
0380         }
0381     }
0382     ret = regmap_bulk_read(info->regmap, info->regs->time, data,
0383             info->regs->regs_count);
0384     if (ret < 0)
0385         return ret;
0386 
0387     switch (info->device_type) {
0388     case S5M8763X:
0389         s5m8763_data_to_tm(data, tm);
0390         break;
0391 
0392     case S5M8767X:
0393     case S2MPS15X:
0394     case S2MPS14X:
0395     case S2MPS13X:
0396         s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
0397         break;
0398 
0399     default:
0400         return -EINVAL;
0401     }
0402 
0403     dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
0404 
0405     return 0;
0406 }
0407 
0408 static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
0409 {
0410     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0411     u8 data[RTC_MAX_NUM_TIME_REGS];
0412     int ret = 0;
0413 
0414     switch (info->device_type) {
0415     case S5M8763X:
0416         s5m8763_tm_to_data(tm, data);
0417         break;
0418     case S5M8767X:
0419     case S2MPS15X:
0420     case S2MPS14X:
0421     case S2MPS13X:
0422         ret = s5m8767_tm_to_data(tm, data);
0423         break;
0424     default:
0425         return -EINVAL;
0426     }
0427 
0428     if (ret < 0)
0429         return ret;
0430 
0431     dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
0432 
0433     ret = regmap_raw_write(info->regmap, info->regs->time, data,
0434             info->regs->regs_count);
0435     if (ret < 0)
0436         return ret;
0437 
0438     ret = s5m8767_rtc_set_time_reg(info);
0439 
0440     return ret;
0441 }
0442 
0443 static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0444 {
0445     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0446     u8 data[RTC_MAX_NUM_TIME_REGS];
0447     unsigned int val;
0448     int ret, i;
0449 
0450     ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
0451             info->regs->regs_count);
0452     if (ret < 0)
0453         return ret;
0454 
0455     switch (info->device_type) {
0456     case S5M8763X:
0457         s5m8763_data_to_tm(data, &alrm->time);
0458         ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val);
0459         if (ret < 0)
0460             return ret;
0461 
0462         alrm->enabled = !!val;
0463         break;
0464 
0465     case S5M8767X:
0466     case S2MPS15X:
0467     case S2MPS14X:
0468     case S2MPS13X:
0469         s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
0470         alrm->enabled = 0;
0471         for (i = 0; i < info->regs->regs_count; i++) {
0472             if (data[i] & ALARM_ENABLE_MASK) {
0473                 alrm->enabled = 1;
0474                 break;
0475             }
0476         }
0477         break;
0478 
0479     default:
0480         return -EINVAL;
0481     }
0482 
0483     dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
0484 
0485     return s5m_check_peding_alarm_interrupt(info, alrm);
0486 }
0487 
0488 static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
0489 {
0490     u8 data[RTC_MAX_NUM_TIME_REGS];
0491     int ret, i;
0492     struct rtc_time tm;
0493 
0494     ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
0495             info->regs->regs_count);
0496     if (ret < 0)
0497         return ret;
0498 
0499     s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
0500     dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
0501 
0502     switch (info->device_type) {
0503     case S5M8763X:
0504         ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0);
0505         break;
0506 
0507     case S5M8767X:
0508     case S2MPS15X:
0509     case S2MPS14X:
0510     case S2MPS13X:
0511         for (i = 0; i < info->regs->regs_count; i++)
0512             data[i] &= ~ALARM_ENABLE_MASK;
0513 
0514         ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
0515                 info->regs->regs_count);
0516         if (ret < 0)
0517             return ret;
0518 
0519         ret = s5m8767_rtc_set_alarm_reg(info);
0520 
0521         break;
0522 
0523     default:
0524         return -EINVAL;
0525     }
0526 
0527     return ret;
0528 }
0529 
0530 static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
0531 {
0532     int ret;
0533     u8 data[RTC_MAX_NUM_TIME_REGS];
0534     u8 alarm0_conf;
0535     struct rtc_time tm;
0536 
0537     ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
0538             info->regs->regs_count);
0539     if (ret < 0)
0540         return ret;
0541 
0542     s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
0543     dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
0544 
0545     switch (info->device_type) {
0546     case S5M8763X:
0547         alarm0_conf = 0x77;
0548         ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf);
0549         break;
0550 
0551     case S5M8767X:
0552     case S2MPS15X:
0553     case S2MPS14X:
0554     case S2MPS13X:
0555         data[RTC_SEC] |= ALARM_ENABLE_MASK;
0556         data[RTC_MIN] |= ALARM_ENABLE_MASK;
0557         data[RTC_HOUR] |= ALARM_ENABLE_MASK;
0558         data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
0559         if (data[RTC_DATE] & 0x1f)
0560             data[RTC_DATE] |= ALARM_ENABLE_MASK;
0561         if (data[RTC_MONTH] & 0xf)
0562             data[RTC_MONTH] |= ALARM_ENABLE_MASK;
0563         if (data[RTC_YEAR1] & 0x7f)
0564             data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
0565 
0566         ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
0567                 info->regs->regs_count);
0568         if (ret < 0)
0569             return ret;
0570         ret = s5m8767_rtc_set_alarm_reg(info);
0571 
0572         break;
0573 
0574     default:
0575         return -EINVAL;
0576     }
0577 
0578     return ret;
0579 }
0580 
0581 static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0582 {
0583     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0584     u8 data[RTC_MAX_NUM_TIME_REGS];
0585     int ret;
0586 
0587     switch (info->device_type) {
0588     case S5M8763X:
0589         s5m8763_tm_to_data(&alrm->time, data);
0590         break;
0591 
0592     case S5M8767X:
0593     case S2MPS15X:
0594     case S2MPS14X:
0595     case S2MPS13X:
0596         s5m8767_tm_to_data(&alrm->time, data);
0597         break;
0598 
0599     default:
0600         return -EINVAL;
0601     }
0602 
0603     dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
0604 
0605     ret = s5m_rtc_stop_alarm(info);
0606     if (ret < 0)
0607         return ret;
0608 
0609     ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
0610             info->regs->regs_count);
0611     if (ret < 0)
0612         return ret;
0613 
0614     ret = s5m8767_rtc_set_alarm_reg(info);
0615     if (ret < 0)
0616         return ret;
0617 
0618     if (alrm->enabled)
0619         ret = s5m_rtc_start_alarm(info);
0620 
0621     return ret;
0622 }
0623 
0624 static int s5m_rtc_alarm_irq_enable(struct device *dev,
0625                     unsigned int enabled)
0626 {
0627     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0628 
0629     if (enabled)
0630         return s5m_rtc_start_alarm(info);
0631     else
0632         return s5m_rtc_stop_alarm(info);
0633 }
0634 
0635 static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
0636 {
0637     struct s5m_rtc_info *info = data;
0638 
0639     rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
0640 
0641     return IRQ_HANDLED;
0642 }
0643 
0644 static const struct rtc_class_ops s5m_rtc_ops = {
0645     .read_time = s5m_rtc_read_time,
0646     .set_time = s5m_rtc_set_time,
0647     .read_alarm = s5m_rtc_read_alarm,
0648     .set_alarm = s5m_rtc_set_alarm,
0649     .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
0650 };
0651 
0652 static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
0653 {
0654     u8 data[2];
0655     int ret;
0656 
0657     switch (info->device_type) {
0658     case S5M8763X:
0659     case S5M8767X:
0660         /* UDR update time. Default of 7.32 ms is too long. */
0661         ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
0662                 S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
0663         if (ret < 0)
0664             dev_err(info->dev, "%s: fail to change UDR time: %d\n",
0665                     __func__, ret);
0666 
0667         /* Set RTC control register : Binary mode, 24hour mode */
0668         data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
0669         data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
0670 
0671         ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
0672         break;
0673 
0674     case S2MPS15X:
0675     case S2MPS14X:
0676     case S2MPS13X:
0677         data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
0678         ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
0679         if (ret < 0)
0680             break;
0681 
0682         /*
0683          * Should set WUDR & (RUDR or AUDR) bits to high after writing
0684          * RTC_CTRL register like writing Alarm registers. We can't find
0685          * the description from datasheet but vendor code does that
0686          * really.
0687          */
0688         ret = s5m8767_rtc_set_alarm_reg(info);
0689         break;
0690 
0691     default:
0692         return -EINVAL;
0693     }
0694 
0695     info->rtc_24hr_mode = 1;
0696     if (ret < 0) {
0697         dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
0698             __func__, ret);
0699         return ret;
0700     }
0701 
0702     return ret;
0703 }
0704 
0705 static int s5m_rtc_probe(struct platform_device *pdev)
0706 {
0707     struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
0708     struct s5m_rtc_info *info;
0709     const struct regmap_config *regmap_cfg;
0710     int ret, alarm_irq;
0711 
0712     info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
0713     if (!info)
0714         return -ENOMEM;
0715 
0716     switch (platform_get_device_id(pdev)->driver_data) {
0717     case S2MPS15X:
0718         regmap_cfg = &s2mps14_rtc_regmap_config;
0719         info->regs = &s2mps15_rtc_regs;
0720         alarm_irq = S2MPS14_IRQ_RTCA0;
0721         break;
0722     case S2MPS14X:
0723         regmap_cfg = &s2mps14_rtc_regmap_config;
0724         info->regs = &s2mps14_rtc_regs;
0725         alarm_irq = S2MPS14_IRQ_RTCA0;
0726         break;
0727     case S2MPS13X:
0728         regmap_cfg = &s2mps14_rtc_regmap_config;
0729         info->regs = &s2mps13_rtc_regs;
0730         alarm_irq = S2MPS14_IRQ_RTCA0;
0731         break;
0732     case S5M8763X:
0733         regmap_cfg = &s5m_rtc_regmap_config;
0734         info->regs = &s5m_rtc_regs;
0735         alarm_irq = S5M8763_IRQ_ALARM0;
0736         break;
0737     case S5M8767X:
0738         regmap_cfg = &s5m_rtc_regmap_config;
0739         info->regs = &s5m_rtc_regs;
0740         alarm_irq = S5M8767_IRQ_RTCA1;
0741         break;
0742     default:
0743         dev_err(&pdev->dev,
0744                 "Device type %lu is not supported by RTC driver\n",
0745                 platform_get_device_id(pdev)->driver_data);
0746         return -ENODEV;
0747     }
0748 
0749     info->i2c = devm_i2c_new_dummy_device(&pdev->dev, s5m87xx->i2c->adapter,
0750                           RTC_I2C_ADDR);
0751     if (IS_ERR(info->i2c)) {
0752         dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n");
0753         return PTR_ERR(info->i2c);
0754     }
0755 
0756     info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg);
0757     if (IS_ERR(info->regmap)) {
0758         ret = PTR_ERR(info->regmap);
0759         dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n",
0760                 ret);
0761         return ret;
0762     }
0763 
0764     info->dev = &pdev->dev;
0765     info->s5m87xx = s5m87xx;
0766     info->device_type = platform_get_device_id(pdev)->driver_data;
0767 
0768     if (s5m87xx->irq_data) {
0769         info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
0770         if (info->irq <= 0) {
0771             dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n",
0772                 alarm_irq);
0773             return -EINVAL;
0774         }
0775     }
0776 
0777     platform_set_drvdata(pdev, info);
0778 
0779     ret = s5m8767_rtc_init_reg(info);
0780     if (ret)
0781         return ret;
0782 
0783     info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
0784     if (IS_ERR(info->rtc_dev))
0785         return PTR_ERR(info->rtc_dev);
0786 
0787     info->rtc_dev->ops = &s5m_rtc_ops;
0788 
0789     if (info->device_type == S5M8763X) {
0790         info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_0000;
0791         info->rtc_dev->range_max = RTC_TIMESTAMP_END_9999;
0792     } else {
0793         info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
0794         info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
0795     }
0796 
0797     if (!info->irq) {
0798         clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features);
0799     } else {
0800         ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
0801                         s5m_rtc_alarm_irq, 0, "rtc-alarm0",
0802                         info);
0803         if (ret < 0) {
0804             dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
0805                 info->irq, ret);
0806             return ret;
0807         }
0808         device_init_wakeup(&pdev->dev, 1);
0809     }
0810 
0811     return devm_rtc_register_device(info->rtc_dev);
0812 }
0813 
0814 #ifdef CONFIG_PM_SLEEP
0815 static int s5m_rtc_resume(struct device *dev)
0816 {
0817     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0818     int ret = 0;
0819 
0820     if (info->irq && device_may_wakeup(dev))
0821         ret = disable_irq_wake(info->irq);
0822 
0823     return ret;
0824 }
0825 
0826 static int s5m_rtc_suspend(struct device *dev)
0827 {
0828     struct s5m_rtc_info *info = dev_get_drvdata(dev);
0829     int ret = 0;
0830 
0831     if (info->irq && device_may_wakeup(dev))
0832         ret = enable_irq_wake(info->irq);
0833 
0834     return ret;
0835 }
0836 #endif /* CONFIG_PM_SLEEP */
0837 
0838 static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
0839 
0840 static const struct platform_device_id s5m_rtc_id[] = {
0841     { "s5m-rtc",        S5M8767X },
0842     { "s2mps13-rtc",    S2MPS13X },
0843     { "s2mps14-rtc",    S2MPS14X },
0844     { "s2mps15-rtc",    S2MPS15X },
0845     { },
0846 };
0847 MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
0848 
0849 static struct platform_driver s5m_rtc_driver = {
0850     .driver     = {
0851         .name   = "s5m-rtc",
0852         .pm = &s5m_rtc_pm_ops,
0853     },
0854     .probe      = s5m_rtc_probe,
0855     .id_table   = s5m_rtc_id,
0856 };
0857 
0858 module_platform_driver(s5m_rtc_driver);
0859 
0860 /* Module information */
0861 MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
0862 MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
0863 MODULE_LICENSE("GPL");
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