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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
0004  *            http://www.simtec.co.uk/products/SWLINUX/
0005  *
0006  * S3C2410 Internal RTC register definition
0007 */
0008 
0009 #ifndef __ASM_ARCH_REGS_RTC_H
0010 #define __ASM_ARCH_REGS_RTC_H __FILE__
0011 
0012 #define S3C2410_RTCREG(x) (x)
0013 #define S3C2410_INTP        S3C2410_RTCREG(0x30)
0014 #define S3C2410_INTP_ALM    (1 << 1)
0015 #define S3C2410_INTP_TIC    (1 << 0)
0016 
0017 #define S3C2410_RTCCON      S3C2410_RTCREG(0x40)
0018 #define S3C2410_RTCCON_RTCEN    (1 << 0)
0019 #define S3C2410_RTCCON_CNTSEL   (1 << 2)
0020 #define S3C2410_RTCCON_CLKRST   (1 << 3)
0021 #define S3C2443_RTCCON_TICSEL   (1 << 4)
0022 #define S3C64XX_RTCCON_TICEN    (1 << 8)
0023 
0024 #define S3C2410_TICNT       S3C2410_RTCREG(0x44)
0025 #define S3C2410_TICNT_ENABLE    (1 << 7)
0026 
0027 /* S3C2443: tick count is 15 bit wide
0028  * TICNT[6:0] contains upper 7 bits
0029  * TICNT1[7:0] contains lower 8 bits
0030  */
0031 #define S3C2443_TICNT_PART(x)   ((x & 0x7f00) >> 8)
0032 #define S3C2443_TICNT1      S3C2410_RTCREG(0x4C)
0033 #define S3C2443_TICNT1_PART(x)  (x & 0xff)
0034 
0035 /* S3C2416: tick count is 32 bit wide
0036  * TICNT[6:0] contains bits [14:8]
0037  * TICNT1[7:0] contains lower 8 bits
0038  * TICNT2[16:0] contains upper 17 bits
0039  */
0040 #define S3C2416_TICNT2      S3C2410_RTCREG(0x48)
0041 #define S3C2416_TICNT2_PART(x)  ((x & 0xffff8000) >> 15)
0042 
0043 #define S3C2410_RTCALM      S3C2410_RTCREG(0x50)
0044 #define S3C2410_RTCALM_ALMEN    (1 << 6)
0045 #define S3C2410_RTCALM_YEAREN   (1 << 5)
0046 #define S3C2410_RTCALM_MONEN    (1 << 4)
0047 #define S3C2410_RTCALM_DAYEN    (1 << 3)
0048 #define S3C2410_RTCALM_HOUREN   (1 << 2)
0049 #define S3C2410_RTCALM_MINEN    (1 << 1)
0050 #define S3C2410_RTCALM_SECEN    (1 << 0)
0051 
0052 #define S3C2410_ALMSEC      S3C2410_RTCREG(0x54)
0053 #define S3C2410_ALMMIN      S3C2410_RTCREG(0x58)
0054 #define S3C2410_ALMHOUR     S3C2410_RTCREG(0x5c)
0055 
0056 #define S3C2410_ALMDATE     S3C2410_RTCREG(0x60)
0057 #define S3C2410_ALMMON      S3C2410_RTCREG(0x64)
0058 #define S3C2410_ALMYEAR     S3C2410_RTCREG(0x68)
0059 
0060 #define S3C2410_RTCSEC      S3C2410_RTCREG(0x70)
0061 #define S3C2410_RTCMIN      S3C2410_RTCREG(0x74)
0062 #define S3C2410_RTCHOUR     S3C2410_RTCREG(0x78)
0063 #define S3C2410_RTCDATE     S3C2410_RTCREG(0x7c)
0064 #define S3C2410_RTCMON      S3C2410_RTCREG(0x84)
0065 #define S3C2410_RTCYEAR     S3C2410_RTCREG(0x88)
0066 
0067 #endif /* __ASM_ARCH_REGS_RTC_H */