drivers/rtc/rtc-rzn1.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Renesas RZ/N1 Real Time Clock interface for Linux
0004  *
0005  * Copyright:
0006  * - 2014 Renesas Electronics Europe Limited
0007  * - 2022 Schneider Electric
0008  *
0009  * Authors:
0010  * - Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
0011  * - Miquel Raynal <miquel.raynal@bootlin.com>
0012  */
0013
0014 #include <linux/bcd.h>
0015 #include <linux/init.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/module.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pm_runtime.h>
0021 #include <linux/rtc.h>
0022
0023 #define RZN1_RTC_CTL0 0x00
0024 #define   RZN1_RTC_CTL0_SLSB_SUBU 0
0025 #define   RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
0026 #define   RZN1_RTC_CTL0_AMPM BIT(5)
0027 #define   RZN1_RTC_CTL0_CE BIT(7)
0028
0029 #define RZN1_RTC_CTL1 0x04
0030 #define   RZN1_RTC_CTL1_ALME BIT(4)
0031
0032 #define RZN1_RTC_CTL2 0x08
0033 #define   RZN1_RTC_CTL2_WAIT BIT(0)
0034 #define   RZN1_RTC_CTL2_WST BIT(1)
0035 #define   RZN1_RTC_CTL2_WUST BIT(5)
0036 #define   RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST)
0037
0038 #define RZN1_RTC_SEC 0x14
0039 #define RZN1_RTC_MIN 0x18
0040 #define RZN1_RTC_HOUR 0x1c
0041 #define RZN1_RTC_WEEK 0x20
0042 #define RZN1_RTC_DAY 0x24
0043 #define RZN1_RTC_MONTH 0x28
0044 #define RZN1_RTC_YEAR 0x2c
0045
0046 #define RZN1_RTC_SUBU 0x38
0047 #define   RZN1_RTC_SUBU_DEV BIT(7)
0048 #define   RZN1_RTC_SUBU_DECR BIT(6)
0049
0050 #define RZN1_RTC_ALM 0x40
0051 #define RZN1_RTC_ALH 0x44
0052 #define RZN1_RTC_ALW 0x48
0053
0054 #define RZN1_RTC_SECC 0x4c
0055 #define RZN1_RTC_MINC 0x50
0056 #define RZN1_RTC_HOURC 0x54
0057 #define RZN1_RTC_WEEKC 0x58
0058 #define RZN1_RTC_DAYC 0x5c
0059 #define RZN1_RTC_MONTHC 0x60
0060 #define RZN1_RTC_YEARC 0x64
0061
0062 struct rzn1_rtc {
0063     struct rtc_device *rtcdev;
0064     void __iomem *base;
0065 };
0066
0067 static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm)
0068 {
0069     tm->tm_sec = readl(rtc->base + RZN1_RTC_SECC);
0070     tm->tm_min = readl(rtc->base + RZN1_RTC_MINC);
0071     tm->tm_hour = readl(rtc->base + RZN1_RTC_HOURC);
0072     tm->tm_wday = readl(rtc->base + RZN1_RTC_WEEKC);
0073     tm->tm_mday = readl(rtc->base + RZN1_RTC_DAYC);
0074     tm->tm_mon = readl(rtc->base + RZN1_RTC_MONTHC);
0075     tm->tm_year = readl(rtc->base + RZN1_RTC_YEARC);
0076 }
0077
0078 static unsigned int rzn1_rtc_tm_to_wday(struct rtc_time *tm)
0079 {
0080     time64_t time;
0081     unsigned int days;
0082     u32 secs;
0083
0084     time = rtc_tm_to_time64(tm);
0085     days = div_s64_rem(time, 86400, &secs);
0086
0087     /* day of the week, 1970-01-01 was a Thursday */
0088     return (days + 4) % 7;
0089 }
0090
0091 static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm)
0092 {
0093     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0094     u32 val, secs;
0095
0096     /*
0097      * The RTC was not started or is stopped and thus does not carry the
0098      * proper time/date.
0099      */
0100     val = readl(rtc->base + RZN1_RTC_CTL2);
0101     if (val & RZN1_RTC_CTL2_STOPPED)
0102         return -EINVAL;
0103
0104     rzn1_rtc_get_time_snapshot(rtc, tm);
0105     secs = readl(rtc->base + RZN1_RTC_SECC);
0106     if (tm->tm_sec != secs)
0107         rzn1_rtc_get_time_snapshot(rtc, tm);
0108
0109     tm->tm_sec = bcd2bin(tm->tm_sec);
0110     tm->tm_min = bcd2bin(tm->tm_min);
0111     tm->tm_hour = bcd2bin(tm->tm_hour);
0112     tm->tm_wday = bcd2bin(tm->tm_wday);
0113     tm->tm_mday = bcd2bin(tm->tm_mday);
0114     tm->tm_mon = bcd2bin(tm->tm_mon);
0115     tm->tm_year = bcd2bin(tm->tm_year);
0116
0117     return 0;
0118 }
0119
0120 static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm)
0121 {
0122     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0123     u32 val;
0124     int ret;
0125
0126     tm->tm_sec = bin2bcd(tm->tm_sec);
0127     tm->tm_min = bin2bcd(tm->tm_min);
0128     tm->tm_hour = bin2bcd(tm->tm_hour);
0129     tm->tm_wday = bin2bcd(rzn1_rtc_tm_to_wday(tm));
0130     tm->tm_mday = bin2bcd(tm->tm_mday);
0131     tm->tm_mon = bin2bcd(tm->tm_mon);
0132     tm->tm_year = bin2bcd(tm->tm_year);
0133
0134     val = readl(rtc->base + RZN1_RTC_CTL2);
0135     if (!(val & RZN1_RTC_CTL2_STOPPED)) {
0136         /* Hold the counter if it was counting up */
0137         writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2);
0138
0139         /* Wait for the counter to stop: two 32k clock cycles */
0140         usleep_range(61, 100);
0141         ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
0142                      val & RZN1_RTC_CTL2_WST, 0, 100);
0143         if (ret)
0144             return ret;
0145     }
0146
0147     writel(tm->tm_sec, rtc->base + RZN1_RTC_SEC);
0148     writel(tm->tm_min, rtc->base + RZN1_RTC_MIN);
0149     writel(tm->tm_hour, rtc->base + RZN1_RTC_HOUR);
0150     writel(tm->tm_wday, rtc->base + RZN1_RTC_WEEK);
0151     writel(tm->tm_mday, rtc->base + RZN1_RTC_DAY);
0152     writel(tm->tm_mon, rtc->base + RZN1_RTC_MONTH);
0153     writel(tm->tm_year, rtc->base + RZN1_RTC_YEAR);
0154     writel(0, rtc->base + RZN1_RTC_CTL2);
0155
0156     return 0;
0157 }
0158
0159 static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id)
0160 {
0161     struct rzn1_rtc *rtc = dev_id;
0162
0163     rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
0164
0165     return IRQ_HANDLED;
0166 }
0167
0168 static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
0169 {
0170     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0171     u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
0172
0173     if (enable)
0174         ctl1 |= RZN1_RTC_CTL1_ALME;
0175     else
0176         ctl1 &= ~RZN1_RTC_CTL1_ALME;
0177
0178     writel(ctl1, rtc->base + RZN1_RTC_CTL1);
0179
0180     return 0;
0181 }
0182
0183 static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0184 {
0185     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0186     struct rtc_time *tm = &alrm->time;
0187     unsigned int min, hour, wday, delta_days;
0188     time64_t alarm;
0189     u32 ctl1;
0190     int ret;
0191
0192     ret = rzn1_rtc_read_time(dev, tm);
0193     if (ret)
0194         return ret;
0195
0196     min = readl(rtc->base + RZN1_RTC_ALM);
0197     hour = readl(rtc->base + RZN1_RTC_ALH);
0198     wday = readl(rtc->base + RZN1_RTC_ALW);
0199
0200     tm->tm_sec = 0;
0201     tm->tm_min = bcd2bin(min);
0202     tm->tm_hour = bcd2bin(hour);
0203     delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7;
0204     tm->tm_wday = fls(wday) - 1;
0205
0206     if (delta_days) {
0207         alarm = rtc_tm_to_time64(tm) + (delta_days * 86400);
0208         rtc_time64_to_tm(alarm, tm);
0209     }
0210
0211     ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
0212     alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME);
0213
0214     return 0;
0215 }
0216
0217 static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0218 {
0219     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0220     struct rtc_time *tm = &alrm->time, tm_now;
0221     unsigned long alarm, farest;
0222     unsigned int days_ahead, wday;
0223     int ret;
0224
0225     ret = rzn1_rtc_read_time(dev, &tm_now);
0226     if (ret)
0227         return ret;
0228
0229     /* We cannot set alarms more than one week ahead */
0230     farest = rtc_tm_to_time64(&tm_now) + (7 * 86400);
0231     alarm = rtc_tm_to_time64(tm);
0232     if (time_after(alarm, farest))
0233         return -ERANGE;
0234
0235     /* Convert alarm day into week day */
0236     days_ahead = tm->tm_mday - tm_now.tm_mday;
0237     wday = (tm_now.tm_wday + days_ahead) % 7;
0238
0239     writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);
0240     writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH);
0241     writel(BIT(wday), rtc->base + RZN1_RTC_ALW);
0242
0243     rzn1_rtc_alarm_irq_enable(dev, alrm->enabled);
0244
0245     return 0;
0246 }
0247
0248 static int rzn1_rtc_read_offset(struct device *dev, long *offset)
0249 {
0250     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0251     unsigned int ppb_per_step;
0252     bool subtract;
0253     u32 val;
0254
0255     val = readl(rtc->base + RZN1_RTC_SUBU);
0256     ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051;
0257     subtract = val & RZN1_RTC_SUBU_DECR;
0258     val &= 0x3F;
0259
0260     if (!val)
0261         *offset = 0;
0262     else if (subtract)
0263         *offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
0264     else
0265         *offset = (val - 1) * ppb_per_step;
0266
0267     return 0;
0268 }
0269
0270 static int rzn1_rtc_set_offset(struct device *dev, long offset)
0271 {
0272     struct rzn1_rtc *rtc = dev_get_drvdata(dev);
0273     int stepsh, stepsl, steps;
0274     u32 subu = 0, ctl2;
0275     int ret;
0276
0277     /*
0278      * Check which resolution mode (every 20 or 60s) can be used.
0279      * Between 2 and 124 clock pulses can be added or substracted.
0280      *
0281      * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is
0282      * close to 3051 ppb. In 60s mode, the resolution is closer to 1017.
0283      */
0284     stepsh = DIV_ROUND_CLOSEST(offset, 1017);
0285     stepsl = DIV_ROUND_CLOSEST(offset, 3051);
0286
0287     if (stepsh >= -0x3E && stepsh <= 0x3E) {
0288         /* 1017 ppb per step */
0289         steps = stepsh;
0290         subu |= RZN1_RTC_SUBU_DEV;
0291     } else if (stepsl >= -0x3E && stepsl <= 0x3E) {
0292         /* 3051 ppb per step */
0293         steps = stepsl;
0294     } else {
0295         return -ERANGE;
0296     }
0297
0298     if (!steps)
0299         return 0;
0300
0301     if (steps > 0) {
0302         subu |= steps + 1;
0303     } else {
0304         subu |= RZN1_RTC_SUBU_DECR;
0305         subu |= (~(-steps - 1)) & 0x3F;
0306     }
0307
0308     ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,
0309                  !(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000);
0310     if (ret)
0311         return ret;
0312
0313     writel(subu, rtc->base + RZN1_RTC_SUBU);
0314
0315     return 0;
0316 }
0317
0318 static const struct rtc_class_ops rzn1_rtc_ops = {
0319     .read_time = rzn1_rtc_read_time,
0320     .set_time = rzn1_rtc_set_time,
0321     .read_alarm = rzn1_rtc_read_alarm,
0322     .set_alarm = rzn1_rtc_set_alarm,
0323     .alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
0324     .read_offset = rzn1_rtc_read_offset,
0325     .set_offset = rzn1_rtc_set_offset,
0326 };
0327
0328 static int rzn1_rtc_probe(struct platform_device *pdev)
0329 {
0330     struct rzn1_rtc *rtc;
0331     int alarm_irq;
0332     int ret;
0333
0334     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
0335     if (!rtc)
0336         return -ENOMEM;
0337
0338     platform_set_drvdata(pdev, rtc);
0339
0340     rtc->base = devm_platform_ioremap_resource(pdev, 0);
0341     if (IS_ERR(rtc->base))
0342         return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n");
0343
0344     alarm_irq = platform_get_irq(pdev, 0);
0345     if (alarm_irq < 0)
0346         return alarm_irq;
0347
0348     rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
0349     if (IS_ERR(rtc->rtcdev))
0350         return PTR_ERR(rtc->rtcdev);
0351
0352     rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
0353     rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
0354     rtc->rtcdev->ops = &rzn1_rtc_ops;
0355     set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features);
0356     clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features);
0357
0358     devm_pm_runtime_enable(&pdev->dev);
0359     ret = pm_runtime_resume_and_get(&pdev->dev);
0360     if (ret < 0)
0361         return ret;
0362
0363     /*
0364      * Ensure the clock counter is enabled.
0365      * Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
0366      */
0367     writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
0368            rtc->base + RZN1_RTC_CTL0);
0369
0370     /* Disable all interrupts */
0371     writel(0, rtc->base + RZN1_RTC_CTL1);
0372
0373     ret = devm_request_irq(&pdev->dev, alarm_irq, rzn1_rtc_alarm_irq, 0,
0374                    dev_name(&pdev->dev), rtc);
0375     if (ret) {
0376         dev_err(&pdev->dev, "RTC timer interrupt not available\n");
0377         goto dis_runtime_pm;
0378     }
0379
0380     ret = devm_rtc_register_device(rtc->rtcdev);
0381     if (ret)
0382         goto dis_runtime_pm;
0383
0384     return 0;
0385
0386 dis_runtime_pm:
0387     pm_runtime_put(&pdev->dev);
0388
0389     return ret;
0390 }
0391
0392 static int rzn1_rtc_remove(struct platform_device *pdev)
0393 {
0394     pm_runtime_put(&pdev->dev);
0395
0396     return 0;
0397 }
0398
0399 static const struct of_device_id rzn1_rtc_of_match[] = {
0400     { .compatible   = "renesas,rzn1-rtc" },
0401     {},
0402 };
0403 MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match);
0404
0405 static struct platform_driver rzn1_rtc_driver = {
0406     .probe = rzn1_rtc_probe,
0407     .remove = rzn1_rtc_remove,
0408     .driver = {
0409         .name   = "rzn1-rtc",
0410         .of_match_table = rzn1_rtc_of_match,
0411     },
0412 };
0413 module_platform_driver(rzn1_rtc_driver);
0414
0415 MODULE_AUTHOR("Michel Pollet <Michel.Pollet@bp.renesas.com");
0416 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com");
0417 MODULE_DESCRIPTION("RZ/N1 RTC driver");
0418 MODULE_LICENSE("GPL");