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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RTC driver for the Micro Crystal RV3032
0004  *
0005  * Copyright (C) 2020 Micro Crystal SA
0006  *
0007  * Alexandre Belloni <alexandre.belloni@bootlin.com>
0008  *
0009  */
0010 
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/bcd.h>
0014 #include <linux/bitfield.h>
0015 #include <linux/bitops.h>
0016 #include <linux/hwmon.h>
0017 #include <linux/i2c.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/kernel.h>
0020 #include <linux/log2.h>
0021 #include <linux/module.h>
0022 #include <linux/of_device.h>
0023 #include <linux/regmap.h>
0024 #include <linux/rtc.h>
0025 
0026 #define RV3032_SEC          0x01
0027 #define RV3032_MIN          0x02
0028 #define RV3032_HOUR         0x03
0029 #define RV3032_WDAY         0x04
0030 #define RV3032_DAY          0x05
0031 #define RV3032_MONTH            0x06
0032 #define RV3032_YEAR         0x07
0033 #define RV3032_ALARM_MIN        0x08
0034 #define RV3032_ALARM_HOUR       0x09
0035 #define RV3032_ALARM_DAY        0x0A
0036 #define RV3032_STATUS           0x0D
0037 #define RV3032_TLSB         0x0E
0038 #define RV3032_TMSB         0x0F
0039 #define RV3032_CTRL1            0x10
0040 #define RV3032_CTRL2            0x11
0041 #define RV3032_CTRL3            0x12
0042 #define RV3032_TS_CTRL          0x13
0043 #define RV3032_CLK_IRQ          0x14
0044 #define RV3032_EEPROM_ADDR      0x3D
0045 #define RV3032_EEPROM_DATA      0x3E
0046 #define RV3032_EEPROM_CMD       0x3F
0047 #define RV3032_RAM1         0x40
0048 #define RV3032_PMU          0xC0
0049 #define RV3032_OFFSET           0xC1
0050 #define RV3032_CLKOUT1          0xC2
0051 #define RV3032_CLKOUT2          0xC3
0052 #define RV3032_TREF0            0xC4
0053 #define RV3032_TREF1            0xC5
0054 
0055 #define RV3032_STATUS_VLF       BIT(0)
0056 #define RV3032_STATUS_PORF      BIT(1)
0057 #define RV3032_STATUS_EVF       BIT(2)
0058 #define RV3032_STATUS_AF        BIT(3)
0059 #define RV3032_STATUS_TF        BIT(4)
0060 #define RV3032_STATUS_UF        BIT(5)
0061 #define RV3032_STATUS_TLF       BIT(6)
0062 #define RV3032_STATUS_THF       BIT(7)
0063 
0064 #define RV3032_TLSB_CLKF        BIT(1)
0065 #define RV3032_TLSB_EEBUSY      BIT(2)
0066 #define RV3032_TLSB_TEMP        GENMASK(7, 4)
0067 
0068 #define RV3032_CLKOUT2_HFD_MSK      GENMASK(4, 0)
0069 #define RV3032_CLKOUT2_FD_MSK       GENMASK(6, 5)
0070 #define RV3032_CLKOUT2_OS       BIT(7)
0071 
0072 #define RV3032_CTRL1_EERD       BIT(3)
0073 #define RV3032_CTRL1_WADA       BIT(5)
0074 
0075 #define RV3032_CTRL2_STOP       BIT(0)
0076 #define RV3032_CTRL2_EIE        BIT(2)
0077 #define RV3032_CTRL2_AIE        BIT(3)
0078 #define RV3032_CTRL2_TIE        BIT(4)
0079 #define RV3032_CTRL2_UIE        BIT(5)
0080 #define RV3032_CTRL2_CLKIE      BIT(6)
0081 #define RV3032_CTRL2_TSE        BIT(7)
0082 
0083 #define RV3032_PMU_TCM          GENMASK(1, 0)
0084 #define RV3032_PMU_TCR          GENMASK(3, 2)
0085 #define RV3032_PMU_BSM          GENMASK(5, 4)
0086 #define RV3032_PMU_NCLKE        BIT(6)
0087 
0088 #define RV3032_PMU_BSM_DSM      1
0089 #define RV3032_PMU_BSM_LSM      2
0090 
0091 #define RV3032_OFFSET_MSK       GENMASK(5, 0)
0092 
0093 #define RV3032_EVT_CTRL_TSR     BIT(2)
0094 
0095 #define RV3032_EEPROM_CMD_UPDATE    0x11
0096 #define RV3032_EEPROM_CMD_WRITE     0x21
0097 #define RV3032_EEPROM_CMD_READ      0x22
0098 
0099 #define RV3032_EEPROM_USER      0xCB
0100 
0101 #define RV3032_EEBUSY_POLL      10000
0102 #define RV3032_EEBUSY_TIMEOUT       100000
0103 
0104 #define OFFSET_STEP_PPT         238419
0105 
0106 struct rv3032_data {
0107     struct regmap *regmap;
0108     struct rtc_device *rtc;
0109     bool trickle_charger_set;
0110 #ifdef CONFIG_COMMON_CLK
0111     struct clk_hw clkout_hw;
0112 #endif
0113 };
0114 
0115 static u16 rv3032_trickle_resistors[] = {1000, 2000, 7000, 11000};
0116 static u16 rv3032_trickle_voltages[] = {0, 1750, 3000, 4400};
0117 
0118 static int rv3032_exit_eerd(struct rv3032_data *rv3032, u32 eerd)
0119 {
0120     if (eerd)
0121         return 0;
0122 
0123     return regmap_update_bits(rv3032->regmap, RV3032_CTRL1, RV3032_CTRL1_EERD, 0);
0124 }
0125 
0126 static int rv3032_enter_eerd(struct rv3032_data *rv3032, u32 *eerd)
0127 {
0128     u32 ctrl1, status;
0129     int ret;
0130 
0131     ret = regmap_read(rv3032->regmap, RV3032_CTRL1, &ctrl1);
0132     if (ret)
0133         return ret;
0134 
0135     *eerd = ctrl1 & RV3032_CTRL1_EERD;
0136     if (*eerd)
0137         return 0;
0138 
0139     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
0140                  RV3032_CTRL1_EERD, RV3032_CTRL1_EERD);
0141     if (ret)
0142         return ret;
0143 
0144     ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
0145                        !(status & RV3032_TLSB_EEBUSY),
0146                        RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0147     if (ret) {
0148         rv3032_exit_eerd(rv3032, *eerd);
0149 
0150         return ret;
0151     }
0152 
0153     return 0;
0154 }
0155 
0156 static int rv3032_update_cfg(struct rv3032_data *rv3032, unsigned int reg,
0157                  unsigned int mask, unsigned int val)
0158 {
0159     u32 status, eerd;
0160     int ret;
0161 
0162     ret = rv3032_enter_eerd(rv3032, &eerd);
0163     if (ret)
0164         return ret;
0165 
0166     ret = regmap_update_bits(rv3032->regmap, reg, mask, val);
0167     if (ret)
0168         goto exit_eerd;
0169 
0170     ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
0171     if (ret)
0172         goto exit_eerd;
0173 
0174     usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
0175 
0176     ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
0177                        !(status & RV3032_TLSB_EEBUSY),
0178                        RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0179 
0180 exit_eerd:
0181     rv3032_exit_eerd(rv3032, eerd);
0182 
0183     return ret;
0184 }
0185 
0186 static irqreturn_t rv3032_handle_irq(int irq, void *dev_id)
0187 {
0188     struct rv3032_data *rv3032 = dev_id;
0189     unsigned long events = 0;
0190     u32 status = 0, ctrl = 0;
0191 
0192     if (regmap_read(rv3032->regmap, RV3032_STATUS, &status) < 0 ||
0193         status == 0) {
0194         return IRQ_NONE;
0195     }
0196 
0197     if (status & RV3032_STATUS_TF) {
0198         status |= RV3032_STATUS_TF;
0199         ctrl |= RV3032_CTRL2_TIE;
0200         events |= RTC_PF;
0201     }
0202 
0203     if (status & RV3032_STATUS_AF) {
0204         status |= RV3032_STATUS_AF;
0205         ctrl |= RV3032_CTRL2_AIE;
0206         events |= RTC_AF;
0207     }
0208 
0209     if (status & RV3032_STATUS_UF) {
0210         status |= RV3032_STATUS_UF;
0211         ctrl |= RV3032_CTRL2_UIE;
0212         events |= RTC_UF;
0213     }
0214 
0215     if (events) {
0216         rtc_update_irq(rv3032->rtc, 1, events);
0217         regmap_update_bits(rv3032->regmap, RV3032_STATUS, status, 0);
0218         regmap_update_bits(rv3032->regmap, RV3032_CTRL2, ctrl, 0);
0219     }
0220 
0221     return IRQ_HANDLED;
0222 }
0223 
0224 static int rv3032_get_time(struct device *dev, struct rtc_time *tm)
0225 {
0226     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0227     u8 date[7];
0228     int ret, status;
0229 
0230     ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
0231     if (ret < 0)
0232         return ret;
0233 
0234     if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
0235         return -EINVAL;
0236 
0237     ret = regmap_bulk_read(rv3032->regmap, RV3032_SEC, date, sizeof(date));
0238     if (ret)
0239         return ret;
0240 
0241     tm->tm_sec  = bcd2bin(date[0] & 0x7f);
0242     tm->tm_min  = bcd2bin(date[1] & 0x7f);
0243     tm->tm_hour = bcd2bin(date[2] & 0x3f);
0244     tm->tm_wday = date[3] & 0x7;
0245     tm->tm_mday = bcd2bin(date[4] & 0x3f);
0246     tm->tm_mon  = bcd2bin(date[5] & 0x1f) - 1;
0247     tm->tm_year = bcd2bin(date[6]) + 100;
0248 
0249     return 0;
0250 }
0251 
0252 static int rv3032_set_time(struct device *dev, struct rtc_time *tm)
0253 {
0254     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0255     u8 date[7];
0256     int ret;
0257 
0258     date[0] = bin2bcd(tm->tm_sec);
0259     date[1] = bin2bcd(tm->tm_min);
0260     date[2] = bin2bcd(tm->tm_hour);
0261     date[3] = tm->tm_wday;
0262     date[4] = bin2bcd(tm->tm_mday);
0263     date[5] = bin2bcd(tm->tm_mon + 1);
0264     date[6] = bin2bcd(tm->tm_year - 100);
0265 
0266     ret = regmap_bulk_write(rv3032->regmap, RV3032_SEC, date,
0267                 sizeof(date));
0268     if (ret)
0269         return ret;
0270 
0271     ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
0272                  RV3032_STATUS_PORF | RV3032_STATUS_VLF, 0);
0273 
0274     return ret;
0275 }
0276 
0277 static int rv3032_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0278 {
0279     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0280     u8 alarmvals[3];
0281     int status, ctrl, ret;
0282 
0283     ret = regmap_bulk_read(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
0284                    sizeof(alarmvals));
0285     if (ret)
0286         return ret;
0287 
0288     ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
0289     if (ret < 0)
0290         return ret;
0291 
0292     ret = regmap_read(rv3032->regmap, RV3032_CTRL2, &ctrl);
0293     if (ret < 0)
0294         return ret;
0295 
0296     alrm->time.tm_sec  = 0;
0297     alrm->time.tm_min  = bcd2bin(alarmvals[0] & 0x7f);
0298     alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
0299     alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
0300 
0301     alrm->enabled = !!(ctrl & RV3032_CTRL2_AIE);
0302     alrm->pending = (status & RV3032_STATUS_AF) && alrm->enabled;
0303 
0304     return 0;
0305 }
0306 
0307 static int rv3032_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0308 {
0309     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0310     u8 alarmvals[3];
0311     u8 ctrl = 0;
0312     int ret;
0313 
0314     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
0315                  RV3032_CTRL2_AIE | RV3032_CTRL2_UIE, 0);
0316     if (ret)
0317         return ret;
0318 
0319     alarmvals[0] = bin2bcd(alrm->time.tm_min);
0320     alarmvals[1] = bin2bcd(alrm->time.tm_hour);
0321     alarmvals[2] = bin2bcd(alrm->time.tm_mday);
0322 
0323     ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
0324                  RV3032_STATUS_AF, 0);
0325     if (ret)
0326         return ret;
0327 
0328     ret = regmap_bulk_write(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
0329                 sizeof(alarmvals));
0330     if (ret)
0331         return ret;
0332 
0333     if (alrm->enabled) {
0334         if (rv3032->rtc->uie_rtctimer.enabled)
0335             ctrl |= RV3032_CTRL2_UIE;
0336         if (rv3032->rtc->aie_timer.enabled)
0337             ctrl |= RV3032_CTRL2_AIE;
0338     }
0339 
0340     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
0341                  RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
0342 
0343     return ret;
0344 }
0345 
0346 static int rv3032_alarm_irq_enable(struct device *dev, unsigned int enabled)
0347 {
0348     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0349     int ctrl = 0, ret;
0350 
0351     if (enabled) {
0352         if (rv3032->rtc->uie_rtctimer.enabled)
0353             ctrl |= RV3032_CTRL2_UIE;
0354         if (rv3032->rtc->aie_timer.enabled)
0355             ctrl |= RV3032_CTRL2_AIE;
0356     }
0357 
0358     ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
0359                  RV3032_STATUS_AF | RV3032_STATUS_UF, 0);
0360     if (ret)
0361         return ret;
0362 
0363     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
0364                  RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
0365     if (ret)
0366         return ret;
0367 
0368     return 0;
0369 }
0370 
0371 static int rv3032_read_offset(struct device *dev, long *offset)
0372 {
0373     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0374     int ret, value, steps;
0375 
0376     ret = regmap_read(rv3032->regmap, RV3032_OFFSET, &value);
0377     if (ret < 0)
0378         return ret;
0379 
0380     steps = sign_extend32(FIELD_GET(RV3032_OFFSET_MSK, value), 5);
0381 
0382     *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
0383 
0384     return 0;
0385 }
0386 
0387 static int rv3032_set_offset(struct device *dev, long offset)
0388 {
0389     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0390 
0391     offset = clamp(offset, -7629L, 7391L) * 1000;
0392     offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
0393 
0394     return rv3032_update_cfg(rv3032, RV3032_OFFSET, RV3032_OFFSET_MSK,
0395                  FIELD_PREP(RV3032_OFFSET_MSK, offset));
0396 }
0397 
0398 static int rv3032_param_get(struct device *dev, struct rtc_param *param)
0399 {
0400     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0401     int ret;
0402 
0403     switch(param->param) {
0404         u32 value;
0405 
0406     case RTC_PARAM_BACKUP_SWITCH_MODE:
0407         ret = regmap_read(rv3032->regmap, RV3032_PMU, &value);
0408         if (ret < 0)
0409             return ret;
0410 
0411         value = FIELD_GET(RV3032_PMU_BSM, value);
0412 
0413         switch(value) {
0414         case RV3032_PMU_BSM_DSM:
0415             param->uvalue = RTC_BSM_DIRECT;
0416             break;
0417         case RV3032_PMU_BSM_LSM:
0418             param->uvalue = RTC_BSM_LEVEL;
0419             break;
0420         default:
0421             param->uvalue = RTC_BSM_DISABLED;
0422         }
0423 
0424         break;
0425 
0426     default:
0427         return -EINVAL;
0428     }
0429 
0430     return 0;
0431 }
0432 
0433 static int rv3032_param_set(struct device *dev, struct rtc_param *param)
0434 {
0435     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0436 
0437     switch(param->param) {
0438         u8 mode;
0439     case RTC_PARAM_BACKUP_SWITCH_MODE:
0440         if (rv3032->trickle_charger_set)
0441             return -EINVAL;
0442 
0443         switch (param->uvalue) {
0444         case RTC_BSM_DISABLED:
0445             mode = 0;
0446             break;
0447         case RTC_BSM_DIRECT:
0448             mode = RV3032_PMU_BSM_DSM;
0449             break;
0450         case RTC_BSM_LEVEL:
0451             mode = RV3032_PMU_BSM_LSM;
0452             break;
0453         default:
0454             return -EINVAL;
0455         }
0456 
0457         return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_BSM,
0458                      FIELD_PREP(RV3032_PMU_BSM, mode));
0459 
0460     default:
0461         return -EINVAL;
0462     }
0463 
0464     return 0;
0465 }
0466 
0467 static int rv3032_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
0468 {
0469     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0470     int status, val = 0, ret = 0;
0471 
0472     switch (cmd) {
0473     case RTC_VL_READ:
0474         ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
0475         if (ret < 0)
0476             return ret;
0477 
0478         if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
0479             val = RTC_VL_DATA_INVALID;
0480         return put_user(val, (unsigned int __user *)arg);
0481 
0482     default:
0483         return -ENOIOCTLCMD;
0484     }
0485 }
0486 
0487 static int rv3032_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes)
0488 {
0489     return regmap_bulk_write(priv, RV3032_RAM1 + offset, val, bytes);
0490 }
0491 
0492 static int rv3032_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes)
0493 {
0494     return regmap_bulk_read(priv, RV3032_RAM1 + offset, val, bytes);
0495 }
0496 
0497 static int rv3032_eeprom_write(void *priv, unsigned int offset, void *val, size_t bytes)
0498 {
0499     struct rv3032_data *rv3032 = priv;
0500     u32 status, eerd;
0501     int i, ret;
0502     u8 *buf = val;
0503 
0504     ret = rv3032_enter_eerd(rv3032, &eerd);
0505     if (ret)
0506         return ret;
0507 
0508     for (i = 0; i < bytes; i++) {
0509         ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
0510                    RV3032_EEPROM_USER + offset + i);
0511         if (ret)
0512             goto exit_eerd;
0513 
0514         ret = regmap_write(rv3032->regmap, RV3032_EEPROM_DATA, buf[i]);
0515         if (ret)
0516             goto exit_eerd;
0517 
0518         ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
0519                    RV3032_EEPROM_CMD_WRITE);
0520         if (ret)
0521             goto exit_eerd;
0522 
0523         usleep_range(RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0524 
0525         ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
0526                            !(status & RV3032_TLSB_EEBUSY),
0527                            RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0528         if (ret)
0529             goto exit_eerd;
0530     }
0531 
0532 exit_eerd:
0533     rv3032_exit_eerd(rv3032, eerd);
0534 
0535     return ret;
0536 }
0537 
0538 static int rv3032_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes)
0539 {
0540     struct rv3032_data *rv3032 = priv;
0541     u32 status, eerd, data;
0542     int i, ret;
0543     u8 *buf = val;
0544 
0545     ret = rv3032_enter_eerd(rv3032, &eerd);
0546     if (ret)
0547         return ret;
0548 
0549     for (i = 0; i < bytes; i++) {
0550         ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
0551                    RV3032_EEPROM_USER + offset + i);
0552         if (ret)
0553             goto exit_eerd;
0554 
0555         ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
0556                    RV3032_EEPROM_CMD_READ);
0557         if (ret)
0558             goto exit_eerd;
0559 
0560         ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
0561                            !(status & RV3032_TLSB_EEBUSY),
0562                            RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0563         if (ret)
0564             goto exit_eerd;
0565 
0566         ret = regmap_read(rv3032->regmap, RV3032_EEPROM_DATA, &data);
0567         if (ret)
0568             goto exit_eerd;
0569         buf[i] = data;
0570     }
0571 
0572 exit_eerd:
0573     rv3032_exit_eerd(rv3032, eerd);
0574 
0575     return ret;
0576 }
0577 
0578 static int rv3032_trickle_charger_setup(struct device *dev, struct rv3032_data *rv3032)
0579 {
0580     u32 val, ohms, voltage;
0581     int i;
0582 
0583     val = FIELD_PREP(RV3032_PMU_TCM, 1) | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_DSM);
0584     if (!device_property_read_u32(dev, "trickle-voltage-millivolt", &voltage)) {
0585         for (i = 0; i < ARRAY_SIZE(rv3032_trickle_voltages); i++)
0586             if (voltage == rv3032_trickle_voltages[i])
0587                 break;
0588         if (i < ARRAY_SIZE(rv3032_trickle_voltages))
0589             val = FIELD_PREP(RV3032_PMU_TCM, i) |
0590                   FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_LSM);
0591     }
0592 
0593     if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
0594         return 0;
0595 
0596     for (i = 0; i < ARRAY_SIZE(rv3032_trickle_resistors); i++)
0597         if (ohms == rv3032_trickle_resistors[i])
0598             break;
0599 
0600     if (i >= ARRAY_SIZE(rv3032_trickle_resistors)) {
0601         dev_warn(dev, "invalid trickle resistor value\n");
0602 
0603         return 0;
0604     }
0605 
0606     rv3032->trickle_charger_set = true;
0607 
0608     return rv3032_update_cfg(rv3032, RV3032_PMU,
0609                  RV3032_PMU_TCR | RV3032_PMU_TCM | RV3032_PMU_BSM,
0610                  val | FIELD_PREP(RV3032_PMU_TCR, i));
0611 }
0612 
0613 #ifdef CONFIG_COMMON_CLK
0614 #define clkout_hw_to_rv3032(hw) container_of(hw, struct rv3032_data, clkout_hw)
0615 
0616 static int clkout_xtal_rates[] = {
0617     32768,
0618     1024,
0619     64,
0620     1,
0621 };
0622 
0623 #define RV3032_HFD_STEP 8192
0624 
0625 static unsigned long rv3032_clkout_recalc_rate(struct clk_hw *hw,
0626                            unsigned long parent_rate)
0627 {
0628     int clkout, ret;
0629     struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
0630 
0631     ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout);
0632     if (ret < 0)
0633         return 0;
0634 
0635     if (clkout & RV3032_CLKOUT2_OS) {
0636         unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8;
0637 
0638         ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout);
0639         if (ret < 0)
0640             return 0;
0641 
0642         rate += clkout + 1;
0643 
0644         return rate * RV3032_HFD_STEP;
0645     }
0646 
0647     return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)];
0648 }
0649 
0650 static long rv3032_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
0651                      unsigned long *prate)
0652 {
0653     int i, hfd;
0654 
0655     if (rate < RV3032_HFD_STEP)
0656         for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++)
0657             if (clkout_xtal_rates[i] <= rate)
0658                 return clkout_xtal_rates[i];
0659 
0660     hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
0661 
0662     return RV3032_HFD_STEP * clamp(hfd, 0, 8192);
0663 }
0664 
0665 static int rv3032_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
0666                   unsigned long parent_rate)
0667 {
0668     struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
0669     u32 status, eerd;
0670     int i, hfd, ret;
0671 
0672     for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) {
0673         if (clkout_xtal_rates[i] == rate) {
0674             return rv3032_update_cfg(rv3032, RV3032_CLKOUT2, 0xff,
0675                          FIELD_PREP(RV3032_CLKOUT2_FD_MSK, i));
0676         }
0677     }
0678 
0679     hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
0680     hfd = clamp(hfd, 1, 8192) - 1;
0681 
0682     ret = rv3032_enter_eerd(rv3032, &eerd);
0683     if (ret)
0684         return ret;
0685 
0686     ret = regmap_write(rv3032->regmap, RV3032_CLKOUT1, hfd & 0xff);
0687     if (ret)
0688         goto exit_eerd;
0689 
0690     ret = regmap_write(rv3032->regmap, RV3032_CLKOUT2, RV3032_CLKOUT2_OS |
0691                 FIELD_PREP(RV3032_CLKOUT2_HFD_MSK, hfd >> 8));
0692     if (ret)
0693         goto exit_eerd;
0694 
0695     ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
0696     if (ret)
0697         goto exit_eerd;
0698 
0699     usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
0700 
0701     ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
0702                        !(status & RV3032_TLSB_EEBUSY),
0703                        RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
0704 
0705 exit_eerd:
0706     rv3032_exit_eerd(rv3032, eerd);
0707 
0708     return ret;
0709 }
0710 
0711 static int rv3032_clkout_prepare(struct clk_hw *hw)
0712 {
0713     struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
0714 
0715     return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, 0);
0716 }
0717 
0718 static void rv3032_clkout_unprepare(struct clk_hw *hw)
0719 {
0720     struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
0721 
0722     rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, RV3032_PMU_NCLKE);
0723 }
0724 
0725 static int rv3032_clkout_is_prepared(struct clk_hw *hw)
0726 {
0727     int val, ret;
0728     struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
0729 
0730     ret = regmap_read(rv3032->regmap, RV3032_PMU, &val);
0731     if (ret < 0)
0732         return ret;
0733 
0734     return !(val & RV3032_PMU_NCLKE);
0735 }
0736 
0737 static const struct clk_ops rv3032_clkout_ops = {
0738     .prepare = rv3032_clkout_prepare,
0739     .unprepare = rv3032_clkout_unprepare,
0740     .is_prepared = rv3032_clkout_is_prepared,
0741     .recalc_rate = rv3032_clkout_recalc_rate,
0742     .round_rate = rv3032_clkout_round_rate,
0743     .set_rate = rv3032_clkout_set_rate,
0744 };
0745 
0746 static int rv3032_clkout_register_clk(struct rv3032_data *rv3032,
0747                       struct i2c_client *client)
0748 {
0749     int ret;
0750     struct clk *clk;
0751     struct clk_init_data init;
0752     struct device_node *node = client->dev.of_node;
0753 
0754     ret = regmap_update_bits(rv3032->regmap, RV3032_TLSB, RV3032_TLSB_CLKF, 0);
0755     if (ret < 0)
0756         return ret;
0757 
0758     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, RV3032_CTRL2_CLKIE, 0);
0759     if (ret < 0)
0760         return ret;
0761 
0762     ret = regmap_write(rv3032->regmap, RV3032_CLK_IRQ, 0);
0763     if (ret < 0)
0764         return ret;
0765 
0766     init.name = "rv3032-clkout";
0767     init.ops = &rv3032_clkout_ops;
0768     init.flags = 0;
0769     init.parent_names = NULL;
0770     init.num_parents = 0;
0771     rv3032->clkout_hw.init = &init;
0772 
0773     of_property_read_string(node, "clock-output-names", &init.name);
0774 
0775     clk = devm_clk_register(&client->dev, &rv3032->clkout_hw);
0776     if (!IS_ERR(clk))
0777         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0778 
0779     return 0;
0780 }
0781 #endif
0782 
0783 static int rv3032_hwmon_read_temp(struct device *dev, long *mC)
0784 {
0785     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0786     u8 buf[2];
0787     int temp, prev = 0;
0788     int ret;
0789 
0790     ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
0791     if (ret)
0792         return ret;
0793 
0794     temp = sign_extend32(buf[1], 7) << 4;
0795     temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
0796 
0797     /* No blocking or shadowing on RV3032_TLSB and RV3032_TMSB */
0798     do {
0799         prev = temp;
0800 
0801         ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
0802         if (ret)
0803             return ret;
0804 
0805         temp = sign_extend32(buf[1], 7) << 4;
0806         temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
0807     } while (temp != prev);
0808 
0809     *mC = (temp * 1000) / 16;
0810 
0811     return 0;
0812 }
0813 
0814 static umode_t rv3032_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
0815                        u32 attr, int channel)
0816 {
0817     if (type != hwmon_temp)
0818         return 0;
0819 
0820     switch (attr) {
0821     case hwmon_temp_input:
0822         return 0444;
0823     default:
0824         return 0;
0825     }
0826 }
0827 
0828 static int rv3032_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
0829                  u32 attr, int channel, long *temp)
0830 {
0831     int err;
0832 
0833     switch (attr) {
0834     case hwmon_temp_input:
0835         err = rv3032_hwmon_read_temp(dev, temp);
0836         break;
0837     default:
0838         err = -EOPNOTSUPP;
0839         break;
0840     }
0841 
0842     return err;
0843 }
0844 
0845 static const struct hwmon_channel_info *rv3032_hwmon_info[] = {
0846     HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
0847     HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
0848     NULL
0849 };
0850 
0851 static const struct hwmon_ops rv3032_hwmon_hwmon_ops = {
0852     .is_visible = rv3032_hwmon_is_visible,
0853     .read = rv3032_hwmon_read,
0854 };
0855 
0856 static const struct hwmon_chip_info rv3032_hwmon_chip_info = {
0857     .ops = &rv3032_hwmon_hwmon_ops,
0858     .info = rv3032_hwmon_info,
0859 };
0860 
0861 static void rv3032_hwmon_register(struct device *dev)
0862 {
0863     struct rv3032_data *rv3032 = dev_get_drvdata(dev);
0864 
0865     if (!IS_REACHABLE(CONFIG_HWMON))
0866         return;
0867 
0868     devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL);
0869 }
0870 
0871 static const struct rtc_class_ops rv3032_rtc_ops = {
0872     .read_time = rv3032_get_time,
0873     .set_time = rv3032_set_time,
0874     .read_offset = rv3032_read_offset,
0875     .set_offset = rv3032_set_offset,
0876     .ioctl = rv3032_ioctl,
0877     .read_alarm = rv3032_get_alarm,
0878     .set_alarm = rv3032_set_alarm,
0879     .alarm_irq_enable = rv3032_alarm_irq_enable,
0880     .param_get = rv3032_param_get,
0881     .param_set = rv3032_param_set,
0882 };
0883 
0884 static const struct regmap_config regmap_config = {
0885     .reg_bits = 8,
0886     .val_bits = 8,
0887     .max_register = 0xCA,
0888 };
0889 
0890 static int rv3032_probe(struct i2c_client *client)
0891 {
0892     struct rv3032_data *rv3032;
0893     int ret, status;
0894     struct nvmem_config nvmem_cfg = {
0895         .name = "rv3032_nvram",
0896         .word_size = 1,
0897         .stride = 1,
0898         .size = 16,
0899         .type = NVMEM_TYPE_BATTERY_BACKED,
0900         .reg_read = rv3032_nvram_read,
0901         .reg_write = rv3032_nvram_write,
0902     };
0903     struct nvmem_config eeprom_cfg = {
0904         .name = "rv3032_eeprom",
0905         .word_size = 1,
0906         .stride = 1,
0907         .size = 32,
0908         .type = NVMEM_TYPE_EEPROM,
0909         .reg_read = rv3032_eeprom_read,
0910         .reg_write = rv3032_eeprom_write,
0911     };
0912 
0913     rv3032 = devm_kzalloc(&client->dev, sizeof(struct rv3032_data),
0914                   GFP_KERNEL);
0915     if (!rv3032)
0916         return -ENOMEM;
0917 
0918     rv3032->regmap = devm_regmap_init_i2c(client, &regmap_config);
0919     if (IS_ERR(rv3032->regmap))
0920         return PTR_ERR(rv3032->regmap);
0921 
0922     i2c_set_clientdata(client, rv3032);
0923 
0924     ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
0925     if (ret < 0)
0926         return ret;
0927 
0928     rv3032->rtc = devm_rtc_allocate_device(&client->dev);
0929     if (IS_ERR(rv3032->rtc))
0930         return PTR_ERR(rv3032->rtc);
0931 
0932     if (client->irq > 0) {
0933         ret = devm_request_threaded_irq(&client->dev, client->irq,
0934                         NULL, rv3032_handle_irq,
0935                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0936                         "rv3032", rv3032);
0937         if (ret) {
0938             dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
0939             client->irq = 0;
0940         }
0941     }
0942     if (!client->irq)
0943         clear_bit(RTC_FEATURE_ALARM, rv3032->rtc->features);
0944 
0945     ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
0946                  RV3032_CTRL1_WADA, RV3032_CTRL1_WADA);
0947     if (ret)
0948         return ret;
0949 
0950     rv3032_trickle_charger_setup(&client->dev, rv3032);
0951 
0952     set_bit(RTC_FEATURE_BACKUP_SWITCH_MODE, rv3032->rtc->features);
0953     set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rv3032->rtc->features);
0954 
0955     rv3032->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0956     rv3032->rtc->range_max = RTC_TIMESTAMP_END_2099;
0957     rv3032->rtc->ops = &rv3032_rtc_ops;
0958     ret = devm_rtc_register_device(rv3032->rtc);
0959     if (ret)
0960         return ret;
0961 
0962     nvmem_cfg.priv = rv3032->regmap;
0963     devm_rtc_nvmem_register(rv3032->rtc, &nvmem_cfg);
0964     eeprom_cfg.priv = rv3032;
0965     devm_rtc_nvmem_register(rv3032->rtc, &eeprom_cfg);
0966 
0967     rv3032->rtc->max_user_freq = 1;
0968 
0969 #ifdef CONFIG_COMMON_CLK
0970     rv3032_clkout_register_clk(rv3032, client);
0971 #endif
0972 
0973     rv3032_hwmon_register(&client->dev);
0974 
0975     return 0;
0976 }
0977 
0978 static const __maybe_unused struct of_device_id rv3032_of_match[] = {
0979     { .compatible = "microcrystal,rv3032", },
0980     { }
0981 };
0982 MODULE_DEVICE_TABLE(of, rv3032_of_match);
0983 
0984 static struct i2c_driver rv3032_driver = {
0985     .driver = {
0986         .name = "rtc-rv3032",
0987         .of_match_table = of_match_ptr(rv3032_of_match),
0988     },
0989     .probe_new  = rv3032_probe,
0990 };
0991 module_i2c_driver(rv3032_driver);
0992 
0993 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
0994 MODULE_DESCRIPTION("Micro Crystal RV3032 RTC driver");
0995 MODULE_LICENSE("GPL v2");
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