drivers/rtc/rtc-rp5c01.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Ricoh RP5C01 RTC Driver
0004  *
0005  *  Copyright 2009 Geert Uytterhoeven
0006  *
0007  *  Based on the A3000 TOD code in arch/m68k/amiga/config.c
0008  *  Copyright (C) 1993 Hamish Macdonald
0009  */
0010
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/rtc.h>
0016 #include <linux/slab.h>
0017
0018
0019 enum {
0020     RP5C01_1_SECOND     = 0x0,  /* MODE 00 */
0021     RP5C01_10_SECOND    = 0x1,  /* MODE 00 */
0022     RP5C01_1_MINUTE     = 0x2,  /* MODE 00 and MODE 01 */
0023     RP5C01_10_MINUTE    = 0x3,  /* MODE 00 and MODE 01 */
0024     RP5C01_1_HOUR       = 0x4,  /* MODE 00 and MODE 01 */
0025     RP5C01_10_HOUR      = 0x5,  /* MODE 00 and MODE 01 */
0026     RP5C01_DAY_OF_WEEK  = 0x6,  /* MODE 00 and MODE 01 */
0027     RP5C01_1_DAY        = 0x7,  /* MODE 00 and MODE 01 */
0028     RP5C01_10_DAY       = 0x8,  /* MODE 00 and MODE 01 */
0029     RP5C01_1_MONTH      = 0x9,  /* MODE 00 */
0030     RP5C01_10_MONTH     = 0xa,  /* MODE 00 */
0031     RP5C01_1_YEAR       = 0xb,  /* MODE 00 */
0032     RP5C01_10_YEAR      = 0xc,  /* MODE 00 */
0033
0034     RP5C01_12_24_SELECT = 0xa,  /* MODE 01 */
0035     RP5C01_LEAP_YEAR    = 0xb,  /* MODE 01 */
0036
0037     RP5C01_MODE     = 0xd,  /* all modes */
0038     RP5C01_TEST     = 0xe,  /* all modes */
0039     RP5C01_RESET        = 0xf,  /* all modes */
0040 };
0041
0042 #define RP5C01_12_24_SELECT_12  (0 << 0)
0043 #define RP5C01_12_24_SELECT_24  (1 << 0)
0044
0045 #define RP5C01_10_HOUR_AM   (0 << 1)
0046 #define RP5C01_10_HOUR_PM   (1 << 1)
0047
0048 #define RP5C01_MODE_TIMER_EN    (1 << 3)    /* timer enable */
0049 #define RP5C01_MODE_ALARM_EN    (1 << 2)    /* alarm enable */
0050
0051 #define RP5C01_MODE_MODE_MASK   (3 << 0)
0052 #define RP5C01_MODE_MODE00  (0 << 0)    /* time */
0053 #define RP5C01_MODE_MODE01  (1 << 0)    /* alarm, 12h/24h, leap year */
0054 #define RP5C01_MODE_RAM_BLOCK10 (2 << 0)    /* RAM 4 bits x 13 */
0055 #define RP5C01_MODE_RAM_BLOCK11 (3 << 0)    /* RAM 4 bits x 13 */
0056
0057 #define RP5C01_RESET_1HZ_PULSE  (1 << 3)
0058 #define RP5C01_RESET_16HZ_PULSE (1 << 2)
0059 #define RP5C01_RESET_SECOND (1 << 1)    /* reset divider stages for */
0060                         /* seconds or smaller units */
0061 #define RP5C01_RESET_ALARM  (1 << 0)    /* reset all alarm registers */
0062
0063
0064 struct rp5c01_priv {
0065     u32 __iomem *regs;
0066     struct rtc_device *rtc;
0067     spinlock_t lock;    /* against concurrent RTC/NVRAM access */
0068 };
0069
0070 static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
0071                        unsigned int reg)
0072 {
0073     return __raw_readl(&priv->regs[reg]) & 0xf;
0074 }
0075
0076 static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val,
0077                 unsigned int reg)
0078 {
0079     __raw_writel(val, &priv->regs[reg]);
0080 }
0081
0082 static void rp5c01_lock(struct rp5c01_priv *priv)
0083 {
0084     rp5c01_write(priv, RP5C01_MODE_MODE00, RP5C01_MODE);
0085 }
0086
0087 static void rp5c01_unlock(struct rp5c01_priv *priv)
0088 {
0089     rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
0090              RP5C01_MODE);
0091 }
0092
0093 static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
0094 {
0095     struct rp5c01_priv *priv = dev_get_drvdata(dev);
0096
0097     spin_lock_irq(&priv->lock);
0098     rp5c01_lock(priv);
0099
0100     tm->tm_sec  = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
0101               rp5c01_read(priv, RP5C01_1_SECOND);
0102     tm->tm_min  = rp5c01_read(priv, RP5C01_10_MINUTE) * 10 +
0103               rp5c01_read(priv, RP5C01_1_MINUTE);
0104     tm->tm_hour = rp5c01_read(priv, RP5C01_10_HOUR) * 10 +
0105               rp5c01_read(priv, RP5C01_1_HOUR);
0106     tm->tm_mday = rp5c01_read(priv, RP5C01_10_DAY) * 10 +
0107               rp5c01_read(priv, RP5C01_1_DAY);
0108     tm->tm_wday = rp5c01_read(priv, RP5C01_DAY_OF_WEEK);
0109     tm->tm_mon  = rp5c01_read(priv, RP5C01_10_MONTH) * 10 +
0110               rp5c01_read(priv, RP5C01_1_MONTH) - 1;
0111     tm->tm_year = rp5c01_read(priv, RP5C01_10_YEAR) * 10 +
0112               rp5c01_read(priv, RP5C01_1_YEAR);
0113     if (tm->tm_year <= 69)
0114         tm->tm_year += 100;
0115
0116     rp5c01_unlock(priv);
0117     spin_unlock_irq(&priv->lock);
0118
0119     return 0;
0120 }
0121
0122 static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
0123 {
0124     struct rp5c01_priv *priv = dev_get_drvdata(dev);
0125
0126     spin_lock_irq(&priv->lock);
0127     rp5c01_lock(priv);
0128
0129     rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
0130     rp5c01_write(priv, tm->tm_sec % 10, RP5C01_1_SECOND);
0131     rp5c01_write(priv, tm->tm_min / 10, RP5C01_10_MINUTE);
0132     rp5c01_write(priv, tm->tm_min % 10, RP5C01_1_MINUTE);
0133     rp5c01_write(priv, tm->tm_hour / 10, RP5C01_10_HOUR);
0134     rp5c01_write(priv, tm->tm_hour % 10, RP5C01_1_HOUR);
0135     rp5c01_write(priv, tm->tm_mday / 10, RP5C01_10_DAY);
0136     rp5c01_write(priv, tm->tm_mday % 10, RP5C01_1_DAY);
0137     if (tm->tm_wday != -1)
0138         rp5c01_write(priv, tm->tm_wday, RP5C01_DAY_OF_WEEK);
0139     rp5c01_write(priv, (tm->tm_mon + 1) / 10, RP5C01_10_MONTH);
0140     rp5c01_write(priv, (tm->tm_mon + 1) % 10, RP5C01_1_MONTH);
0141     if (tm->tm_year >= 100)
0142         tm->tm_year -= 100;
0143     rp5c01_write(priv, tm->tm_year / 10, RP5C01_10_YEAR);
0144     rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
0145
0146     rp5c01_unlock(priv);
0147     spin_unlock_irq(&priv->lock);
0148     return 0;
0149 }
0150
0151 static const struct rtc_class_ops rp5c01_rtc_ops = {
0152     .read_time  = rp5c01_read_time,
0153     .set_time   = rp5c01_set_time,
0154 };
0155
0156
0157 /*
0158  * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
0159  * We provide access to them like AmigaOS does: the high nibble of each 8-bit
0160  * byte is stored in BLOCK10, the low nibble in BLOCK11.
0161  */
0162
0163 static int rp5c01_nvram_read(void *_priv, unsigned int pos, void *val,
0164                  size_t bytes)
0165 {
0166     struct rp5c01_priv *priv = _priv;
0167     u8 *buf = val;
0168
0169     spin_lock_irq(&priv->lock);
0170
0171     for (; bytes; bytes--) {
0172         u8 data;
0173
0174         rp5c01_write(priv,
0175                  RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
0176                  RP5C01_MODE);
0177         data = rp5c01_read(priv, pos) << 4;
0178         rp5c01_write(priv,
0179                  RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
0180                  RP5C01_MODE);
0181         data |= rp5c01_read(priv, pos++);
0182         rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
0183                  RP5C01_MODE);
0184         *buf++ = data;
0185     }
0186
0187     spin_unlock_irq(&priv->lock);
0188     return 0;
0189 }
0190
0191 static int rp5c01_nvram_write(void *_priv, unsigned int pos, void *val,
0192                   size_t bytes)
0193 {
0194     struct rp5c01_priv *priv = _priv;
0195     u8 *buf = val;
0196
0197     spin_lock_irq(&priv->lock);
0198
0199     for (; bytes; bytes--) {
0200         u8 data = *buf++;
0201
0202         rp5c01_write(priv,
0203                  RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
0204                  RP5C01_MODE);
0205         rp5c01_write(priv, data >> 4, pos);
0206         rp5c01_write(priv,
0207                  RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
0208                  RP5C01_MODE);
0209         rp5c01_write(priv, data & 0xf, pos++);
0210         rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
0211                  RP5C01_MODE);
0212     }
0213
0214     spin_unlock_irq(&priv->lock);
0215     return 0;
0216 }
0217
0218 static int __init rp5c01_rtc_probe(struct platform_device *dev)
0219 {
0220     struct resource *res;
0221     struct rp5c01_priv *priv;
0222     struct rtc_device *rtc;
0223     int error;
0224     struct nvmem_config nvmem_cfg = {
0225         .name = "rp5c01_nvram",
0226         .word_size = 1,
0227         .stride = 1,
0228         .size = RP5C01_MODE,
0229         .reg_read = rp5c01_nvram_read,
0230         .reg_write = rp5c01_nvram_write,
0231     };
0232
0233     res = platform_get_resource(dev, IORESOURCE_MEM, 0);
0234     if (!res)
0235         return -ENODEV;
0236
0237     priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
0238     if (!priv)
0239         return -ENOMEM;
0240
0241     priv->regs = devm_ioremap(&dev->dev, res->start, resource_size(res));
0242     if (!priv->regs)
0243         return -ENOMEM;
0244
0245     spin_lock_init(&priv->lock);
0246
0247     platform_set_drvdata(dev, priv);
0248
0249     rtc = devm_rtc_allocate_device(&dev->dev);
0250     if (IS_ERR(rtc))
0251         return PTR_ERR(rtc);
0252
0253     rtc->ops = &rp5c01_rtc_ops;
0254
0255     priv->rtc = rtc;
0256
0257     nvmem_cfg.priv = priv;
0258     error = devm_rtc_nvmem_register(rtc, &nvmem_cfg);
0259     if (error)
0260         return error;
0261
0262     return devm_rtc_register_device(rtc);
0263 }
0264
0265 static struct platform_driver rp5c01_rtc_driver = {
0266     .driver = {
0267         .name   = "rtc-rp5c01",
0268     },
0269 };
0270
0271 module_platform_driver_probe(rp5c01_rtc_driver, rp5c01_rtc_probe);
0272
0273 MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
0274 MODULE_LICENSE("GPL");
0275 MODULE_DESCRIPTION("Ricoh RP5C01 RTC driver");
0276 MODULE_ALIAS("platform:rtc-rp5c01");