drivers/rtc/rtc-r7301.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * EPSON TOYOCOM RTC-7301SF/DG Driver
0004  *
0005  * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
0006  *
0007  * Based on rtc-rp5c01.c
0008  *
0009  * Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
0010  */
0011
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/delay.h>
0017 #include <linux/regmap.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/rtc.h>
0020
0021 #define DRV_NAME "rtc-r7301"
0022
0023 #define RTC7301_1_SEC       0x0 /* Bank 0 and Band 1 */
0024 #define RTC7301_10_SEC      0x1 /* Bank 0 and Band 1 */
0025 #define RTC7301_AE      BIT(3)
0026 #define RTC7301_1_MIN       0x2 /* Bank 0 and Band 1 */
0027 #define RTC7301_10_MIN      0x3 /* Bank 0 and Band 1 */
0028 #define RTC7301_1_HOUR      0x4 /* Bank 0 and Band 1 */
0029 #define RTC7301_10_HOUR     0x5 /* Bank 0 and Band 1 */
0030 #define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
0031 #define RTC7301_1_DAY       0x7 /* Bank 0 and Band 1 */
0032 #define RTC7301_10_DAY      0x8 /* Bank 0 and Band 1 */
0033 #define RTC7301_1_MONTH     0x9 /* Bank 0 */
0034 #define RTC7301_10_MONTH    0xa /* Bank 0 */
0035 #define RTC7301_1_YEAR      0xb /* Bank 0 */
0036 #define RTC7301_10_YEAR     0xc /* Bank 0 */
0037 #define RTC7301_100_YEAR    0xd /* Bank 0 */
0038 #define RTC7301_1000_YEAR   0xe /* Bank 0 */
0039 #define RTC7301_ALARM_CONTROL   0xe /* Bank 1 */
0040 #define RTC7301_ALARM_CONTROL_AIE   BIT(0)
0041 #define RTC7301_ALARM_CONTROL_AF    BIT(1)
0042 #define RTC7301_TIMER_CONTROL   0xe /* Bank 2 */
0043 #define RTC7301_TIMER_CONTROL_TIE   BIT(0)
0044 #define RTC7301_TIMER_CONTROL_TF    BIT(1)
0045 #define RTC7301_CONTROL     0xf /* All banks */
0046 #define RTC7301_CONTROL_BUSY        BIT(0)
0047 #define RTC7301_CONTROL_STOP        BIT(1)
0048 #define RTC7301_CONTROL_BANK_SEL_0  BIT(2)
0049 #define RTC7301_CONTROL_BANK_SEL_1  BIT(3)
0050
0051 struct rtc7301_priv {
0052     struct regmap *regmap;
0053     int irq;
0054     spinlock_t lock;
0055     u8 bank;
0056 };
0057
0058 static const struct regmap_config rtc7301_regmap_config = {
0059     .reg_bits = 32,
0060     .val_bits = 8,
0061     .reg_stride = 4,
0062 };
0063
0064 static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
0065 {
0066     int reg_stride = regmap_get_reg_stride(priv->regmap);
0067     unsigned int val;
0068
0069     regmap_read(priv->regmap, reg_stride * reg, &val);
0070
0071     return val & 0xf;
0072 }
0073
0074 static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
0075 {
0076     int reg_stride = regmap_get_reg_stride(priv->regmap);
0077
0078     regmap_write(priv->regmap, reg_stride * reg, val);
0079 }
0080
0081 static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
0082                 u8 mask, u8 val)
0083 {
0084     int reg_stride = regmap_get_reg_stride(priv->regmap);
0085
0086     regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
0087 }
0088
0089 static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
0090 {
0091     int retries = 100;
0092
0093     while (retries-- > 0) {
0094         u8 val;
0095
0096         val = rtc7301_read(priv, RTC7301_CONTROL);
0097         if (!(val & RTC7301_CONTROL_BUSY))
0098             return 0;
0099
0100         udelay(300);
0101     }
0102
0103     return -ETIMEDOUT;
0104 }
0105
0106 static void rtc7301_stop(struct rtc7301_priv *priv)
0107 {
0108     rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
0109                 RTC7301_CONTROL_STOP);
0110 }
0111
0112 static void rtc7301_start(struct rtc7301_priv *priv)
0113 {
0114     rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
0115 }
0116
0117 static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
0118 {
0119     u8 val = 0;
0120
0121     if (bank == priv->bank)
0122         return;
0123
0124     if (bank & BIT(0))
0125         val |= RTC7301_CONTROL_BANK_SEL_0;
0126     if (bank & BIT(1))
0127         val |= RTC7301_CONTROL_BANK_SEL_1;
0128
0129     rtc7301_update_bits(priv, RTC7301_CONTROL,
0130                 RTC7301_CONTROL_BANK_SEL_0 |
0131                 RTC7301_CONTROL_BANK_SEL_1, val);
0132
0133     priv->bank = bank;
0134 }
0135
0136 static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
0137                  bool alarm)
0138 {
0139     int year;
0140
0141     tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
0142     tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
0143     tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
0144     tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
0145     tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
0146     tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
0147     tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
0148     tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
0149
0150     if (alarm) {
0151         tm->tm_wday = -1;
0152         tm->tm_mon = -1;
0153         tm->tm_year = -1;
0154         tm->tm_yday = -1;
0155         tm->tm_isdst = -1;
0156         return;
0157     }
0158
0159     tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
0160     tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
0161              rtc7301_read(priv, RTC7301_1_MONTH) - 1;
0162     year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
0163            rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
0164            rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
0165            rtc7301_read(priv, RTC7301_1_YEAR);
0166
0167     tm->tm_year = year - 1900;
0168 }
0169
0170 static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
0171                    bool alarm)
0172 {
0173     int year;
0174
0175     rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
0176     rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
0177
0178     rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
0179     rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
0180
0181     rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
0182     rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
0183
0184     rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
0185     rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
0186
0187     /* Don't care for alarm register */
0188     rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
0189               RTC7301_DAY_OF_WEEK);
0190
0191     if (alarm)
0192         return;
0193
0194     rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
0195     rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
0196
0197     year = tm->tm_year + 1900;
0198
0199     rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
0200     rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
0201     rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
0202     rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
0203 }
0204
0205 static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
0206 {
0207     rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
0208                 RTC7301_ALARM_CONTROL_AF |
0209                 RTC7301_ALARM_CONTROL_AIE,
0210                 enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
0211 }
0212
0213 static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
0214 {
0215     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0216     unsigned long flags;
0217     int err;
0218
0219     spin_lock_irqsave(&priv->lock, flags);
0220
0221     rtc7301_select_bank(priv, 0);
0222
0223     err = rtc7301_wait_while_busy(priv);
0224     if (!err)
0225         rtc7301_get_time(priv, tm, false);
0226
0227     spin_unlock_irqrestore(&priv->lock, flags);
0228
0229     return err;
0230 }
0231
0232 static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
0233 {
0234     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0235     unsigned long flags;
0236
0237     spin_lock_irqsave(&priv->lock, flags);
0238
0239     rtc7301_stop(priv);
0240     udelay(300);
0241     rtc7301_select_bank(priv, 0);
0242     rtc7301_write_time(priv, tm, false);
0243     rtc7301_start(priv);
0244
0245     spin_unlock_irqrestore(&priv->lock, flags);
0246
0247     return 0;
0248 }
0249
0250 static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0251 {
0252     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0253     unsigned long flags;
0254     u8 alrm_ctrl;
0255
0256     if (priv->irq <= 0)
0257         return -EINVAL;
0258
0259     spin_lock_irqsave(&priv->lock, flags);
0260
0261     rtc7301_select_bank(priv, 1);
0262     rtc7301_get_time(priv, &alarm->time, true);
0263
0264     alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
0265
0266     alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
0267     alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
0268
0269     spin_unlock_irqrestore(&priv->lock, flags);
0270
0271     return 0;
0272 }
0273
0274 static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0275 {
0276     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0277     unsigned long flags;
0278
0279     if (priv->irq <= 0)
0280         return -EINVAL;
0281
0282     spin_lock_irqsave(&priv->lock, flags);
0283
0284     rtc7301_select_bank(priv, 1);
0285     rtc7301_write_time(priv, &alarm->time, true);
0286     rtc7301_alarm_irq(priv, alarm->enabled);
0287
0288     spin_unlock_irqrestore(&priv->lock, flags);
0289
0290     return 0;
0291 }
0292
0293 static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
0294 {
0295     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0296     unsigned long flags;
0297
0298     if (priv->irq <= 0)
0299         return -EINVAL;
0300
0301     spin_lock_irqsave(&priv->lock, flags);
0302
0303     rtc7301_select_bank(priv, 1);
0304     rtc7301_alarm_irq(priv, enabled);
0305
0306     spin_unlock_irqrestore(&priv->lock, flags);
0307
0308     return 0;
0309 }
0310
0311 static const struct rtc_class_ops rtc7301_rtc_ops = {
0312     .read_time  = rtc7301_read_time,
0313     .set_time   = rtc7301_set_time,
0314     .read_alarm = rtc7301_read_alarm,
0315     .set_alarm  = rtc7301_set_alarm,
0316     .alarm_irq_enable = rtc7301_alarm_irq_enable,
0317 };
0318
0319 static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
0320 {
0321     struct rtc_device *rtc = dev_id;
0322     struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
0323     irqreturn_t ret = IRQ_NONE;
0324     u8 alrm_ctrl;
0325
0326     spin_lock(&priv->lock);
0327
0328     rtc7301_select_bank(priv, 1);
0329
0330     alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
0331     if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
0332         ret = IRQ_HANDLED;
0333         rtc7301_alarm_irq(priv, false);
0334         rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
0335     }
0336
0337     spin_unlock(&priv->lock);
0338
0339     return ret;
0340 }
0341
0342 static void rtc7301_init(struct rtc7301_priv *priv)
0343 {
0344     unsigned long flags;
0345
0346     spin_lock_irqsave(&priv->lock, flags);
0347
0348     rtc7301_select_bank(priv, 2);
0349     rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
0350
0351     spin_unlock_irqrestore(&priv->lock, flags);
0352 }
0353
0354 static int __init rtc7301_rtc_probe(struct platform_device *dev)
0355 {
0356     void __iomem *regs;
0357     struct rtc7301_priv *priv;
0358     struct rtc_device *rtc;
0359     int ret;
0360
0361     priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
0362     if (!priv)
0363         return -ENOMEM;
0364
0365     regs = devm_platform_ioremap_resource(dev, 0);
0366     if (IS_ERR(regs))
0367         return PTR_ERR(regs);
0368
0369     priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
0370                          &rtc7301_regmap_config);
0371     if (IS_ERR(priv->regmap))
0372         return PTR_ERR(priv->regmap);
0373
0374     priv->irq = platform_get_irq(dev, 0);
0375
0376     spin_lock_init(&priv->lock);
0377     priv->bank = -1;
0378
0379     rtc7301_init(priv);
0380
0381     platform_set_drvdata(dev, priv);
0382
0383     rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
0384                        THIS_MODULE);
0385     if (IS_ERR(rtc))
0386         return PTR_ERR(rtc);
0387
0388     if (priv->irq > 0) {
0389         ret = devm_request_irq(&dev->dev, priv->irq,
0390                        rtc7301_irq_handler, IRQF_SHARED,
0391                        dev_name(&dev->dev), rtc);
0392         if (ret) {
0393             priv->irq = 0;
0394             dev_err(&dev->dev, "unable to request IRQ\n");
0395         } else {
0396             device_set_wakeup_capable(&dev->dev, true);
0397         }
0398     }
0399
0400     return 0;
0401 }
0402
0403 #ifdef CONFIG_PM_SLEEP
0404
0405 static int rtc7301_suspend(struct device *dev)
0406 {
0407     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0408
0409     if (device_may_wakeup(dev))
0410         enable_irq_wake(priv->irq);
0411
0412     return 0;
0413 }
0414
0415 static int rtc7301_resume(struct device *dev)
0416 {
0417     struct rtc7301_priv *priv = dev_get_drvdata(dev);
0418
0419     if (device_may_wakeup(dev))
0420         disable_irq_wake(priv->irq);
0421
0422     return 0;
0423 }
0424
0425 #endif
0426
0427 static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
0428
0429 static const struct of_device_id rtc7301_dt_match[] = {
0430     { .compatible = "epson,rtc7301sf" },
0431     { .compatible = "epson,rtc7301dg" },
0432     {}
0433 };
0434 MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
0435
0436 static struct platform_driver rtc7301_rtc_driver = {
0437     .driver = {
0438         .name = DRV_NAME,
0439         .of_match_table = rtc7301_dt_match,
0440         .pm = &rtc7301_pm_ops,
0441     },
0442 };
0443
0444 module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
0445
0446 MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
0447 MODULE_LICENSE("GPL");
0448 MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
0449 MODULE_ALIAS("platform:rtc-r7301");