drivers/rtc/rtc-pxa.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Real Time Clock interface for XScale PXA27x and PXA3xx
0004  *
0005  * Copyright (C) 2008 Robert Jarzmik
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/module.h>
0011 #include <linux/rtc.h>
0012 #include <linux/seq_file.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/slab.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018
0019 #include "rtc-sa1100.h"
0020
0021 #define RTC_DEF_DIVIDER     (32768 - 1)
0022 #define RTC_DEF_TRIM        0
0023 #define MAXFREQ_PERIODIC    1000
0024
0025 /*
0026  * PXA Registers and bits definitions
0027  */
0028 #define RTSR_PICE   (1 << 15)   /* Periodic interrupt count enable */
0029 #define RTSR_PIALE  (1 << 14)   /* Periodic interrupt Alarm enable */
0030 #define RTSR_PIAL   (1 << 13)   /* Periodic interrupt detected */
0031 #define RTSR_SWALE2 (1 << 11)   /* RTC stopwatch alarm2 enable */
0032 #define RTSR_SWAL2  (1 << 10)   /* RTC stopwatch alarm2 detected */
0033 #define RTSR_SWALE1 (1 << 9)    /* RTC stopwatch alarm1 enable */
0034 #define RTSR_SWAL1  (1 << 8)    /* RTC stopwatch alarm1 detected */
0035 #define RTSR_RDALE2 (1 << 7)    /* RTC alarm2 enable */
0036 #define RTSR_RDAL2  (1 << 6)    /* RTC alarm2 detected */
0037 #define RTSR_RDALE1 (1 << 5)    /* RTC alarm1 enable */
0038 #define RTSR_RDAL1  (1 << 4)    /* RTC alarm1 detected */
0039 #define RTSR_HZE    (1 << 3)    /* HZ interrupt enable */
0040 #define RTSR_ALE    (1 << 2)    /* RTC alarm interrupt enable */
0041 #define RTSR_HZ     (1 << 1)    /* HZ rising-edge detected */
0042 #define RTSR_AL     (1 << 0)    /* RTC alarm detected */
0043 #define RTSR_TRIG_MASK  (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
0044              | RTSR_SWAL1 | RTSR_SWAL2)
0045 #define RYxR_YEAR_S 9
0046 #define RYxR_YEAR_MASK  (0xfff << RYxR_YEAR_S)
0047 #define RYxR_MONTH_S    5
0048 #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
0049 #define RYxR_DAY_MASK   0x1f
0050 #define RDxR_WOM_S     20
0051 #define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
0052 #define RDxR_DOW_S     17
0053 #define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
0054 #define RDxR_HOUR_S 12
0055 #define RDxR_HOUR_MASK  (0x1f << RDxR_HOUR_S)
0056 #define RDxR_MIN_S  6
0057 #define RDxR_MIN_MASK   (0x3f << RDxR_MIN_S)
0058 #define RDxR_SEC_MASK   0x3f
0059
0060 #define RTSR        0x08
0061 #define RTTR        0x0c
0062 #define RDCR        0x10
0063 #define RYCR        0x14
0064 #define RDAR1       0x18
0065 #define RYAR1       0x1c
0066 #define RTCPICR     0x34
0067 #define PIAR        0x38
0068
0069 #define rtc_readl(pxa_rtc, reg) \
0070     __raw_readl((pxa_rtc)->base + (reg))
0071 #define rtc_writel(pxa_rtc, reg, value) \
0072     __raw_writel((value), (pxa_rtc)->base + (reg))
0073
0074 struct pxa_rtc {
0075     struct sa1100_rtc sa1100_rtc;
0076     struct resource *ress;
0077     void __iomem        *base;
0078     struct rtc_device   *rtc;
0079     spinlock_t      lock;       /* Protects this structure */
0080 };
0081
0082
0083 static u32 ryxr_calc(struct rtc_time *tm)
0084 {
0085     return ((tm->tm_year + 1900) << RYxR_YEAR_S)
0086         | ((tm->tm_mon + 1) << RYxR_MONTH_S)
0087         | tm->tm_mday;
0088 }
0089
0090 static u32 rdxr_calc(struct rtc_time *tm)
0091 {
0092     return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
0093         | (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
0094         | (tm->tm_hour << RDxR_HOUR_S)
0095         | (tm->tm_min << RDxR_MIN_S)
0096         | tm->tm_sec;
0097 }
0098
0099 static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
0100 {
0101     tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
0102     tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
0103     tm->tm_mday = (rycr & RYxR_DAY_MASK);
0104     tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
0105     tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
0106     tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
0107     tm->tm_sec = rdcr & RDxR_SEC_MASK;
0108 }
0109
0110 static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
0111 {
0112     u32 rtsr;
0113
0114     rtsr = rtc_readl(pxa_rtc, RTSR);
0115     rtsr &= ~RTSR_TRIG_MASK;
0116     rtsr &= ~mask;
0117     rtc_writel(pxa_rtc, RTSR, rtsr);
0118 }
0119
0120 static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
0121 {
0122     u32 rtsr;
0123
0124     rtsr = rtc_readl(pxa_rtc, RTSR);
0125     rtsr &= ~RTSR_TRIG_MASK;
0126     rtsr |= mask;
0127     rtc_writel(pxa_rtc, RTSR, rtsr);
0128 }
0129
0130 static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
0131 {
0132     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
0133     u32 rtsr;
0134     unsigned long events = 0;
0135
0136     spin_lock(&pxa_rtc->lock);
0137
0138     /* clear interrupt sources */
0139     rtsr = rtc_readl(pxa_rtc, RTSR);
0140     rtc_writel(pxa_rtc, RTSR, rtsr);
0141
0142     /* temporary disable rtc interrupts */
0143     rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
0144
0145     /* clear alarm interrupt if it has occurred */
0146     if (rtsr & RTSR_RDAL1)
0147         rtsr &= ~RTSR_RDALE1;
0148
0149     /* update irq data & counter */
0150     if (rtsr & RTSR_RDAL1)
0151         events |= RTC_AF | RTC_IRQF;
0152     if (rtsr & RTSR_HZ)
0153         events |= RTC_UF | RTC_IRQF;
0154     if (rtsr & RTSR_PIAL)
0155         events |= RTC_PF | RTC_IRQF;
0156
0157     rtc_update_irq(pxa_rtc->rtc, 1, events);
0158
0159     /* enable back rtc interrupts */
0160     rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
0161
0162     spin_unlock(&pxa_rtc->lock);
0163     return IRQ_HANDLED;
0164 }
0165
0166 static int pxa_rtc_open(struct device *dev)
0167 {
0168     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0169     int ret;
0170
0171     ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
0172               "rtc 1Hz", dev);
0173     if (ret < 0) {
0174         dev_err(dev, "can't get irq %i, err %d\n",
0175             pxa_rtc->sa1100_rtc.irq_1hz, ret);
0176         goto err_irq_1Hz;
0177     }
0178     ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
0179               "rtc Alrm", dev);
0180     if (ret < 0) {
0181         dev_err(dev, "can't get irq %i, err %d\n",
0182             pxa_rtc->sa1100_rtc.irq_alarm, ret);
0183         goto err_irq_Alrm;
0184     }
0185
0186     return 0;
0187
0188 err_irq_Alrm:
0189     free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
0190 err_irq_1Hz:
0191     return ret;
0192 }
0193
0194 static void pxa_rtc_release(struct device *dev)
0195 {
0196     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0197
0198     spin_lock_irq(&pxa_rtc->lock);
0199     rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
0200     spin_unlock_irq(&pxa_rtc->lock);
0201
0202     free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
0203     free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
0204 }
0205
0206 static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
0207 {
0208     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0209
0210     spin_lock_irq(&pxa_rtc->lock);
0211
0212     if (enabled)
0213         rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
0214     else
0215         rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
0216
0217     spin_unlock_irq(&pxa_rtc->lock);
0218     return 0;
0219 }
0220
0221 static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
0222 {
0223     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0224     u32 rycr, rdcr;
0225
0226     rycr = rtc_readl(pxa_rtc, RYCR);
0227     rdcr = rtc_readl(pxa_rtc, RDCR);
0228
0229     tm_calc(rycr, rdcr, tm);
0230     return 0;
0231 }
0232
0233 static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
0234 {
0235     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0236
0237     rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
0238     rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
0239
0240     return 0;
0241 }
0242
0243 static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0244 {
0245     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0246     u32 rtsr, ryar, rdar;
0247
0248     ryar = rtc_readl(pxa_rtc, RYAR1);
0249     rdar = rtc_readl(pxa_rtc, RDAR1);
0250     tm_calc(ryar, rdar, &alrm->time);
0251
0252     rtsr = rtc_readl(pxa_rtc, RTSR);
0253     alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
0254     alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
0255     return 0;
0256 }
0257
0258 static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0259 {
0260     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0261     u32 rtsr;
0262
0263     spin_lock_irq(&pxa_rtc->lock);
0264
0265     rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
0266     rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
0267
0268     rtsr = rtc_readl(pxa_rtc, RTSR);
0269     if (alrm->enabled)
0270         rtsr |= RTSR_RDALE1;
0271     else
0272         rtsr &= ~RTSR_RDALE1;
0273     rtc_writel(pxa_rtc, RTSR, rtsr);
0274
0275     spin_unlock_irq(&pxa_rtc->lock);
0276
0277     return 0;
0278 }
0279
0280 static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
0281 {
0282     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0283
0284     seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
0285     seq_printf(seq, "update_IRQ\t: %s\n",
0286            (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
0287     seq_printf(seq, "periodic_IRQ\t: %s\n",
0288            (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
0289     seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
0290
0291     return 0;
0292 }
0293
0294 static const struct rtc_class_ops pxa_rtc_ops = {
0295     .read_time = pxa_rtc_read_time,
0296     .set_time = pxa_rtc_set_time,
0297     .read_alarm = pxa_rtc_read_alarm,
0298     .set_alarm = pxa_rtc_set_alarm,
0299     .alarm_irq_enable = pxa_alarm_irq_enable,
0300     .proc = pxa_rtc_proc,
0301 };
0302
0303 static int __init pxa_rtc_probe(struct platform_device *pdev)
0304 {
0305     struct device *dev = &pdev->dev;
0306     struct pxa_rtc *pxa_rtc;
0307     struct sa1100_rtc *sa1100_rtc;
0308     int ret;
0309
0310     pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
0311     if (!pxa_rtc)
0312         return -ENOMEM;
0313     sa1100_rtc = &pxa_rtc->sa1100_rtc;
0314
0315     spin_lock_init(&pxa_rtc->lock);
0316     platform_set_drvdata(pdev, pxa_rtc);
0317
0318     pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0319     if (!pxa_rtc->ress) {
0320         dev_err(dev, "No I/O memory resource defined\n");
0321         return -ENXIO;
0322     }
0323
0324     sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
0325     if (sa1100_rtc->irq_1hz < 0)
0326         return -ENXIO;
0327     sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
0328     if (sa1100_rtc->irq_alarm < 0)
0329         return -ENXIO;
0330
0331     sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
0332     if (IS_ERR(sa1100_rtc->rtc))
0333         return PTR_ERR(sa1100_rtc->rtc);
0334
0335     pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
0336                 resource_size(pxa_rtc->ress));
0337     if (!pxa_rtc->base) {
0338         dev_err(dev, "Unable to map pxa RTC I/O memory\n");
0339         return -ENOMEM;
0340     }
0341
0342     pxa_rtc_open(dev);
0343
0344     sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
0345     sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
0346     sa1100_rtc->rtar = pxa_rtc->base + 0x4;
0347     sa1100_rtc->rttr = pxa_rtc->base + 0xc;
0348     ret = sa1100_rtc_init(pdev, sa1100_rtc);
0349     if (ret) {
0350         dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
0351         return ret;
0352     }
0353
0354     rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
0355
0356     pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
0357                         &pxa_rtc_ops, THIS_MODULE);
0358     if (IS_ERR(pxa_rtc->rtc)) {
0359         ret = PTR_ERR(pxa_rtc->rtc);
0360         dev_err(dev, "Failed to register RTC device -> %d\n", ret);
0361         return ret;
0362     }
0363
0364     device_init_wakeup(dev, 1);
0365
0366     return 0;
0367 }
0368
0369 static int __exit pxa_rtc_remove(struct platform_device *pdev)
0370 {
0371     struct device *dev = &pdev->dev;
0372
0373     pxa_rtc_release(dev);
0374     return 0;
0375 }
0376
0377 #ifdef CONFIG_OF
0378 static const struct of_device_id pxa_rtc_dt_ids[] = {
0379     { .compatible = "marvell,pxa-rtc" },
0380     {}
0381 };
0382 MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
0383 #endif
0384
0385 #ifdef CONFIG_PM_SLEEP
0386 static int pxa_rtc_suspend(struct device *dev)
0387 {
0388     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0389
0390     if (device_may_wakeup(dev))
0391         enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
0392     return 0;
0393 }
0394
0395 static int pxa_rtc_resume(struct device *dev)
0396 {
0397     struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
0398
0399     if (device_may_wakeup(dev))
0400         disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
0401     return 0;
0402 }
0403 #endif
0404
0405 static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
0406
0407 static struct platform_driver pxa_rtc_driver = {
0408     .remove     = __exit_p(pxa_rtc_remove),
0409     .driver     = {
0410         .name   = "pxa-rtc",
0411         .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
0412         .pm = &pxa_rtc_pm_ops,
0413     },
0414 };
0415
0416 module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
0417
0418 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
0419 MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
0420 MODULE_LICENSE("GPL");
0421 MODULE_ALIAS("platform:pxa-rtc");