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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
0003  */
0004 #include <linux/of.h>
0005 #include <linux/module.h>
0006 #include <linux/init.h>
0007 #include <linux/rtc.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pm.h>
0010 #include <linux/pm_wakeirq.h>
0011 #include <linux/regmap.h>
0012 #include <linux/slab.h>
0013 #include <linux/spinlock.h>
0014 
0015 /* RTC Register offsets from RTC CTRL REG */
0016 #define PM8XXX_ALARM_CTRL_OFFSET    0x01
0017 #define PM8XXX_RTC_WRITE_OFFSET     0x02
0018 #define PM8XXX_RTC_READ_OFFSET      0x06
0019 #define PM8XXX_ALARM_RW_OFFSET      0x0A
0020 
0021 /* RTC_CTRL register bit fields */
0022 #define PM8xxx_RTC_ENABLE       BIT(7)
0023 #define PM8xxx_RTC_ALARM_CLEAR      BIT(0)
0024 #define PM8xxx_RTC_ALARM_ENABLE     BIT(7)
0025 
0026 #define NUM_8_BIT_RTC_REGS      0x4
0027 
0028 /**
0029  * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
0030  * @ctrl: base address of control register
0031  * @write: base address of write register
0032  * @read: base address of read register
0033  * @alarm_ctrl: base address of alarm control register
0034  * @alarm_ctrl2: base address of alarm control2 register
0035  * @alarm_rw: base address of alarm read-write register
0036  * @alarm_en: alarm enable mask
0037  */
0038 struct pm8xxx_rtc_regs {
0039     unsigned int ctrl;
0040     unsigned int write;
0041     unsigned int read;
0042     unsigned int alarm_ctrl;
0043     unsigned int alarm_ctrl2;
0044     unsigned int alarm_rw;
0045     unsigned int alarm_en;
0046 };
0047 
0048 /**
0049  * struct pm8xxx_rtc -  rtc driver internal structure
0050  * @rtc:        rtc device for this driver.
0051  * @regmap:     regmap used to access RTC registers
0052  * @allow_set_time: indicates whether writing to the RTC is allowed
0053  * @rtc_alarm_irq:  rtc alarm irq number.
0054  * @regs:       rtc registers description.
0055  * @rtc_dev:        device structure.
0056  * @ctrl_reg_lock:  spinlock protecting access to ctrl_reg.
0057  */
0058 struct pm8xxx_rtc {
0059     struct rtc_device *rtc;
0060     struct regmap *regmap;
0061     bool allow_set_time;
0062     int rtc_alarm_irq;
0063     const struct pm8xxx_rtc_regs *regs;
0064     struct device *rtc_dev;
0065     spinlock_t ctrl_reg_lock;
0066 };
0067 
0068 /*
0069  * Steps to write the RTC registers.
0070  * 1. Disable alarm if enabled.
0071  * 2. Disable rtc if enabled.
0072  * 3. Write 0x00 to LSB.
0073  * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
0074  * 5. Enable rtc if disabled in step 2.
0075  * 6. Enable alarm if disabled in step 1.
0076  */
0077 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
0078 {
0079     int rc, i;
0080     unsigned long secs, irq_flags;
0081     u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
0082     unsigned int ctrl_reg, rtc_ctrl_reg;
0083     struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
0084     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0085 
0086     if (!rtc_dd->allow_set_time)
0087         return -ENODEV;
0088 
0089     secs = rtc_tm_to_time64(tm);
0090 
0091     dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
0092 
0093     for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
0094         value[i] = secs & 0xFF;
0095         secs >>= 8;
0096     }
0097 
0098     spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
0099 
0100     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
0101     if (rc)
0102         goto rtc_rw_fail;
0103 
0104     if (ctrl_reg & regs->alarm_en) {
0105         alarm_enabled = 1;
0106         ctrl_reg &= ~regs->alarm_en;
0107         rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
0108         if (rc) {
0109             dev_err(dev, "Write to RTC Alarm control register failed\n");
0110             goto rtc_rw_fail;
0111         }
0112     }
0113 
0114     /* Disable RTC H/w before writing on RTC register */
0115     rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
0116     if (rc)
0117         goto rtc_rw_fail;
0118 
0119     if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
0120         rtc_disabled = 1;
0121         rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
0122         rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
0123         if (rc) {
0124             dev_err(dev, "Write to RTC control register failed\n");
0125             goto rtc_rw_fail;
0126         }
0127     }
0128 
0129     /* Write 0 to Byte[0] */
0130     rc = regmap_write(rtc_dd->regmap, regs->write, 0);
0131     if (rc) {
0132         dev_err(dev, "Write to RTC write data register failed\n");
0133         goto rtc_rw_fail;
0134     }
0135 
0136     /* Write Byte[1], Byte[2], Byte[3] */
0137     rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
0138                    &value[1], sizeof(value) - 1);
0139     if (rc) {
0140         dev_err(dev, "Write to RTC write data register failed\n");
0141         goto rtc_rw_fail;
0142     }
0143 
0144     /* Write Byte[0] */
0145     rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
0146     if (rc) {
0147         dev_err(dev, "Write to RTC write data register failed\n");
0148         goto rtc_rw_fail;
0149     }
0150 
0151     /* Enable RTC H/w after writing on RTC register */
0152     if (rtc_disabled) {
0153         rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
0154         rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
0155         if (rc) {
0156             dev_err(dev, "Write to RTC control register failed\n");
0157             goto rtc_rw_fail;
0158         }
0159     }
0160 
0161     if (alarm_enabled) {
0162         ctrl_reg |= regs->alarm_en;
0163         rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
0164         if (rc) {
0165             dev_err(dev, "Write to RTC Alarm control register failed\n");
0166             goto rtc_rw_fail;
0167         }
0168     }
0169 
0170 rtc_rw_fail:
0171     spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
0172 
0173     return rc;
0174 }
0175 
0176 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
0177 {
0178     int rc;
0179     u8 value[NUM_8_BIT_RTC_REGS];
0180     unsigned long secs;
0181     unsigned int reg;
0182     struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
0183     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0184 
0185     rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
0186     if (rc) {
0187         dev_err(dev, "RTC read data register failed\n");
0188         return rc;
0189     }
0190 
0191     /*
0192      * Read the LSB again and check if there has been a carry over.
0193      * If there is, redo the read operation.
0194      */
0195     rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
0196     if (rc < 0) {
0197         dev_err(dev, "RTC read data register failed\n");
0198         return rc;
0199     }
0200 
0201     if (unlikely(reg < value[0])) {
0202         rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
0203                       value, sizeof(value));
0204         if (rc) {
0205             dev_err(dev, "RTC read data register failed\n");
0206             return rc;
0207         }
0208     }
0209 
0210     secs = value[0] | (value[1] << 8) | (value[2] << 16) |
0211            ((unsigned long)value[3] << 24);
0212 
0213     rtc_time64_to_tm(secs, tm);
0214 
0215     dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
0216 
0217     return 0;
0218 }
0219 
0220 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0221 {
0222     int rc, i;
0223     u8 value[NUM_8_BIT_RTC_REGS];
0224     unsigned int ctrl_reg;
0225     unsigned long secs, irq_flags;
0226     struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
0227     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0228 
0229     secs = rtc_tm_to_time64(&alarm->time);
0230 
0231     for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
0232         value[i] = secs & 0xFF;
0233         secs >>= 8;
0234     }
0235 
0236     spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
0237 
0238     rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
0239                    sizeof(value));
0240     if (rc) {
0241         dev_err(dev, "Write to RTC ALARM register failed\n");
0242         goto rtc_rw_fail;
0243     }
0244 
0245     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
0246     if (rc)
0247         goto rtc_rw_fail;
0248 
0249     if (alarm->enabled)
0250         ctrl_reg |= regs->alarm_en;
0251     else
0252         ctrl_reg &= ~regs->alarm_en;
0253 
0254     rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
0255     if (rc) {
0256         dev_err(dev, "Write to RTC alarm control register failed\n");
0257         goto rtc_rw_fail;
0258     }
0259 
0260     dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
0261         &alarm->time, &alarm->time);
0262 rtc_rw_fail:
0263     spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
0264     return rc;
0265 }
0266 
0267 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0268 {
0269     int rc;
0270     unsigned int ctrl_reg;
0271     u8 value[NUM_8_BIT_RTC_REGS];
0272     unsigned long secs;
0273     struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
0274     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0275 
0276     rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
0277                   sizeof(value));
0278     if (rc) {
0279         dev_err(dev, "RTC alarm time read failed\n");
0280         return rc;
0281     }
0282 
0283     secs = value[0] | (value[1] << 8) | (value[2] << 16) |
0284            ((unsigned long)value[3] << 24);
0285 
0286     rtc_time64_to_tm(secs, &alarm->time);
0287 
0288     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
0289     if (rc) {
0290         dev_err(dev, "Read from RTC alarm control register failed\n");
0291         return rc;
0292     }
0293     alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
0294 
0295     dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
0296         &alarm->time, &alarm->time);
0297 
0298     return 0;
0299 }
0300 
0301 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
0302 {
0303     int rc;
0304     unsigned long irq_flags;
0305     struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
0306     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0307     unsigned int ctrl_reg;
0308     u8 value[NUM_8_BIT_RTC_REGS] = {0};
0309 
0310     spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
0311 
0312     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
0313     if (rc)
0314         goto rtc_rw_fail;
0315 
0316     if (enable)
0317         ctrl_reg |= regs->alarm_en;
0318     else
0319         ctrl_reg &= ~regs->alarm_en;
0320 
0321     rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
0322     if (rc) {
0323         dev_err(dev, "Write to RTC control register failed\n");
0324         goto rtc_rw_fail;
0325     }
0326 
0327     /* Clear Alarm register */
0328     if (!enable) {
0329         rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
0330                        sizeof(value));
0331         if (rc) {
0332             dev_err(dev, "Clear RTC ALARM register failed\n");
0333             goto rtc_rw_fail;
0334         }
0335     }
0336 
0337 rtc_rw_fail:
0338     spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
0339     return rc;
0340 }
0341 
0342 static const struct rtc_class_ops pm8xxx_rtc_ops = {
0343     .read_time  = pm8xxx_rtc_read_time,
0344     .set_time   = pm8xxx_rtc_set_time,
0345     .set_alarm  = pm8xxx_rtc_set_alarm,
0346     .read_alarm = pm8xxx_rtc_read_alarm,
0347     .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
0348 };
0349 
0350 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
0351 {
0352     struct pm8xxx_rtc *rtc_dd = dev_id;
0353     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0354     unsigned int ctrl_reg;
0355     int rc;
0356 
0357     rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
0358 
0359     spin_lock(&rtc_dd->ctrl_reg_lock);
0360 
0361     /* Clear the alarm enable bit */
0362     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
0363     if (rc) {
0364         spin_unlock(&rtc_dd->ctrl_reg_lock);
0365         goto rtc_alarm_handled;
0366     }
0367 
0368     ctrl_reg &= ~regs->alarm_en;
0369 
0370     rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
0371     if (rc) {
0372         spin_unlock(&rtc_dd->ctrl_reg_lock);
0373         dev_err(rtc_dd->rtc_dev,
0374             "Write to alarm control register failed\n");
0375         goto rtc_alarm_handled;
0376     }
0377 
0378     spin_unlock(&rtc_dd->ctrl_reg_lock);
0379 
0380     /* Clear RTC alarm register */
0381     rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
0382     if (rc) {
0383         dev_err(rtc_dd->rtc_dev,
0384             "RTC Alarm control2 register read failed\n");
0385         goto rtc_alarm_handled;
0386     }
0387 
0388     ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
0389     rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
0390     if (rc)
0391         dev_err(rtc_dd->rtc_dev,
0392             "Write to RTC Alarm control2 register failed\n");
0393 
0394 rtc_alarm_handled:
0395     return IRQ_HANDLED;
0396 }
0397 
0398 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
0399 {
0400     const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
0401     unsigned int ctrl_reg;
0402     int rc;
0403 
0404     /* Check if the RTC is on, else turn it on */
0405     rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
0406     if (rc)
0407         return rc;
0408 
0409     if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
0410         ctrl_reg |= PM8xxx_RTC_ENABLE;
0411         rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
0412         if (rc)
0413             return rc;
0414     }
0415 
0416     return 0;
0417 }
0418 
0419 static const struct pm8xxx_rtc_regs pm8921_regs = {
0420     .ctrl       = 0x11d,
0421     .write      = 0x11f,
0422     .read       = 0x123,
0423     .alarm_rw   = 0x127,
0424     .alarm_ctrl = 0x11d,
0425     .alarm_ctrl2    = 0x11e,
0426     .alarm_en   = BIT(1),
0427 };
0428 
0429 static const struct pm8xxx_rtc_regs pm8058_regs = {
0430     .ctrl       = 0x1e8,
0431     .write      = 0x1ea,
0432     .read       = 0x1ee,
0433     .alarm_rw   = 0x1f2,
0434     .alarm_ctrl = 0x1e8,
0435     .alarm_ctrl2    = 0x1e9,
0436     .alarm_en   = BIT(1),
0437 };
0438 
0439 static const struct pm8xxx_rtc_regs pm8941_regs = {
0440     .ctrl       = 0x6046,
0441     .write      = 0x6040,
0442     .read       = 0x6048,
0443     .alarm_rw   = 0x6140,
0444     .alarm_ctrl = 0x6146,
0445     .alarm_ctrl2    = 0x6148,
0446     .alarm_en   = BIT(7),
0447 };
0448 
0449 static const struct pm8xxx_rtc_regs pmk8350_regs = {
0450     .ctrl       = 0x6146,
0451     .write      = 0x6140,
0452     .read       = 0x6148,
0453     .alarm_rw   = 0x6240,
0454     .alarm_ctrl = 0x6246,
0455     .alarm_ctrl2    = 0x6248,
0456     .alarm_en   = BIT(7),
0457 };
0458 
0459 /*
0460  * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
0461  */
0462 static const struct of_device_id pm8xxx_id_table[] = {
0463     { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
0464     { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
0465     { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
0466     { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
0467     { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
0468     { },
0469 };
0470 MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
0471 
0472 static int pm8xxx_rtc_probe(struct platform_device *pdev)
0473 {
0474     int rc;
0475     struct pm8xxx_rtc *rtc_dd;
0476     const struct of_device_id *match;
0477 
0478     match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
0479     if (!match)
0480         return -ENXIO;
0481 
0482     rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
0483     if (rtc_dd == NULL)
0484         return -ENOMEM;
0485 
0486     /* Initialise spinlock to protect RTC control register */
0487     spin_lock_init(&rtc_dd->ctrl_reg_lock);
0488 
0489     rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
0490     if (!rtc_dd->regmap) {
0491         dev_err(&pdev->dev, "Parent regmap unavailable.\n");
0492         return -ENXIO;
0493     }
0494 
0495     rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
0496     if (rtc_dd->rtc_alarm_irq < 0)
0497         return -ENXIO;
0498 
0499     rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
0500                               "allow-set-time");
0501 
0502     rtc_dd->regs = match->data;
0503     rtc_dd->rtc_dev = &pdev->dev;
0504 
0505     rc = pm8xxx_rtc_enable(rtc_dd);
0506     if (rc)
0507         return rc;
0508 
0509     platform_set_drvdata(pdev, rtc_dd);
0510 
0511     device_init_wakeup(&pdev->dev, 1);
0512 
0513     /* Register the RTC device */
0514     rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
0515     if (IS_ERR(rtc_dd->rtc))
0516         return PTR_ERR(rtc_dd->rtc);
0517 
0518     rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
0519     rtc_dd->rtc->range_max = U32_MAX;
0520 
0521     /* Request the alarm IRQ */
0522     rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
0523                       pm8xxx_alarm_trigger,
0524                       IRQF_TRIGGER_RISING,
0525                       "pm8xxx_rtc_alarm", rtc_dd);
0526     if (rc < 0) {
0527         dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
0528         return rc;
0529     }
0530 
0531     rc = devm_rtc_register_device(rtc_dd->rtc);
0532     if (rc)
0533         return rc;
0534 
0535     rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->rtc_alarm_irq);
0536     if (rc)
0537         return rc;
0538 
0539     return 0;
0540 }
0541 
0542 static int pm8xxx_remove(struct platform_device *pdev)
0543 {
0544     dev_pm_clear_wake_irq(&pdev->dev);
0545     return 0;
0546 }
0547 
0548 static struct platform_driver pm8xxx_rtc_driver = {
0549     .probe      = pm8xxx_rtc_probe,
0550     .remove     = pm8xxx_remove,
0551     .driver = {
0552         .name       = "rtc-pm8xxx",
0553         .of_match_table = pm8xxx_id_table,
0554     },
0555 };
0556 
0557 module_platform_driver(pm8xxx_rtc_driver);
0558 
0559 MODULE_ALIAS("platform:rtc-pm8xxx");
0560 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
0561 MODULE_LICENSE("GPL v2");
0562 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
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