drivers/rtc/rtc-pic32.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * PIC32 RTC driver
0004  *
0005  * Joshua Henderson <joshua.henderson@microchip.com>
0006  * Copyright (C) 2016 Microchip Technology Inc.  All rights reserved.
0007  *
0008  */
0009 #include <linux/init.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/io.h>
0014 #include <linux/slab.h>
0015 #include <linux/clk.h>
0016 #include <linux/rtc.h>
0017 #include <linux/bcd.h>
0018
0019 #include <asm/mach-pic32/pic32.h>
0020
0021 #define PIC32_RTCCON        0x00
0022 #define PIC32_RTCCON_ON     BIT(15)
0023 #define PIC32_RTCCON_SIDL   BIT(13)
0024 #define PIC32_RTCCON_RTCCLKSEL  (3 << 9)
0025 #define PIC32_RTCCON_RTCCLKON   BIT(6)
0026 #define PIC32_RTCCON_RTCWREN    BIT(3)
0027 #define PIC32_RTCCON_RTCSYNC    BIT(2)
0028 #define PIC32_RTCCON_HALFSEC    BIT(1)
0029 #define PIC32_RTCCON_RTCOE  BIT(0)
0030
0031 #define PIC32_RTCALRM       0x10
0032 #define PIC32_RTCALRM_ALRMEN    BIT(15)
0033 #define PIC32_RTCALRM_CHIME BIT(14)
0034 #define PIC32_RTCALRM_PIV   BIT(13)
0035 #define PIC32_RTCALRM_ALARMSYNC BIT(12)
0036 #define PIC32_RTCALRM_AMASK 0x0F00
0037 #define PIC32_RTCALRM_ARPT  0xFF
0038
0039 #define PIC32_RTCHOUR       0x23
0040 #define PIC32_RTCMIN        0x22
0041 #define PIC32_RTCSEC        0x21
0042 #define PIC32_RTCYEAR       0x33
0043 #define PIC32_RTCMON        0x32
0044 #define PIC32_RTCDAY        0x31
0045
0046 #define PIC32_ALRMTIME      0x40
0047 #define PIC32_ALRMDATE      0x50
0048
0049 #define PIC32_ALRMHOUR      0x43
0050 #define PIC32_ALRMMIN       0x42
0051 #define PIC32_ALRMSEC       0x41
0052 #define PIC32_ALRMYEAR      0x53
0053 #define PIC32_ALRMMON       0x52
0054 #define PIC32_ALRMDAY       0x51
0055
0056 struct pic32_rtc_dev {
0057     struct rtc_device   *rtc;
0058     void __iomem        *reg_base;
0059     struct clk      *clk;
0060     spinlock_t      alarm_lock;
0061     int         alarm_irq;
0062     bool            alarm_clk_enabled;
0063 };
0064
0065 static void pic32_rtc_alarm_clk_enable(struct pic32_rtc_dev *pdata,
0066                        bool enable)
0067 {
0068     unsigned long flags;
0069
0070     spin_lock_irqsave(&pdata->alarm_lock, flags);
0071     if (enable) {
0072         if (!pdata->alarm_clk_enabled) {
0073             clk_enable(pdata->clk);
0074             pdata->alarm_clk_enabled = true;
0075         }
0076     } else {
0077         if (pdata->alarm_clk_enabled) {
0078             clk_disable(pdata->clk);
0079             pdata->alarm_clk_enabled = false;
0080         }
0081     }
0082     spin_unlock_irqrestore(&pdata->alarm_lock, flags);
0083 }
0084
0085 static irqreturn_t pic32_rtc_alarmirq(int irq, void *id)
0086 {
0087     struct pic32_rtc_dev *pdata = (struct pic32_rtc_dev *)id;
0088
0089     clk_enable(pdata->clk);
0090     rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
0091     clk_disable(pdata->clk);
0092
0093     pic32_rtc_alarm_clk_enable(pdata, false);
0094
0095     return IRQ_HANDLED;
0096 }
0097
0098 static int pic32_rtc_setaie(struct device *dev, unsigned int enabled)
0099 {
0100     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0101     void __iomem *base = pdata->reg_base;
0102
0103     clk_enable(pdata->clk);
0104
0105     writel(PIC32_RTCALRM_ALRMEN,
0106            base + (enabled ? PIC32_SET(PIC32_RTCALRM) :
0107                PIC32_CLR(PIC32_RTCALRM)));
0108
0109     clk_disable(pdata->clk);
0110
0111     pic32_rtc_alarm_clk_enable(pdata, enabled);
0112
0113     return 0;
0114 }
0115
0116 static int pic32_rtc_setfreq(struct device *dev, int freq)
0117 {
0118     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0119     void __iomem *base = pdata->reg_base;
0120
0121     clk_enable(pdata->clk);
0122
0123     writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM));
0124     writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM));
0125     writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM));
0126
0127     clk_disable(pdata->clk);
0128
0129     return 0;
0130 }
0131
0132 static int pic32_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
0133 {
0134     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0135     void __iomem *base = pdata->reg_base;
0136     unsigned int tries = 0;
0137
0138     clk_enable(pdata->clk);
0139
0140     do {
0141         rtc_tm->tm_hour = readb(base + PIC32_RTCHOUR);
0142         rtc_tm->tm_min = readb(base + PIC32_RTCMIN);
0143         rtc_tm->tm_mon  = readb(base + PIC32_RTCMON);
0144         rtc_tm->tm_mday = readb(base + PIC32_RTCDAY);
0145         rtc_tm->tm_year = readb(base + PIC32_RTCYEAR);
0146         rtc_tm->tm_sec  = readb(base + PIC32_RTCSEC);
0147
0148         /*
0149          * The only way to work out whether the system was mid-update
0150          * when we read it is to check the second counter, and if it
0151          * is zero, then we re-try the entire read.
0152          */
0153         tries += 1;
0154     } while (rtc_tm->tm_sec == 0 && tries < 2);
0155
0156     rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
0157     rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
0158     rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
0159     rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
0160     rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon) - 1;
0161     rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
0162
0163     rtc_tm->tm_year += 100;
0164
0165     dev_dbg(dev, "read time %ptR\n", rtc_tm);
0166
0167     clk_disable(pdata->clk);
0168     return 0;
0169 }
0170
0171 static int pic32_rtc_settime(struct device *dev, struct rtc_time *tm)
0172 {
0173     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0174     void __iomem *base = pdata->reg_base;
0175
0176     dev_dbg(dev, "set time %ptR\n", tm);
0177
0178     clk_enable(pdata->clk);
0179     writeb(bin2bcd(tm->tm_sec),  base + PIC32_RTCSEC);
0180     writeb(bin2bcd(tm->tm_min),  base + PIC32_RTCMIN);
0181     writeb(bin2bcd(tm->tm_hour), base + PIC32_RTCHOUR);
0182     writeb(bin2bcd(tm->tm_mday), base + PIC32_RTCDAY);
0183     writeb(bin2bcd(tm->tm_mon + 1), base + PIC32_RTCMON);
0184     writeb(bin2bcd(tm->tm_year - 100), base + PIC32_RTCYEAR);
0185     clk_disable(pdata->clk);
0186
0187     return 0;
0188 }
0189
0190 static int pic32_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
0191 {
0192     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0193     struct rtc_time *alm_tm = &alrm->time;
0194     void __iomem *base = pdata->reg_base;
0195     unsigned int alm_en;
0196
0197     clk_enable(pdata->clk);
0198     alm_tm->tm_sec  = readb(base + PIC32_ALRMSEC);
0199     alm_tm->tm_min  = readb(base + PIC32_ALRMMIN);
0200     alm_tm->tm_hour = readb(base + PIC32_ALRMHOUR);
0201     alm_tm->tm_mon  = readb(base + PIC32_ALRMMON);
0202     alm_tm->tm_mday = readb(base + PIC32_ALRMDAY);
0203     alm_tm->tm_year = readb(base + PIC32_ALRMYEAR);
0204
0205     alm_en = readb(base + PIC32_RTCALRM);
0206
0207     alrm->enabled = (alm_en & PIC32_RTCALRM_ALRMEN) ? 1 : 0;
0208
0209     dev_dbg(dev, "getalarm: %d, %ptR\n", alm_en, alm_tm);
0210
0211     alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
0212     alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
0213     alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
0214     alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
0215     alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon) - 1;
0216     alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
0217
0218     clk_disable(pdata->clk);
0219     return 0;
0220 }
0221
0222 static int pic32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
0223 {
0224     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0225     struct rtc_time *tm = &alrm->time;
0226     void __iomem *base = pdata->reg_base;
0227
0228     clk_enable(pdata->clk);
0229     dev_dbg(dev, "setalarm: %d, %ptR\n", alrm->enabled, tm);
0230
0231     writel(0x00, base + PIC32_ALRMTIME);
0232     writel(0x00, base + PIC32_ALRMDATE);
0233
0234     pic32_rtc_setaie(dev, alrm->enabled);
0235
0236     clk_disable(pdata->clk);
0237     return 0;
0238 }
0239
0240 static int pic32_rtc_proc(struct device *dev, struct seq_file *seq)
0241 {
0242     struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
0243     void __iomem *base = pdata->reg_base;
0244     unsigned int repeat;
0245
0246     clk_enable(pdata->clk);
0247
0248     repeat = readw(base + PIC32_RTCALRM);
0249     repeat &= PIC32_RTCALRM_ARPT;
0250     seq_printf(seq, "periodic_IRQ\t: %s\n", repeat  ? "yes" : "no");
0251
0252     clk_disable(pdata->clk);
0253     return 0;
0254 }
0255
0256 static const struct rtc_class_ops pic32_rtcops = {
0257     .read_time    = pic32_rtc_gettime,
0258     .set_time     = pic32_rtc_settime,
0259     .read_alarm   = pic32_rtc_getalarm,
0260     .set_alarm    = pic32_rtc_setalarm,
0261     .proc         = pic32_rtc_proc,
0262     .alarm_irq_enable = pic32_rtc_setaie,
0263 };
0264
0265 static void pic32_rtc_enable(struct pic32_rtc_dev *pdata, int en)
0266 {
0267     void __iomem *base = pdata->reg_base;
0268
0269     if (!base)
0270         return;
0271
0272     clk_enable(pdata->clk);
0273     if (!en) {
0274         writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON));
0275     } else {
0276         pic32_syskey_unlock();
0277
0278         writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON));
0279         writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON));
0280
0281         if (!(readl(base + PIC32_RTCCON) & PIC32_RTCCON_ON))
0282             writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON));
0283     }
0284     clk_disable(pdata->clk);
0285 }
0286
0287 static int pic32_rtc_remove(struct platform_device *pdev)
0288 {
0289     struct pic32_rtc_dev *pdata = platform_get_drvdata(pdev);
0290
0291     pic32_rtc_setaie(&pdev->dev, 0);
0292     clk_unprepare(pdata->clk);
0293     pdata->clk = NULL;
0294
0295     return 0;
0296 }
0297
0298 static int pic32_rtc_probe(struct platform_device *pdev)
0299 {
0300     struct pic32_rtc_dev *pdata;
0301     int ret;
0302
0303     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0304     if (!pdata)
0305         return -ENOMEM;
0306
0307     platform_set_drvdata(pdev, pdata);
0308
0309     pdata->alarm_irq = platform_get_irq(pdev, 0);
0310     if (pdata->alarm_irq < 0)
0311         return pdata->alarm_irq;
0312
0313     pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
0314     if (IS_ERR(pdata->reg_base))
0315         return PTR_ERR(pdata->reg_base);
0316
0317     pdata->clk = devm_clk_get(&pdev->dev, NULL);
0318     if (IS_ERR(pdata->clk)) {
0319         dev_err(&pdev->dev, "failed to find rtc clock source\n");
0320         ret = PTR_ERR(pdata->clk);
0321         pdata->clk = NULL;
0322         return ret;
0323     }
0324
0325     spin_lock_init(&pdata->alarm_lock);
0326
0327     clk_prepare_enable(pdata->clk);
0328
0329     pic32_rtc_enable(pdata, 1);
0330
0331     device_init_wakeup(&pdev->dev, 1);
0332
0333     pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
0334     if (IS_ERR(pdata->rtc))
0335         return PTR_ERR(pdata->rtc);
0336
0337     pdata->rtc->ops = &pic32_rtcops;
0338     pdata->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0339     pdata->rtc->range_max = RTC_TIMESTAMP_END_2099;
0340
0341     ret = devm_rtc_register_device(pdata->rtc);
0342     if (ret)
0343         goto err_nortc;
0344
0345     pdata->rtc->max_user_freq = 128;
0346
0347     pic32_rtc_setfreq(&pdev->dev, 1);
0348     ret = devm_request_irq(&pdev->dev, pdata->alarm_irq,
0349                    pic32_rtc_alarmirq, 0,
0350                    dev_name(&pdev->dev), pdata);
0351     if (ret) {
0352         dev_err(&pdev->dev,
0353             "IRQ %d error %d\n", pdata->alarm_irq, ret);
0354         goto err_nortc;
0355     }
0356
0357     clk_disable(pdata->clk);
0358
0359     return 0;
0360
0361 err_nortc:
0362     pic32_rtc_enable(pdata, 0);
0363     clk_disable_unprepare(pdata->clk);
0364
0365     return ret;
0366 }
0367
0368 static const struct of_device_id pic32_rtc_dt_ids[] = {
0369     { .compatible = "microchip,pic32mzda-rtc" },
0370     { /* sentinel */ }
0371 };
0372 MODULE_DEVICE_TABLE(of, pic32_rtc_dt_ids);
0373
0374 static struct platform_driver pic32_rtc_driver = {
0375     .probe      = pic32_rtc_probe,
0376     .remove     = pic32_rtc_remove,
0377     .driver     = {
0378         .name   = "pic32-rtc",
0379         .of_match_table = of_match_ptr(pic32_rtc_dt_ids),
0380     },
0381 };
0382 module_platform_driver(pic32_rtc_driver);
0383
0384 MODULE_DESCRIPTION("Microchip PIC32 RTC Driver");
0385 MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
0386 MODULE_LICENSE("GPL");