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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * An I2C driver for the PCF85063 RTC
0004  * Copyright 2014 Rose Technology
0005  *
0006  * Author: Søren Andersen <san@rosetechnology.dk>
0007  * Maintainers: http://www.nslu2-linux.org/
0008  *
0009  * Copyright (C) 2019 Micro Crystal AG
0010  * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
0011  */
0012 #include <linux/clk-provider.h>
0013 #include <linux/i2c.h>
0014 #include <linux/bcd.h>
0015 #include <linux/rtc.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pm_wakeirq.h>
0019 #include <linux/regmap.h>
0020 
0021 /*
0022  * Information for this driver was pulled from the following datasheets.
0023  *
0024  *  https://www.nxp.com/docs/en/data-sheet/PCF85063A.pdf
0025  *  https://www.nxp.com/docs/en/data-sheet/PCF85063TP.pdf
0026  *
0027  *  PCF85063A -- Rev. 7 — 30 March 2018
0028  *  PCF85063TP -- Rev. 4 — 6 May 2015
0029  *
0030  *  https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
0031  *  RV8263 -- Rev. 1.0 — January 2019
0032  */
0033 
0034 #define PCF85063_REG_CTRL1      0x00 /* status */
0035 #define PCF85063_REG_CTRL1_CAP_SEL  BIT(0)
0036 #define PCF85063_REG_CTRL1_STOP     BIT(5)
0037 #define PCF85063_REG_CTRL1_EXT_TEST BIT(7)
0038 
0039 #define PCF85063_REG_CTRL2      0x01
0040 #define PCF85063_CTRL2_AF       BIT(6)
0041 #define PCF85063_CTRL2_AIE      BIT(7)
0042 
0043 #define PCF85063_REG_OFFSET     0x02
0044 #define PCF85063_OFFSET_SIGN_BIT    6   /* 2's complement sign bit */
0045 #define PCF85063_OFFSET_MODE        BIT(7)
0046 #define PCF85063_OFFSET_STEP0       4340
0047 #define PCF85063_OFFSET_STEP1       4069
0048 
0049 #define PCF85063_REG_CLKO_F_MASK    0x07 /* frequency mask */
0050 #define PCF85063_REG_CLKO_F_32768HZ 0x00
0051 #define PCF85063_REG_CLKO_F_OFF     0x07
0052 
0053 #define PCF85063_REG_RAM        0x03
0054 
0055 #define PCF85063_REG_SC         0x04 /* datetime */
0056 #define PCF85063_REG_SC_OS      0x80
0057 
0058 #define PCF85063_REG_ALM_S      0x0b
0059 #define PCF85063_AEN            BIT(7)
0060 
0061 struct pcf85063_config {
0062     struct regmap_config regmap;
0063     unsigned has_alarms:1;
0064     unsigned force_cap_7000:1;
0065 };
0066 
0067 struct pcf85063 {
0068     struct rtc_device   *rtc;
0069     struct regmap       *regmap;
0070 #ifdef CONFIG_COMMON_CLK
0071     struct clk_hw       clkout_hw;
0072 #endif
0073 };
0074 
0075 static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
0076 {
0077     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0078     int rc;
0079     u8 regs[7];
0080 
0081     /*
0082      * while reading, the time/date registers are blocked and not updated
0083      * anymore until the access is finished. To not lose a second
0084      * event, the access must be finished within one second. So, read all
0085      * time/date registers in one turn.
0086      */
0087     rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
0088                   sizeof(regs));
0089     if (rc)
0090         return rc;
0091 
0092     /* if the clock has lost its power it makes no sense to use its time */
0093     if (regs[0] & PCF85063_REG_SC_OS) {
0094         dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
0095         return -EINVAL;
0096     }
0097 
0098     tm->tm_sec = bcd2bin(regs[0] & 0x7F);
0099     tm->tm_min = bcd2bin(regs[1] & 0x7F);
0100     tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
0101     tm->tm_mday = bcd2bin(regs[3] & 0x3F);
0102     tm->tm_wday = regs[4] & 0x07;
0103     tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
0104     tm->tm_year = bcd2bin(regs[6]);
0105     tm->tm_year += 100;
0106 
0107     return 0;
0108 }
0109 
0110 static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
0111 {
0112     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0113     int rc;
0114     u8 regs[7];
0115 
0116     /*
0117      * to accurately set the time, reset the divider chain and keep it in
0118      * reset state until all time/date registers are written
0119      */
0120     rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
0121                 PCF85063_REG_CTRL1_EXT_TEST |
0122                 PCF85063_REG_CTRL1_STOP,
0123                 PCF85063_REG_CTRL1_STOP);
0124     if (rc)
0125         return rc;
0126 
0127     /* hours, minutes and seconds */
0128     regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
0129 
0130     regs[1] = bin2bcd(tm->tm_min);
0131     regs[2] = bin2bcd(tm->tm_hour);
0132 
0133     /* Day of month, 1 - 31 */
0134     regs[3] = bin2bcd(tm->tm_mday);
0135 
0136     /* Day, 0 - 6 */
0137     regs[4] = tm->tm_wday & 0x07;
0138 
0139     /* month, 1 - 12 */
0140     regs[5] = bin2bcd(tm->tm_mon + 1);
0141 
0142     /* year and century */
0143     regs[6] = bin2bcd(tm->tm_year - 100);
0144 
0145     /* write all registers at once */
0146     rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
0147                    regs, sizeof(regs));
0148     if (rc)
0149         return rc;
0150 
0151     /*
0152      * Write the control register as a separate action since the size of
0153      * the register space is different between the PCF85063TP and
0154      * PCF85063A devices.  The rollover point can not be used.
0155      */
0156     return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
0157                   PCF85063_REG_CTRL1_STOP, 0);
0158 }
0159 
0160 static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0161 {
0162     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0163     u8 buf[4];
0164     unsigned int val;
0165     int ret;
0166 
0167     ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
0168                    buf, sizeof(buf));
0169     if (ret)
0170         return ret;
0171 
0172     alrm->time.tm_sec = bcd2bin(buf[0]);
0173     alrm->time.tm_min = bcd2bin(buf[1]);
0174     alrm->time.tm_hour = bcd2bin(buf[2]);
0175     alrm->time.tm_mday = bcd2bin(buf[3]);
0176 
0177     ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
0178     if (ret)
0179         return ret;
0180 
0181     alrm->enabled =  !!(val & PCF85063_CTRL2_AIE);
0182 
0183     return 0;
0184 }
0185 
0186 static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0187 {
0188     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0189     u8 buf[5];
0190     int ret;
0191 
0192     buf[0] = bin2bcd(alrm->time.tm_sec);
0193     buf[1] = bin2bcd(alrm->time.tm_min);
0194     buf[2] = bin2bcd(alrm->time.tm_hour);
0195     buf[3] = bin2bcd(alrm->time.tm_mday);
0196     buf[4] = PCF85063_AEN; /* Do not match on week day */
0197 
0198     ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
0199                  PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
0200     if (ret)
0201         return ret;
0202 
0203     ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
0204                 buf, sizeof(buf));
0205     if (ret)
0206         return ret;
0207 
0208     return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
0209                   PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
0210                   alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
0211 }
0212 
0213 static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
0214                      unsigned int enabled)
0215 {
0216     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0217 
0218     return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
0219                   PCF85063_CTRL2_AIE,
0220                   enabled ? PCF85063_CTRL2_AIE : 0);
0221 }
0222 
0223 static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
0224 {
0225     struct pcf85063 *pcf85063 = dev_id;
0226     unsigned int val;
0227     int err;
0228 
0229     err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
0230     if (err)
0231         return IRQ_NONE;
0232 
0233     if (val & PCF85063_CTRL2_AF) {
0234         rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
0235         regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
0236                    PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
0237                    0);
0238         return IRQ_HANDLED;
0239     }
0240 
0241     return IRQ_NONE;
0242 }
0243 
0244 static int pcf85063_read_offset(struct device *dev, long *offset)
0245 {
0246     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0247     long val;
0248     u32 reg;
0249     int ret;
0250 
0251     ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &reg);
0252     if (ret < 0)
0253         return ret;
0254 
0255     val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
0256                 PCF85063_OFFSET_SIGN_BIT);
0257 
0258     if (reg & PCF85063_OFFSET_MODE)
0259         *offset = val * PCF85063_OFFSET_STEP1;
0260     else
0261         *offset = val * PCF85063_OFFSET_STEP0;
0262 
0263     return 0;
0264 }
0265 
0266 static int pcf85063_set_offset(struct device *dev, long offset)
0267 {
0268     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0269     s8 mode0, mode1, reg;
0270     unsigned int error0, error1;
0271 
0272     if (offset > PCF85063_OFFSET_STEP0 * 63)
0273         return -ERANGE;
0274     if (offset < PCF85063_OFFSET_STEP0 * -64)
0275         return -ERANGE;
0276 
0277     mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
0278     mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
0279 
0280     error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
0281     error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
0282     if (mode1 > 63 || mode1 < -64 || error0 < error1)
0283         reg = mode0 & ~PCF85063_OFFSET_MODE;
0284     else
0285         reg = mode1 | PCF85063_OFFSET_MODE;
0286 
0287     return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
0288 }
0289 
0290 static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
0291               unsigned long arg)
0292 {
0293     struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
0294     int status, ret = 0;
0295 
0296     switch (cmd) {
0297     case RTC_VL_READ:
0298         ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
0299         if (ret < 0)
0300             return ret;
0301 
0302         status = (status & PCF85063_REG_SC_OS) ? RTC_VL_DATA_INVALID : 0;
0303 
0304         return put_user(status, (unsigned int __user *)arg);
0305 
0306     default:
0307         return -ENOIOCTLCMD;
0308     }
0309 }
0310 
0311 static const struct rtc_class_ops pcf85063_rtc_ops = {
0312     .read_time  = pcf85063_rtc_read_time,
0313     .set_time   = pcf85063_rtc_set_time,
0314     .read_offset    = pcf85063_read_offset,
0315     .set_offset = pcf85063_set_offset,
0316     .read_alarm = pcf85063_rtc_read_alarm,
0317     .set_alarm  = pcf85063_rtc_set_alarm,
0318     .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
0319     .ioctl      = pcf85063_ioctl,
0320 };
0321 
0322 static int pcf85063_nvmem_read(void *priv, unsigned int offset,
0323                    void *val, size_t bytes)
0324 {
0325     return regmap_read(priv, PCF85063_REG_RAM, val);
0326 }
0327 
0328 static int pcf85063_nvmem_write(void *priv, unsigned int offset,
0329                 void *val, size_t bytes)
0330 {
0331     return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
0332 }
0333 
0334 static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
0335                      const struct device_node *np,
0336                      unsigned int force_cap)
0337 {
0338     u32 load = 7000;
0339     u8 reg = 0;
0340 
0341     if (force_cap)
0342         load = force_cap;
0343     else
0344         of_property_read_u32(np, "quartz-load-femtofarads", &load);
0345 
0346     switch (load) {
0347     default:
0348         dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
0349              load);
0350         fallthrough;
0351     case 7000:
0352         break;
0353     case 12500:
0354         reg = PCF85063_REG_CTRL1_CAP_SEL;
0355         break;
0356     }
0357 
0358     return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
0359                   PCF85063_REG_CTRL1_CAP_SEL, reg);
0360 }
0361 
0362 #ifdef CONFIG_COMMON_CLK
0363 /*
0364  * Handling of the clkout
0365  */
0366 
0367 #define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
0368 
0369 static int clkout_rates[] = {
0370     32768,
0371     16384,
0372     8192,
0373     4096,
0374     2048,
0375     1024,
0376     1,
0377     0
0378 };
0379 
0380 static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
0381                          unsigned long parent_rate)
0382 {
0383     struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
0384     unsigned int buf;
0385     int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
0386 
0387     if (ret < 0)
0388         return 0;
0389 
0390     buf &= PCF85063_REG_CLKO_F_MASK;
0391     return clkout_rates[buf];
0392 }
0393 
0394 static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
0395                        unsigned long *prate)
0396 {
0397     int i;
0398 
0399     for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
0400         if (clkout_rates[i] <= rate)
0401             return clkout_rates[i];
0402 
0403     return 0;
0404 }
0405 
0406 static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
0407                     unsigned long parent_rate)
0408 {
0409     struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
0410     int i;
0411 
0412     for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
0413         if (clkout_rates[i] == rate)
0414             return regmap_update_bits(pcf85063->regmap,
0415                 PCF85063_REG_CTRL2,
0416                 PCF85063_REG_CLKO_F_MASK, i);
0417 
0418     return -EINVAL;
0419 }
0420 
0421 static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
0422 {
0423     struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
0424     unsigned int buf;
0425     int ret;
0426 
0427     ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
0428     if (ret < 0)
0429         return ret;
0430     buf &= PCF85063_REG_CLKO_F_MASK;
0431 
0432     if (enable) {
0433         if (buf == PCF85063_REG_CLKO_F_OFF)
0434             buf = PCF85063_REG_CLKO_F_32768HZ;
0435         else
0436             return 0;
0437     } else {
0438         if (buf != PCF85063_REG_CLKO_F_OFF)
0439             buf = PCF85063_REG_CLKO_F_OFF;
0440         else
0441             return 0;
0442     }
0443 
0444     return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
0445                     PCF85063_REG_CLKO_F_MASK, buf);
0446 }
0447 
0448 static int pcf85063_clkout_prepare(struct clk_hw *hw)
0449 {
0450     return pcf85063_clkout_control(hw, 1);
0451 }
0452 
0453 static void pcf85063_clkout_unprepare(struct clk_hw *hw)
0454 {
0455     pcf85063_clkout_control(hw, 0);
0456 }
0457 
0458 static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
0459 {
0460     struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
0461     unsigned int buf;
0462     int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
0463 
0464     if (ret < 0)
0465         return 0;
0466 
0467     return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
0468 }
0469 
0470 static const struct clk_ops pcf85063_clkout_ops = {
0471     .prepare = pcf85063_clkout_prepare,
0472     .unprepare = pcf85063_clkout_unprepare,
0473     .is_prepared = pcf85063_clkout_is_prepared,
0474     .recalc_rate = pcf85063_clkout_recalc_rate,
0475     .round_rate = pcf85063_clkout_round_rate,
0476     .set_rate = pcf85063_clkout_set_rate,
0477 };
0478 
0479 static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
0480 {
0481     struct clk *clk;
0482     struct clk_init_data init;
0483     struct device_node *node = pcf85063->rtc->dev.parent->of_node;
0484     struct device_node *fixed_clock;
0485 
0486     fixed_clock = of_get_child_by_name(node, "clock");
0487     if (fixed_clock) {
0488         /*
0489          * skip registering square wave clock when a fixed
0490          * clock has been registered. The fixed clock is
0491          * registered automatically when being referenced.
0492          */
0493         of_node_put(fixed_clock);
0494         return NULL;
0495     }
0496 
0497     init.name = "pcf85063-clkout";
0498     init.ops = &pcf85063_clkout_ops;
0499     init.flags = 0;
0500     init.parent_names = NULL;
0501     init.num_parents = 0;
0502     pcf85063->clkout_hw.init = &init;
0503 
0504     /* optional override of the clockname */
0505     of_property_read_string(node, "clock-output-names", &init.name);
0506 
0507     /* register the clock */
0508     clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
0509 
0510     if (!IS_ERR(clk))
0511         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0512 
0513     return clk;
0514 }
0515 #endif
0516 
0517 enum pcf85063_type {
0518     PCF85063,
0519     PCF85063TP,
0520     PCF85063A,
0521     RV8263,
0522     PCF85063_LAST_ID
0523 };
0524 
0525 static struct pcf85063_config pcf85063_cfg[] = {
0526     [PCF85063] = {
0527         .regmap = {
0528             .reg_bits = 8,
0529             .val_bits = 8,
0530             .max_register = 0x0a,
0531         },
0532     },
0533     [PCF85063TP] = {
0534         .regmap = {
0535             .reg_bits = 8,
0536             .val_bits = 8,
0537             .max_register = 0x0a,
0538         },
0539     },
0540     [PCF85063A] = {
0541         .regmap = {
0542             .reg_bits = 8,
0543             .val_bits = 8,
0544             .max_register = 0x11,
0545         },
0546         .has_alarms = 1,
0547     },
0548     [RV8263] = {
0549         .regmap = {
0550             .reg_bits = 8,
0551             .val_bits = 8,
0552             .max_register = 0x11,
0553         },
0554         .has_alarms = 1,
0555         .force_cap_7000 = 1,
0556     },
0557 };
0558 
0559 static const struct i2c_device_id pcf85063_ids[];
0560 
0561 static int pcf85063_probe(struct i2c_client *client)
0562 {
0563     struct pcf85063 *pcf85063;
0564     unsigned int tmp;
0565     int err;
0566     const struct pcf85063_config *config;
0567     struct nvmem_config nvmem_cfg = {
0568         .name = "pcf85063_nvram",
0569         .reg_read = pcf85063_nvmem_read,
0570         .reg_write = pcf85063_nvmem_write,
0571         .type = NVMEM_TYPE_BATTERY_BACKED,
0572         .size = 1,
0573     };
0574 
0575     dev_dbg(&client->dev, "%s\n", __func__);
0576 
0577     pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
0578                 GFP_KERNEL);
0579     if (!pcf85063)
0580         return -ENOMEM;
0581 
0582     if (client->dev.of_node) {
0583         config = of_device_get_match_data(&client->dev);
0584         if (!config)
0585             return -ENODEV;
0586     } else {
0587         enum pcf85063_type type =
0588             i2c_match_id(pcf85063_ids, client)->driver_data;
0589         if (type >= PCF85063_LAST_ID)
0590             return -ENODEV;
0591         config = &pcf85063_cfg[type];
0592     }
0593 
0594     pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
0595     if (IS_ERR(pcf85063->regmap))
0596         return PTR_ERR(pcf85063->regmap);
0597 
0598     i2c_set_clientdata(client, pcf85063);
0599 
0600     err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
0601     if (err) {
0602         dev_err(&client->dev, "RTC chip is not present\n");
0603         return err;
0604     }
0605 
0606     pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
0607     if (IS_ERR(pcf85063->rtc))
0608         return PTR_ERR(pcf85063->rtc);
0609 
0610     err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
0611                     config->force_cap_7000 ? 7000 : 0);
0612     if (err < 0)
0613         dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
0614              err);
0615 
0616     pcf85063->rtc->ops = &pcf85063_rtc_ops;
0617     pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0618     pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
0619     set_bit(RTC_FEATURE_ALARM_RES_2S, pcf85063->rtc->features);
0620     clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf85063->rtc->features);
0621     clear_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
0622 
0623     if (config->has_alarms && client->irq > 0) {
0624         err = devm_request_threaded_irq(&client->dev, client->irq,
0625                         NULL, pcf85063_rtc_handle_irq,
0626                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0627                         "pcf85063", pcf85063);
0628         if (err) {
0629             dev_warn(&pcf85063->rtc->dev,
0630                  "unable to request IRQ, alarms disabled\n");
0631         } else {
0632             set_bit(RTC_FEATURE_ALARM, pcf85063->rtc->features);
0633             device_init_wakeup(&client->dev, true);
0634             err = dev_pm_set_wake_irq(&client->dev, client->irq);
0635             if (err)
0636                 dev_err(&pcf85063->rtc->dev,
0637                     "failed to enable irq wake\n");
0638         }
0639     }
0640 
0641     nvmem_cfg.priv = pcf85063->regmap;
0642     devm_rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
0643 
0644 #ifdef CONFIG_COMMON_CLK
0645     /* register clk in common clk framework */
0646     pcf85063_clkout_register_clk(pcf85063);
0647 #endif
0648 
0649     return devm_rtc_register_device(pcf85063->rtc);
0650 }
0651 
0652 static const struct i2c_device_id pcf85063_ids[] = {
0653     { "pca85073a", PCF85063A },
0654     { "pcf85063", PCF85063 },
0655     { "pcf85063tp", PCF85063TP },
0656     { "pcf85063a", PCF85063A },
0657     { "rv8263", RV8263 },
0658     {}
0659 };
0660 MODULE_DEVICE_TABLE(i2c, pcf85063_ids);
0661 
0662 #ifdef CONFIG_OF
0663 static const struct of_device_id pcf85063_of_match[] = {
0664     { .compatible = "nxp,pca85073a", .data = &pcf85063_cfg[PCF85063A] },
0665     { .compatible = "nxp,pcf85063", .data = &pcf85063_cfg[PCF85063] },
0666     { .compatible = "nxp,pcf85063tp", .data = &pcf85063_cfg[PCF85063TP] },
0667     { .compatible = "nxp,pcf85063a", .data = &pcf85063_cfg[PCF85063A] },
0668     { .compatible = "microcrystal,rv8263", .data = &pcf85063_cfg[RV8263] },
0669     {}
0670 };
0671 MODULE_DEVICE_TABLE(of, pcf85063_of_match);
0672 #endif
0673 
0674 static struct i2c_driver pcf85063_driver = {
0675     .driver     = {
0676         .name   = "rtc-pcf85063",
0677         .of_match_table = of_match_ptr(pcf85063_of_match),
0678     },
0679     .probe_new  = pcf85063_probe,
0680     .id_table   = pcf85063_ids,
0681 };
0682 
0683 module_i2c_driver(pcf85063_driver);
0684 
0685 MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
0686 MODULE_DESCRIPTION("PCF85063 RTC driver");
0687 MODULE_LICENSE("GPL");
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