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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * An I2C and SPI driver for the NXP PCF2127/29 RTC
0004  * Copyright 2013 Til-Technologies
0005  *
0006  * Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
0007  *
0008  * Watchdog and tamper functions
0009  * Author: Bruno Thomsen <bruno.thomsen@gmail.com>
0010  *
0011  * based on the other drivers in this same directory.
0012  *
0013  * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2127.pdf
0014  */
0015 
0016 #include <linux/i2c.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/bcd.h>
0019 #include <linux/rtc.h>
0020 #include <linux/slab.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/regmap.h>
0025 #include <linux/watchdog.h>
0026 
0027 /* Control register 1 */
0028 #define PCF2127_REG_CTRL1       0x00
0029 #define PCF2127_BIT_CTRL1_POR_OVRD      BIT(3)
0030 #define PCF2127_BIT_CTRL1_TSF1          BIT(4)
0031 /* Control register 2 */
0032 #define PCF2127_REG_CTRL2       0x01
0033 #define PCF2127_BIT_CTRL2_AIE           BIT(1)
0034 #define PCF2127_BIT_CTRL2_TSIE          BIT(2)
0035 #define PCF2127_BIT_CTRL2_AF            BIT(4)
0036 #define PCF2127_BIT_CTRL2_TSF2          BIT(5)
0037 #define PCF2127_BIT_CTRL2_WDTF          BIT(6)
0038 /* Control register 3 */
0039 #define PCF2127_REG_CTRL3       0x02
0040 #define PCF2127_BIT_CTRL3_BLIE          BIT(0)
0041 #define PCF2127_BIT_CTRL3_BIE           BIT(1)
0042 #define PCF2127_BIT_CTRL3_BLF           BIT(2)
0043 #define PCF2127_BIT_CTRL3_BF            BIT(3)
0044 #define PCF2127_BIT_CTRL3_BTSE          BIT(4)
0045 /* Time and date registers */
0046 #define PCF2127_REG_SC          0x03
0047 #define PCF2127_BIT_SC_OSF          BIT(7)
0048 #define PCF2127_REG_MN          0x04
0049 #define PCF2127_REG_HR          0x05
0050 #define PCF2127_REG_DM          0x06
0051 #define PCF2127_REG_DW          0x07
0052 #define PCF2127_REG_MO          0x08
0053 #define PCF2127_REG_YR          0x09
0054 /* Alarm registers */
0055 #define PCF2127_REG_ALARM_SC        0x0A
0056 #define PCF2127_REG_ALARM_MN        0x0B
0057 #define PCF2127_REG_ALARM_HR        0x0C
0058 #define PCF2127_REG_ALARM_DM        0x0D
0059 #define PCF2127_REG_ALARM_DW        0x0E
0060 #define PCF2127_BIT_ALARM_AE            BIT(7)
0061 /* CLKOUT control register */
0062 #define PCF2127_REG_CLKOUT      0x0f
0063 #define PCF2127_BIT_CLKOUT_OTPR         BIT(5)
0064 /* Watchdog registers */
0065 #define PCF2127_REG_WD_CTL      0x10
0066 #define PCF2127_BIT_WD_CTL_TF0          BIT(0)
0067 #define PCF2127_BIT_WD_CTL_TF1          BIT(1)
0068 #define PCF2127_BIT_WD_CTL_CD0          BIT(6)
0069 #define PCF2127_BIT_WD_CTL_CD1          BIT(7)
0070 #define PCF2127_REG_WD_VAL      0x11
0071 /* Tamper timestamp registers */
0072 #define PCF2127_REG_TS_CTRL     0x12
0073 #define PCF2127_BIT_TS_CTRL_TSOFF       BIT(6)
0074 #define PCF2127_BIT_TS_CTRL_TSM         BIT(7)
0075 #define PCF2127_REG_TS_SC       0x13
0076 #define PCF2127_REG_TS_MN       0x14
0077 #define PCF2127_REG_TS_HR       0x15
0078 #define PCF2127_REG_TS_DM       0x16
0079 #define PCF2127_REG_TS_MO       0x17
0080 #define PCF2127_REG_TS_YR       0x18
0081 /*
0082  * RAM registers
0083  * PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
0084  * battery backed and can survive a power outage.
0085  * PCF2129 doesn't have this feature.
0086  */
0087 #define PCF2127_REG_RAM_ADDR_MSB    0x1A
0088 #define PCF2127_REG_RAM_WRT_CMD     0x1C
0089 #define PCF2127_REG_RAM_RD_CMD      0x1D
0090 
0091 /* Watchdog timer value constants */
0092 #define PCF2127_WD_VAL_STOP     0
0093 #define PCF2127_WD_VAL_MIN      2
0094 #define PCF2127_WD_VAL_MAX      255
0095 #define PCF2127_WD_VAL_DEFAULT      60
0096 
0097 /* Mask for currently enabled interrupts */
0098 #define PCF2127_CTRL1_IRQ_MASK (PCF2127_BIT_CTRL1_TSF1)
0099 #define PCF2127_CTRL2_IRQ_MASK ( \
0100         PCF2127_BIT_CTRL2_AF | \
0101         PCF2127_BIT_CTRL2_WDTF | \
0102         PCF2127_BIT_CTRL2_TSF2)
0103 
0104 struct pcf2127 {
0105     struct rtc_device *rtc;
0106     struct watchdog_device wdd;
0107     struct regmap *regmap;
0108     time64_t ts;
0109     bool ts_valid;
0110     bool irq_enabled;
0111 };
0112 
0113 /*
0114  * In the routines that deal directly with the pcf2127 hardware, we use
0115  * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
0116  */
0117 static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
0118 {
0119     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0120     unsigned char buf[10];
0121     int ret;
0122 
0123     /*
0124      * Avoid reading CTRL2 register as it causes WD_VAL register
0125      * value to reset to 0 which means watchdog is stopped.
0126      */
0127     ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3,
0128                    (buf + PCF2127_REG_CTRL3),
0129                    ARRAY_SIZE(buf) - PCF2127_REG_CTRL3);
0130     if (ret) {
0131         dev_err(dev, "%s: read error\n", __func__);
0132         return ret;
0133     }
0134 
0135     if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF)
0136         dev_info(dev,
0137             "low voltage detected, check/replace RTC battery.\n");
0138 
0139     /* Clock integrity is not guaranteed when OSF flag is set. */
0140     if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) {
0141         /*
0142          * no need clear the flag here,
0143          * it will be cleared once the new date is saved
0144          */
0145         dev_warn(dev,
0146              "oscillator stop detected, date/time is not reliable\n");
0147         return -EINVAL;
0148     }
0149 
0150     dev_dbg(dev,
0151         "%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, "
0152         "mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
0153         __func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC],
0154         buf[PCF2127_REG_MN], buf[PCF2127_REG_HR],
0155         buf[PCF2127_REG_DM], buf[PCF2127_REG_DW],
0156         buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]);
0157 
0158     tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
0159     tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
0160     tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */
0161     tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
0162     tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
0163     tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
0164     tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]);
0165     tm->tm_year += 100;
0166 
0167     dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
0168         "mday=%d, mon=%d, year=%d, wday=%d\n",
0169         __func__,
0170         tm->tm_sec, tm->tm_min, tm->tm_hour,
0171         tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
0172 
0173     return 0;
0174 }
0175 
0176 static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
0177 {
0178     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0179     unsigned char buf[7];
0180     int i = 0, err;
0181 
0182     dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
0183         "mday=%d, mon=%d, year=%d, wday=%d\n",
0184         __func__,
0185         tm->tm_sec, tm->tm_min, tm->tm_hour,
0186         tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
0187 
0188     /* hours, minutes and seconds */
0189     buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
0190     buf[i++] = bin2bcd(tm->tm_min);
0191     buf[i++] = bin2bcd(tm->tm_hour);
0192     buf[i++] = bin2bcd(tm->tm_mday);
0193     buf[i++] = tm->tm_wday & 0x07;
0194 
0195     /* month, 1 - 12 */
0196     buf[i++] = bin2bcd(tm->tm_mon + 1);
0197 
0198     /* year */
0199     buf[i++] = bin2bcd(tm->tm_year - 100);
0200 
0201     /* write register's data */
0202     err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i);
0203     if (err) {
0204         dev_err(dev,
0205             "%s: err=%d", __func__, err);
0206         return err;
0207     }
0208 
0209     return 0;
0210 }
0211 
0212 static int pcf2127_rtc_ioctl(struct device *dev,
0213                 unsigned int cmd, unsigned long arg)
0214 {
0215     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0216     int val, touser = 0;
0217     int ret;
0218 
0219     switch (cmd) {
0220     case RTC_VL_READ:
0221         ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
0222         if (ret)
0223             return ret;
0224 
0225         if (val & PCF2127_BIT_CTRL3_BLF)
0226             touser |= RTC_VL_BACKUP_LOW;
0227 
0228         if (val & PCF2127_BIT_CTRL3_BF)
0229             touser |= RTC_VL_BACKUP_SWITCH;
0230 
0231         return put_user(touser, (unsigned int __user *)arg);
0232 
0233     case RTC_VL_CLR:
0234         return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
0235                       PCF2127_BIT_CTRL3_BF, 0);
0236 
0237     default:
0238         return -ENOIOCTLCMD;
0239     }
0240 }
0241 
0242 static int pcf2127_nvmem_read(void *priv, unsigned int offset,
0243                   void *val, size_t bytes)
0244 {
0245     struct pcf2127 *pcf2127 = priv;
0246     int ret;
0247     unsigned char offsetbuf[] = { offset >> 8, offset };
0248 
0249     ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
0250                 offsetbuf, 2);
0251     if (ret)
0252         return ret;
0253 
0254     return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
0255                 val, bytes);
0256 }
0257 
0258 static int pcf2127_nvmem_write(void *priv, unsigned int offset,
0259                    void *val, size_t bytes)
0260 {
0261     struct pcf2127 *pcf2127 = priv;
0262     int ret;
0263     unsigned char offsetbuf[] = { offset >> 8, offset };
0264 
0265     ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
0266                 offsetbuf, 2);
0267     if (ret)
0268         return ret;
0269 
0270     return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
0271                  val, bytes);
0272 }
0273 
0274 /* watchdog driver */
0275 
0276 static int pcf2127_wdt_ping(struct watchdog_device *wdd)
0277 {
0278     struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
0279 
0280     return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
0281 }
0282 
0283 /*
0284  * Restart watchdog timer if feature is active.
0285  *
0286  * Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
0287  * since register also contain control/status flags for other features.
0288  * Always call this function after reading CTRL2 register.
0289  */
0290 static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
0291 {
0292     int ret = 0;
0293 
0294     if (watchdog_active(wdd)) {
0295         ret = pcf2127_wdt_ping(wdd);
0296         if (ret)
0297             dev_err(wdd->parent,
0298                 "%s: watchdog restart failed, ret=%d\n",
0299                 __func__, ret);
0300     }
0301 
0302     return ret;
0303 }
0304 
0305 static int pcf2127_wdt_start(struct watchdog_device *wdd)
0306 {
0307     return pcf2127_wdt_ping(wdd);
0308 }
0309 
0310 static int pcf2127_wdt_stop(struct watchdog_device *wdd)
0311 {
0312     struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
0313 
0314     return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
0315                 PCF2127_WD_VAL_STOP);
0316 }
0317 
0318 static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
0319                    unsigned int new_timeout)
0320 {
0321     dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
0322         new_timeout, wdd->timeout);
0323 
0324     wdd->timeout = new_timeout;
0325 
0326     return pcf2127_wdt_active_ping(wdd);
0327 }
0328 
0329 static const struct watchdog_info pcf2127_wdt_info = {
0330     .identity = "NXP PCF2127/PCF2129 Watchdog",
0331     .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
0332 };
0333 
0334 static const struct watchdog_ops pcf2127_watchdog_ops = {
0335     .owner = THIS_MODULE,
0336     .start = pcf2127_wdt_start,
0337     .stop = pcf2127_wdt_stop,
0338     .ping = pcf2127_wdt_ping,
0339     .set_timeout = pcf2127_wdt_set_timeout,
0340 };
0341 
0342 static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
0343 {
0344     u32 wdd_timeout;
0345     int ret;
0346 
0347     if (!IS_ENABLED(CONFIG_WATCHDOG) ||
0348         !device_property_read_bool(dev, "reset-source"))
0349         return 0;
0350 
0351     pcf2127->wdd.parent = dev;
0352     pcf2127->wdd.info = &pcf2127_wdt_info;
0353     pcf2127->wdd.ops = &pcf2127_watchdog_ops;
0354     pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN;
0355     pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
0356     pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
0357     pcf2127->wdd.min_hw_heartbeat_ms = 500;
0358     pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
0359 
0360     watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
0361 
0362     /* Test if watchdog timer is started by bootloader */
0363     ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
0364     if (ret)
0365         return ret;
0366 
0367     if (wdd_timeout)
0368         set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
0369 
0370     return devm_watchdog_register_device(dev, &pcf2127->wdd);
0371 }
0372 
0373 /* Alarm */
0374 static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0375 {
0376     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0377     u8 buf[5];
0378     unsigned int ctrl2;
0379     int ret;
0380 
0381     ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
0382     if (ret)
0383         return ret;
0384 
0385     ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
0386     if (ret)
0387         return ret;
0388 
0389     ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
0390                    sizeof(buf));
0391     if (ret)
0392         return ret;
0393 
0394     alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
0395     alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
0396 
0397     alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
0398     alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
0399     alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
0400     alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
0401 
0402     return 0;
0403 }
0404 
0405 static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
0406 {
0407     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0408     int ret;
0409 
0410     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
0411                  PCF2127_BIT_CTRL2_AIE,
0412                  enable ? PCF2127_BIT_CTRL2_AIE : 0);
0413     if (ret)
0414         return ret;
0415 
0416     return pcf2127_wdt_active_ping(&pcf2127->wdd);
0417 }
0418 
0419 static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0420 {
0421     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0422     uint8_t buf[5];
0423     int ret;
0424 
0425     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
0426                  PCF2127_BIT_CTRL2_AF, 0);
0427     if (ret)
0428         return ret;
0429 
0430     ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
0431     if (ret)
0432         return ret;
0433 
0434     buf[0] = bin2bcd(alrm->time.tm_sec);
0435     buf[1] = bin2bcd(alrm->time.tm_min);
0436     buf[2] = bin2bcd(alrm->time.tm_hour);
0437     buf[3] = bin2bcd(alrm->time.tm_mday);
0438     buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
0439 
0440     ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
0441                 sizeof(buf));
0442     if (ret)
0443         return ret;
0444 
0445     return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
0446 }
0447 
0448 /*
0449  * This function reads ctrl2 register, caller is responsible for calling
0450  * pcf2127_wdt_active_ping()
0451  */
0452 static int pcf2127_rtc_ts_read(struct device *dev, time64_t *ts)
0453 {
0454     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0455     struct rtc_time tm;
0456     int ret;
0457     unsigned char data[25];
0458 
0459     ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data,
0460                    sizeof(data));
0461     if (ret) {
0462         dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
0463         return ret;
0464     }
0465 
0466     dev_dbg(dev,
0467         "%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
0468         __func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2],
0469         data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC],
0470         data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR],
0471         data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO],
0472         data[PCF2127_REG_TS_YR]);
0473 
0474     tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F);
0475     tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F);
0476     tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F);
0477     tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F);
0478     /* TS_MO register (month) value range: 1-12 */
0479     tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1;
0480     tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]);
0481     if (tm.tm_year < 70)
0482         tm.tm_year += 100; /* assume we are in 1970...2069 */
0483 
0484     ret = rtc_valid_tm(&tm);
0485     if (ret) {
0486         dev_err(dev, "Invalid timestamp. ret=%d\n", ret);
0487         return ret;
0488     }
0489 
0490     *ts = rtc_tm_to_time64(&tm);
0491     return 0;
0492 };
0493 
0494 static void pcf2127_rtc_ts_snapshot(struct device *dev)
0495 {
0496     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0497     int ret;
0498 
0499     /* Let userspace read the first timestamp */
0500     if (pcf2127->ts_valid)
0501         return;
0502 
0503     ret = pcf2127_rtc_ts_read(dev, &pcf2127->ts);
0504     if (!ret)
0505         pcf2127->ts_valid = true;
0506 }
0507 
0508 static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
0509 {
0510     struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
0511     unsigned int ctrl1, ctrl2;
0512     int ret = 0;
0513 
0514     ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
0515     if (ret)
0516         return IRQ_NONE;
0517 
0518     ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
0519     if (ret)
0520         return IRQ_NONE;
0521 
0522     if (!(ctrl1 & PCF2127_CTRL1_IRQ_MASK || ctrl2 & PCF2127_CTRL2_IRQ_MASK))
0523         return IRQ_NONE;
0524 
0525     if (ctrl1 & PCF2127_BIT_CTRL1_TSF1 || ctrl2 & PCF2127_BIT_CTRL2_TSF2)
0526         pcf2127_rtc_ts_snapshot(dev);
0527 
0528     if (ctrl1 & PCF2127_CTRL1_IRQ_MASK)
0529         regmap_write(pcf2127->regmap, PCF2127_REG_CTRL1,
0530             ctrl1 & ~PCF2127_CTRL1_IRQ_MASK);
0531 
0532     if (ctrl2 & PCF2127_CTRL2_IRQ_MASK)
0533         regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
0534             ctrl2 & ~PCF2127_CTRL2_IRQ_MASK);
0535 
0536     if (ctrl2 & PCF2127_BIT_CTRL2_AF)
0537         rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
0538 
0539     pcf2127_wdt_active_ping(&pcf2127->wdd);
0540 
0541     return IRQ_HANDLED;
0542 }
0543 
0544 static const struct rtc_class_ops pcf2127_rtc_ops = {
0545     .ioctl            = pcf2127_rtc_ioctl,
0546     .read_time        = pcf2127_rtc_read_time,
0547     .set_time         = pcf2127_rtc_set_time,
0548     .read_alarm       = pcf2127_rtc_read_alarm,
0549     .set_alarm        = pcf2127_rtc_set_alarm,
0550     .alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
0551 };
0552 
0553 /* sysfs interface */
0554 
0555 static ssize_t timestamp0_store(struct device *dev,
0556                 struct device_attribute *attr,
0557                 const char *buf, size_t count)
0558 {
0559     struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
0560     int ret;
0561 
0562     if (pcf2127->irq_enabled) {
0563         pcf2127->ts_valid = false;
0564     } else {
0565         ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
0566             PCF2127_BIT_CTRL1_TSF1, 0);
0567         if (ret) {
0568             dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
0569             return ret;
0570         }
0571 
0572         ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
0573             PCF2127_BIT_CTRL2_TSF2, 0);
0574         if (ret) {
0575             dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
0576             return ret;
0577         }
0578 
0579         ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
0580         if (ret)
0581             return ret;
0582     }
0583 
0584     return count;
0585 };
0586 
0587 static ssize_t timestamp0_show(struct device *dev,
0588                    struct device_attribute *attr, char *buf)
0589 {
0590     struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
0591     unsigned int ctrl1, ctrl2;
0592     int ret;
0593     time64_t ts;
0594 
0595     if (pcf2127->irq_enabled) {
0596         if (!pcf2127->ts_valid)
0597             return 0;
0598         ts = pcf2127->ts;
0599     } else {
0600         ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL1, &ctrl1);
0601         if (ret)
0602             return 0;
0603 
0604         ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
0605         if (ret)
0606             return 0;
0607 
0608         if (!(ctrl1 & PCF2127_BIT_CTRL1_TSF1) &&
0609             !(ctrl2 & PCF2127_BIT_CTRL2_TSF2))
0610             return 0;
0611 
0612         ret = pcf2127_rtc_ts_read(dev->parent, &ts);
0613         if (ret)
0614             return 0;
0615 
0616         ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
0617         if (ret)
0618             return ret;
0619     }
0620     return sprintf(buf, "%llu\n", (unsigned long long)ts);
0621 };
0622 
0623 static DEVICE_ATTR_RW(timestamp0);
0624 
0625 static struct attribute *pcf2127_attrs[] = {
0626     &dev_attr_timestamp0.attr,
0627     NULL
0628 };
0629 
0630 static const struct attribute_group pcf2127_attr_group = {
0631     .attrs  = pcf2127_attrs,
0632 };
0633 
0634 static int pcf2127_probe(struct device *dev, struct regmap *regmap,
0635              int alarm_irq, const char *name, bool is_pcf2127)
0636 {
0637     struct pcf2127 *pcf2127;
0638     int ret = 0;
0639     unsigned int val;
0640 
0641     dev_dbg(dev, "%s\n", __func__);
0642 
0643     pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
0644     if (!pcf2127)
0645         return -ENOMEM;
0646 
0647     pcf2127->regmap = regmap;
0648 
0649     dev_set_drvdata(dev, pcf2127);
0650 
0651     pcf2127->rtc = devm_rtc_allocate_device(dev);
0652     if (IS_ERR(pcf2127->rtc))
0653         return PTR_ERR(pcf2127->rtc);
0654 
0655     pcf2127->rtc->ops = &pcf2127_rtc_ops;
0656     pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0657     pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
0658     pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
0659     set_bit(RTC_FEATURE_ALARM_RES_2S, pcf2127->rtc->features);
0660     clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, pcf2127->rtc->features);
0661     clear_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
0662 
0663     if (alarm_irq > 0) {
0664         unsigned long flags;
0665 
0666         /*
0667          * If flags = 0, devm_request_threaded_irq() will use IRQ flags
0668          * obtained from device tree.
0669          */
0670         if (dev_fwnode(dev))
0671             flags = 0;
0672         else
0673             flags = IRQF_TRIGGER_LOW;
0674 
0675         ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
0676                         pcf2127_rtc_irq,
0677                         flags | IRQF_ONESHOT,
0678                         dev_name(dev), dev);
0679         if (ret) {
0680             dev_err(dev, "failed to request alarm irq\n");
0681             return ret;
0682         }
0683         pcf2127->irq_enabled = true;
0684     }
0685 
0686     if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
0687         device_init_wakeup(dev, true);
0688         set_bit(RTC_FEATURE_ALARM, pcf2127->rtc->features);
0689     }
0690 
0691     if (is_pcf2127) {
0692         struct nvmem_config nvmem_cfg = {
0693             .priv = pcf2127,
0694             .reg_read = pcf2127_nvmem_read,
0695             .reg_write = pcf2127_nvmem_write,
0696             .size = 512,
0697         };
0698 
0699         ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
0700     }
0701 
0702     /*
0703      * The "Power-On Reset Override" facility prevents the RTC to do a reset
0704      * after power on. For normal operation the PORO must be disabled.
0705      */
0706     regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
0707                 PCF2127_BIT_CTRL1_POR_OVRD);
0708 
0709     ret = regmap_read(pcf2127->regmap, PCF2127_REG_CLKOUT, &val);
0710     if (ret < 0)
0711         return ret;
0712 
0713     if (!(val & PCF2127_BIT_CLKOUT_OTPR)) {
0714         ret = regmap_set_bits(pcf2127->regmap, PCF2127_REG_CLKOUT,
0715                       PCF2127_BIT_CLKOUT_OTPR);
0716         if (ret < 0)
0717             return ret;
0718 
0719         msleep(100);
0720     }
0721 
0722     /*
0723      * Watchdog timer enabled and reset pin /RST activated when timed out.
0724      * Select 1Hz clock source for watchdog timer.
0725      * Note: Countdown timer disabled and not available.
0726      * For pca2129, pcf2129, only bit[7] is for Symbol WD_CD
0727      * of register watchdg_tim_ctl. The bit[6] is labeled
0728      * as T. Bits labeled as T must always be written with
0729      * logic 0.
0730      */
0731     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
0732                  PCF2127_BIT_WD_CTL_CD1 |
0733                  PCF2127_BIT_WD_CTL_CD0 |
0734                  PCF2127_BIT_WD_CTL_TF1 |
0735                  PCF2127_BIT_WD_CTL_TF0,
0736                  PCF2127_BIT_WD_CTL_CD1 |
0737                  (is_pcf2127 ? PCF2127_BIT_WD_CTL_CD0 : 0) |
0738                  PCF2127_BIT_WD_CTL_TF1);
0739     if (ret) {
0740         dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
0741         return ret;
0742     }
0743 
0744     pcf2127_watchdog_init(dev, pcf2127);
0745 
0746     /*
0747      * Disable battery low/switch-over timestamp and interrupts.
0748      * Clear battery interrupt flags which can block new trigger events.
0749      * Note: This is the default chip behaviour but added to ensure
0750      * correct tamper timestamp and interrupt function.
0751      */
0752     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
0753                  PCF2127_BIT_CTRL3_BTSE |
0754                  PCF2127_BIT_CTRL3_BIE |
0755                  PCF2127_BIT_CTRL3_BLIE, 0);
0756     if (ret) {
0757         dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
0758             __func__);
0759         return ret;
0760     }
0761 
0762     /*
0763      * Enable timestamp function and store timestamp of first trigger
0764      * event until TSF1 and TSF2 interrupt flags are cleared.
0765      */
0766     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
0767                  PCF2127_BIT_TS_CTRL_TSOFF |
0768                  PCF2127_BIT_TS_CTRL_TSM,
0769                  PCF2127_BIT_TS_CTRL_TSM);
0770     if (ret) {
0771         dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
0772             __func__);
0773         return ret;
0774     }
0775 
0776     /*
0777      * Enable interrupt generation when TSF1 or TSF2 timestamp flags
0778      * are set. Interrupt signal is an open-drain output and can be
0779      * left floating if unused.
0780      */
0781     ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
0782                  PCF2127_BIT_CTRL2_TSIE,
0783                  PCF2127_BIT_CTRL2_TSIE);
0784     if (ret) {
0785         dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
0786             __func__);
0787         return ret;
0788     }
0789 
0790     ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
0791     if (ret) {
0792         dev_err(dev, "%s: tamper sysfs registering failed\n",
0793             __func__);
0794         return ret;
0795     }
0796 
0797     return devm_rtc_register_device(pcf2127->rtc);
0798 }
0799 
0800 #ifdef CONFIG_OF
0801 static const struct of_device_id pcf2127_of_match[] = {
0802     { .compatible = "nxp,pcf2127" },
0803     { .compatible = "nxp,pcf2129" },
0804     { .compatible = "nxp,pca2129" },
0805     {}
0806 };
0807 MODULE_DEVICE_TABLE(of, pcf2127_of_match);
0808 #endif
0809 
0810 #if IS_ENABLED(CONFIG_I2C)
0811 
0812 static int pcf2127_i2c_write(void *context, const void *data, size_t count)
0813 {
0814     struct device *dev = context;
0815     struct i2c_client *client = to_i2c_client(dev);
0816     int ret;
0817 
0818     ret = i2c_master_send(client, data, count);
0819     if (ret != count)
0820         return ret < 0 ? ret : -EIO;
0821 
0822     return 0;
0823 }
0824 
0825 static int pcf2127_i2c_gather_write(void *context,
0826                 const void *reg, size_t reg_size,
0827                 const void *val, size_t val_size)
0828 {
0829     struct device *dev = context;
0830     struct i2c_client *client = to_i2c_client(dev);
0831     int ret;
0832     void *buf;
0833 
0834     if (WARN_ON(reg_size != 1))
0835         return -EINVAL;
0836 
0837     buf = kmalloc(val_size + 1, GFP_KERNEL);
0838     if (!buf)
0839         return -ENOMEM;
0840 
0841     memcpy(buf, reg, 1);
0842     memcpy(buf + 1, val, val_size);
0843 
0844     ret = i2c_master_send(client, buf, val_size + 1);
0845 
0846     kfree(buf);
0847 
0848     if (ret != val_size + 1)
0849         return ret < 0 ? ret : -EIO;
0850 
0851     return 0;
0852 }
0853 
0854 static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
0855                 void *val, size_t val_size)
0856 {
0857     struct device *dev = context;
0858     struct i2c_client *client = to_i2c_client(dev);
0859     int ret;
0860 
0861     if (WARN_ON(reg_size != 1))
0862         return -EINVAL;
0863 
0864     ret = i2c_master_send(client, reg, 1);
0865     if (ret != 1)
0866         return ret < 0 ? ret : -EIO;
0867 
0868     ret = i2c_master_recv(client, val, val_size);
0869     if (ret != val_size)
0870         return ret < 0 ? ret : -EIO;
0871 
0872     return 0;
0873 }
0874 
0875 /*
0876  * The reason we need this custom regmap_bus instead of using regmap_init_i2c()
0877  * is that the STOP condition is required between set register address and
0878  * read register data when reading from registers.
0879  */
0880 static const struct regmap_bus pcf2127_i2c_regmap = {
0881     .write = pcf2127_i2c_write,
0882     .gather_write = pcf2127_i2c_gather_write,
0883     .read = pcf2127_i2c_read,
0884 };
0885 
0886 static struct i2c_driver pcf2127_i2c_driver;
0887 
0888 static int pcf2127_i2c_probe(struct i2c_client *client,
0889                 const struct i2c_device_id *id)
0890 {
0891     struct regmap *regmap;
0892     static const struct regmap_config config = {
0893         .reg_bits = 8,
0894         .val_bits = 8,
0895         .max_register = 0x1d,
0896     };
0897 
0898     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
0899         return -ENODEV;
0900 
0901     regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
0902                     &client->dev, &config);
0903     if (IS_ERR(regmap)) {
0904         dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
0905             __func__, PTR_ERR(regmap));
0906         return PTR_ERR(regmap);
0907     }
0908 
0909     return pcf2127_probe(&client->dev, regmap, client->irq,
0910                  pcf2127_i2c_driver.driver.name, id->driver_data);
0911 }
0912 
0913 static const struct i2c_device_id pcf2127_i2c_id[] = {
0914     { "pcf2127", 1 },
0915     { "pcf2129", 0 },
0916     { "pca2129", 0 },
0917     { }
0918 };
0919 MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
0920 
0921 static struct i2c_driver pcf2127_i2c_driver = {
0922     .driver     = {
0923         .name   = "rtc-pcf2127-i2c",
0924         .of_match_table = of_match_ptr(pcf2127_of_match),
0925     },
0926     .probe      = pcf2127_i2c_probe,
0927     .id_table   = pcf2127_i2c_id,
0928 };
0929 
0930 static int pcf2127_i2c_register_driver(void)
0931 {
0932     return i2c_add_driver(&pcf2127_i2c_driver);
0933 }
0934 
0935 static void pcf2127_i2c_unregister_driver(void)
0936 {
0937     i2c_del_driver(&pcf2127_i2c_driver);
0938 }
0939 
0940 #else
0941 
0942 static int pcf2127_i2c_register_driver(void)
0943 {
0944     return 0;
0945 }
0946 
0947 static void pcf2127_i2c_unregister_driver(void)
0948 {
0949 }
0950 
0951 #endif
0952 
0953 #if IS_ENABLED(CONFIG_SPI_MASTER)
0954 
0955 static struct spi_driver pcf2127_spi_driver;
0956 
0957 static int pcf2127_spi_probe(struct spi_device *spi)
0958 {
0959     static const struct regmap_config config = {
0960         .reg_bits = 8,
0961         .val_bits = 8,
0962         .read_flag_mask = 0xa0,
0963         .write_flag_mask = 0x20,
0964         .max_register = 0x1d,
0965     };
0966     struct regmap *regmap;
0967 
0968     regmap = devm_regmap_init_spi(spi, &config);
0969     if (IS_ERR(regmap)) {
0970         dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
0971             __func__, PTR_ERR(regmap));
0972         return PTR_ERR(regmap);
0973     }
0974 
0975     return pcf2127_probe(&spi->dev, regmap, spi->irq,
0976                  pcf2127_spi_driver.driver.name,
0977                  spi_get_device_id(spi)->driver_data);
0978 }
0979 
0980 static const struct spi_device_id pcf2127_spi_id[] = {
0981     { "pcf2127", 1 },
0982     { "pcf2129", 0 },
0983     { "pca2129", 0 },
0984     { }
0985 };
0986 MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
0987 
0988 static struct spi_driver pcf2127_spi_driver = {
0989     .driver     = {
0990         .name   = "rtc-pcf2127-spi",
0991         .of_match_table = of_match_ptr(pcf2127_of_match),
0992     },
0993     .probe      = pcf2127_spi_probe,
0994     .id_table   = pcf2127_spi_id,
0995 };
0996 
0997 static int pcf2127_spi_register_driver(void)
0998 {
0999     return spi_register_driver(&pcf2127_spi_driver);
1000 }
1001 
1002 static void pcf2127_spi_unregister_driver(void)
1003 {
1004     spi_unregister_driver(&pcf2127_spi_driver);
1005 }
1006 
1007 #else
1008 
1009 static int pcf2127_spi_register_driver(void)
1010 {
1011     return 0;
1012 }
1013 
1014 static void pcf2127_spi_unregister_driver(void)
1015 {
1016 }
1017 
1018 #endif
1019 
1020 static int __init pcf2127_init(void)
1021 {
1022     int ret;
1023 
1024     ret = pcf2127_i2c_register_driver();
1025     if (ret) {
1026         pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
1027         return ret;
1028     }
1029 
1030     ret = pcf2127_spi_register_driver();
1031     if (ret) {
1032         pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
1033         pcf2127_i2c_unregister_driver();
1034     }
1035 
1036     return ret;
1037 }
1038 module_init(pcf2127_init)
1039 
1040 static void __exit pcf2127_exit(void)
1041 {
1042     pcf2127_spi_unregister_driver();
1043     pcf2127_i2c_unregister_driver();
1044 }
1045 module_exit(pcf2127_exit)
1046 
1047 MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
1048 MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
1049 MODULE_LICENSE("GPL v2");
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