drivers/rtc/rtc-mxc_v2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Real Time Clock (RTC) Driver for i.MX53
0004  * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
0005  * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/mod_devicetable.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pm_wakeirq.h>
0014 #include <linux/rtc.h>
0015
0016 #define SRTC_LPPDR_INIT       0x41736166    /* init for glitch detect */
0017
0018 #define SRTC_LPCR_EN_LP       BIT(3)    /* lp enable */
0019 #define SRTC_LPCR_WAE         BIT(4)    /* lp wakeup alarm enable */
0020 #define SRTC_LPCR_ALP         BIT(7)    /* lp alarm flag */
0021 #define SRTC_LPCR_NSA         BIT(11)   /* lp non secure access */
0022 #define SRTC_LPCR_NVE         BIT(14)   /* lp non valid state exit bit */
0023 #define SRTC_LPCR_IE          BIT(15)   /* lp init state exit bit */
0024
0025 #define SRTC_LPSR_ALP         BIT(3)    /* lp alarm flag */
0026 #define SRTC_LPSR_NVES        BIT(14)   /* lp non-valid state exit status */
0027 #define SRTC_LPSR_IES         BIT(15)   /* lp init state exit status */
0028
0029 #define SRTC_LPSCMR 0x00    /* LP Secure Counter MSB Reg */
0030 #define SRTC_LPSCLR 0x04    /* LP Secure Counter LSB Reg */
0031 #define SRTC_LPSAR  0x08    /* LP Secure Alarm Reg */
0032 #define SRTC_LPCR   0x10    /* LP Control Reg */
0033 #define SRTC_LPSR   0x14    /* LP Status Reg */
0034 #define SRTC_LPPDR  0x18    /* LP Power Supply Glitch Detector Reg */
0035
0036 /* max. number of retries to read registers, 120 was max during test */
0037 #define REG_READ_TIMEOUT 2000
0038
0039 struct mxc_rtc_data {
0040     struct rtc_device *rtc;
0041     void __iomem *ioaddr;
0042     struct clk *clk;
0043     spinlock_t lock; /* protects register access */
0044     int irq;
0045 };
0046
0047 /*
0048  * This function does write synchronization for writes to the lp srtc block.
0049  * To take care of the asynchronous CKIL clock, all writes from the IP domain
0050  * will be synchronized to the CKIL domain.
0051  * The caller should hold the pdata->lock
0052  */
0053 static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
0054 {
0055     unsigned int i;
0056
0057     /* Wait for 3 CKIL cycles */
0058     for (i = 0; i < 3; i++) {
0059         const u32 count = readl(ioaddr + SRTC_LPSCLR);
0060         unsigned int timeout = REG_READ_TIMEOUT;
0061
0062         while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
0063             if (!--timeout) {
0064                 dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
0065                 return;
0066             }
0067         }
0068     }
0069 }
0070
0071 /* This function is the RTC interrupt service routine. */
0072 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
0073 {
0074     struct device *dev = dev_id;
0075     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0076     void __iomem *ioaddr = pdata->ioaddr;
0077     u32 lp_status;
0078     u32 lp_cr;
0079
0080     spin_lock(&pdata->lock);
0081     if (clk_enable(pdata->clk)) {
0082         spin_unlock(&pdata->lock);
0083         return IRQ_NONE;
0084     }
0085
0086     lp_status = readl(ioaddr + SRTC_LPSR);
0087     lp_cr = readl(ioaddr + SRTC_LPCR);
0088
0089     /* update irq data & counter */
0090     if (lp_status & SRTC_LPSR_ALP) {
0091         if (lp_cr & SRTC_LPCR_ALP)
0092             rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
0093
0094         /* disable further lp alarm interrupts */
0095         lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
0096     }
0097
0098     /* Update interrupt enables */
0099     writel(lp_cr, ioaddr + SRTC_LPCR);
0100
0101     /* clear interrupt status */
0102     writel(lp_status, ioaddr + SRTC_LPSR);
0103
0104     mxc_rtc_sync_lp_locked(dev, ioaddr);
0105     clk_disable(pdata->clk);
0106     spin_unlock(&pdata->lock);
0107     return IRQ_HANDLED;
0108 }
0109
0110 /*
0111  * Enable clk and aquire spinlock
0112  * @return  0 if successful; non-zero otherwise.
0113  */
0114 static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
0115 {
0116     int ret;
0117
0118     spin_lock_irq(&pdata->lock);
0119     ret = clk_enable(pdata->clk);
0120     if (ret) {
0121         spin_unlock_irq(&pdata->lock);
0122         return ret;
0123     }
0124     return 0;
0125 }
0126
0127 static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
0128 {
0129     clk_disable(pdata->clk);
0130     spin_unlock_irq(&pdata->lock);
0131     return 0;
0132 }
0133
0134 /*
0135  * This function reads the current RTC time into tm in Gregorian date.
0136  *
0137  * @param  tm           contains the RTC time value upon return
0138  *
0139  * @return  0 if successful; non-zero otherwise.
0140  */
0141 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
0142 {
0143     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0144     const int clk_failed = clk_enable(pdata->clk);
0145
0146     if (!clk_failed) {
0147         const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
0148
0149         rtc_time64_to_tm(now, tm);
0150         clk_disable(pdata->clk);
0151         return 0;
0152     }
0153     return clk_failed;
0154 }
0155
0156 /*
0157  * This function sets the internal RTC time based on tm in Gregorian date.
0158  *
0159  * @param  tm           the time value to be set in the RTC
0160  *
0161  * @return  0 if successful; non-zero otherwise.
0162  */
0163 static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
0164 {
0165     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0166     time64_t time = rtc_tm_to_time64(tm);
0167     int ret;
0168
0169     ret = mxc_rtc_lock(pdata);
0170     if (ret)
0171         return ret;
0172
0173     writel(time, pdata->ioaddr + SRTC_LPSCMR);
0174     mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
0175     return mxc_rtc_unlock(pdata);
0176 }
0177
0178 /*
0179  * This function reads the current alarm value into the passed in \b alrm
0180  * argument. It updates the \b alrm's pending field value based on the whether
0181  * an alarm interrupt occurs or not.
0182  *
0183  * @param  alrm         contains the RTC alarm value upon return
0184  *
0185  * @return  0 if successful; non-zero otherwise.
0186  */
0187 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0188 {
0189     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0190     void __iomem *ioaddr = pdata->ioaddr;
0191     int ret;
0192
0193     ret = mxc_rtc_lock(pdata);
0194     if (ret)
0195         return ret;
0196
0197     rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
0198     alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
0199     return mxc_rtc_unlock(pdata);
0200 }
0201
0202 /*
0203  * Enable/Disable alarm interrupt
0204  * The caller should hold the pdata->lock
0205  */
0206 static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
0207                         unsigned int enable)
0208 {
0209     u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
0210
0211     if (enable)
0212         lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
0213     else
0214         lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
0215
0216     writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
0217 }
0218
0219 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
0220 {
0221     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0222     int ret = mxc_rtc_lock(pdata);
0223
0224     if (ret)
0225         return ret;
0226
0227     mxc_rtc_alarm_irq_enable_locked(pdata, enable);
0228     return mxc_rtc_unlock(pdata);
0229 }
0230
0231 /*
0232  * This function sets the RTC alarm based on passed in alrm.
0233  *
0234  * @param  alrm         the alarm value to be set in the RTC
0235  *
0236  * @return  0 if successful; non-zero otherwise.
0237  */
0238 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0239 {
0240     const time64_t time = rtc_tm_to_time64(&alrm->time);
0241     struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
0242     int ret = mxc_rtc_lock(pdata);
0243
0244     if (ret)
0245         return ret;
0246
0247     writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
0248
0249     /* clear alarm interrupt status bit */
0250     writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
0251     mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
0252
0253     mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
0254     mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
0255     mxc_rtc_unlock(pdata);
0256     return ret;
0257 }
0258
0259 static const struct rtc_class_ops mxc_rtc_ops = {
0260     .read_time = mxc_rtc_read_time,
0261     .set_time = mxc_rtc_set_time,
0262     .read_alarm = mxc_rtc_read_alarm,
0263     .set_alarm = mxc_rtc_set_alarm,
0264     .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
0265 };
0266
0267 static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
0268 {
0269     unsigned int timeout = REG_READ_TIMEOUT;
0270
0271     while (!(readl(ioaddr) & flag)) {
0272         if (!--timeout)
0273             return -EBUSY;
0274     }
0275     return 0;
0276 }
0277
0278 static int mxc_rtc_probe(struct platform_device *pdev)
0279 {
0280     struct mxc_rtc_data *pdata;
0281     void __iomem *ioaddr;
0282     int ret = 0;
0283
0284     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0285     if (!pdata)
0286         return -ENOMEM;
0287
0288     pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
0289     if (IS_ERR(pdata->ioaddr))
0290         return PTR_ERR(pdata->ioaddr);
0291
0292     ioaddr = pdata->ioaddr;
0293
0294     pdata->clk = devm_clk_get(&pdev->dev, NULL);
0295     if (IS_ERR(pdata->clk)) {
0296         dev_err(&pdev->dev, "unable to get rtc clock!\n");
0297         return PTR_ERR(pdata->clk);
0298     }
0299
0300     spin_lock_init(&pdata->lock);
0301     pdata->irq = platform_get_irq(pdev, 0);
0302     if (pdata->irq < 0)
0303         return pdata->irq;
0304
0305     device_init_wakeup(&pdev->dev, 1);
0306     ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
0307     if (ret)
0308         dev_err(&pdev->dev, "failed to enable irq wake\n");
0309
0310     ret = clk_prepare_enable(pdata->clk);
0311     if (ret)
0312         return ret;
0313     /* initialize glitch detect */
0314     writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
0315
0316     /* clear lp interrupt status */
0317     writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
0318
0319     /* move out of init state */
0320     writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
0321     ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
0322     if (ret) {
0323         dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
0324         clk_disable_unprepare(pdata->clk);
0325         return ret;
0326     }
0327
0328     /* move out of non-valid state */
0329     writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
0330         SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
0331     ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
0332     if (ret) {
0333         dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
0334         clk_disable_unprepare(pdata->clk);
0335         return ret;
0336     }
0337
0338     pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
0339     if (IS_ERR(pdata->rtc))
0340         return PTR_ERR(pdata->rtc);
0341
0342     pdata->rtc->ops = &mxc_rtc_ops;
0343     pdata->rtc->range_max = U32_MAX;
0344
0345     clk_disable(pdata->clk);
0346     platform_set_drvdata(pdev, pdata);
0347     ret =
0348         devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
0349                  pdev->name, &pdev->dev);
0350     if (ret < 0) {
0351         dev_err(&pdev->dev, "interrupt not available.\n");
0352         clk_unprepare(pdata->clk);
0353         return ret;
0354     }
0355
0356     ret = devm_rtc_register_device(pdata->rtc);
0357     if (ret < 0)
0358         clk_unprepare(pdata->clk);
0359
0360     return ret;
0361 }
0362
0363 static int mxc_rtc_remove(struct platform_device *pdev)
0364 {
0365     struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
0366
0367     clk_disable_unprepare(pdata->clk);
0368     return 0;
0369 }
0370
0371 static const struct of_device_id mxc_ids[] = {
0372     { .compatible = "fsl,imx53-rtc", },
0373     {}
0374 };
0375 MODULE_DEVICE_TABLE(of, mxc_ids);
0376
0377 static struct platform_driver mxc_rtc_driver = {
0378     .driver = {
0379         .name = "mxc_rtc_v2",
0380         .of_match_table = mxc_ids,
0381     },
0382     .probe = mxc_rtc_probe,
0383     .remove = mxc_rtc_remove,
0384 };
0385
0386 module_platform_driver(mxc_rtc_driver);
0387
0388 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
0389 MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
0390 MODULE_LICENSE("GPL");