drivers/rtc/rtc-mxc.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
0004
0005 #include <linux/io.h>
0006 #include <linux/rtc.h>
0007 #include <linux/module.h>
0008 #include <linux/slab.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/pm_wakeirq.h>
0012 #include <linux/clk.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015
0016 #define RTC_INPUT_CLK_32768HZ   (0x00 << 5)
0017 #define RTC_INPUT_CLK_32000HZ   (0x01 << 5)
0018 #define RTC_INPUT_CLK_38400HZ   (0x02 << 5)
0019
0020 #define RTC_SW_BIT      (1 << 0)
0021 #define RTC_ALM_BIT     (1 << 2)
0022 #define RTC_1HZ_BIT     (1 << 4)
0023 #define RTC_2HZ_BIT     (1 << 7)
0024 #define RTC_SAM0_BIT    (1 << 8)
0025 #define RTC_SAM1_BIT    (1 << 9)
0026 #define RTC_SAM2_BIT    (1 << 10)
0027 #define RTC_SAM3_BIT    (1 << 11)
0028 #define RTC_SAM4_BIT    (1 << 12)
0029 #define RTC_SAM5_BIT    (1 << 13)
0030 #define RTC_SAM6_BIT    (1 << 14)
0031 #define RTC_SAM7_BIT    (1 << 15)
0032 #define PIT_ALL_ON      (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
0033              RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
0034              RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
0035
0036 #define RTC_ENABLE_BIT  (1 << 7)
0037
0038 #define MAX_PIE_NUM     9
0039 #define MAX_PIE_FREQ    512
0040
0041 #define MXC_RTC_TIME    0
0042 #define MXC_RTC_ALARM   1
0043
0044 #define RTC_HOURMIN 0x00    /*  32bit rtc hour/min counter reg */
0045 #define RTC_SECOND  0x04    /*  32bit rtc seconds counter reg */
0046 #define RTC_ALRM_HM 0x08    /*  32bit rtc alarm hour/min reg */
0047 #define RTC_ALRM_SEC    0x0C    /*  32bit rtc alarm seconds reg */
0048 #define RTC_RTCCTL  0x10    /*  32bit rtc control reg */
0049 #define RTC_RTCISR  0x14    /*  32bit rtc interrupt status reg */
0050 #define RTC_RTCIENR 0x18    /*  32bit rtc interrupt enable reg */
0051 #define RTC_STPWCH  0x1C    /*  32bit rtc stopwatch min reg */
0052 #define RTC_DAYR    0x20    /*  32bit rtc days counter reg */
0053 #define RTC_DAYALARM    0x24    /*  32bit rtc day alarm reg */
0054 #define RTC_TEST1   0x28    /*  32bit rtc test reg 1 */
0055 #define RTC_TEST2   0x2C    /*  32bit rtc test reg 2 */
0056 #define RTC_TEST3   0x30    /*  32bit rtc test reg 3 */
0057
0058 enum imx_rtc_type {
0059     IMX1_RTC,
0060     IMX21_RTC,
0061 };
0062
0063 struct rtc_plat_data {
0064     struct rtc_device *rtc;
0065     void __iomem *ioaddr;
0066     int irq;
0067     struct clk *clk_ref;
0068     struct clk *clk_ipg;
0069     struct rtc_time g_rtc_alarm;
0070     enum imx_rtc_type devtype;
0071 };
0072
0073 static const struct of_device_id imx_rtc_dt_ids[] = {
0074     { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
0075     { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
0076     {}
0077 };
0078 MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
0079
0080 static inline int is_imx1_rtc(struct rtc_plat_data *data)
0081 {
0082     return data->devtype == IMX1_RTC;
0083 }
0084
0085 /*
0086  * This function is used to obtain the RTC time or the alarm value in
0087  * second.
0088  */
0089 static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
0090 {
0091     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0092     void __iomem *ioaddr = pdata->ioaddr;
0093     u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
0094
0095     switch (time_alarm) {
0096     case MXC_RTC_TIME:
0097         day = readw(ioaddr + RTC_DAYR);
0098         hr_min = readw(ioaddr + RTC_HOURMIN);
0099         sec = readw(ioaddr + RTC_SECOND);
0100         break;
0101     case MXC_RTC_ALARM:
0102         day = readw(ioaddr + RTC_DAYALARM);
0103         hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
0104         sec = readw(ioaddr + RTC_ALRM_SEC);
0105         break;
0106     }
0107
0108     hr = hr_min >> 8;
0109     min = hr_min & 0xff;
0110
0111     return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
0112 }
0113
0114 /*
0115  * This function sets the RTC alarm value or the time value.
0116  */
0117 static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
0118 {
0119     u32 tod, day, hr, min, sec, temp;
0120     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0121     void __iomem *ioaddr = pdata->ioaddr;
0122
0123     day = div_s64_rem(time, 86400, &tod);
0124
0125     /* time is within a day now */
0126     hr = tod / 3600;
0127     tod -= hr * 3600;
0128
0129     /* time is within an hour now */
0130     min = tod / 60;
0131     sec = tod - min * 60;
0132
0133     temp = (hr << 8) + min;
0134
0135     switch (time_alarm) {
0136     case MXC_RTC_TIME:
0137         writew(day, ioaddr + RTC_DAYR);
0138         writew(sec, ioaddr + RTC_SECOND);
0139         writew(temp, ioaddr + RTC_HOURMIN);
0140         break;
0141     case MXC_RTC_ALARM:
0142         writew(day, ioaddr + RTC_DAYALARM);
0143         writew(sec, ioaddr + RTC_ALRM_SEC);
0144         writew(temp, ioaddr + RTC_ALRM_HM);
0145         break;
0146     }
0147 }
0148
0149 /*
0150  * This function updates the RTC alarm registers and then clears all the
0151  * interrupt status bits.
0152  */
0153 static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
0154 {
0155     time64_t time;
0156     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0157     void __iomem *ioaddr = pdata->ioaddr;
0158
0159     time = rtc_tm_to_time64(alrm);
0160
0161     /* clear all the interrupt status bits */
0162     writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
0163     set_alarm_or_time(dev, MXC_RTC_ALARM, time);
0164 }
0165
0166 static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
0167                 unsigned int enabled)
0168 {
0169     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0170     void __iomem *ioaddr = pdata->ioaddr;
0171     u32 reg;
0172     unsigned long flags;
0173
0174     spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
0175     reg = readw(ioaddr + RTC_RTCIENR);
0176
0177     if (enabled)
0178         reg |= bit;
0179     else
0180         reg &= ~bit;
0181
0182     writew(reg, ioaddr + RTC_RTCIENR);
0183     spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
0184 }
0185
0186 /* This function is the RTC interrupt service routine. */
0187 static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
0188 {
0189     struct platform_device *pdev = dev_id;
0190     struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
0191     void __iomem *ioaddr = pdata->ioaddr;
0192     u32 status;
0193     u32 events = 0;
0194
0195     spin_lock(&pdata->rtc->irq_lock);
0196     status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
0197     /* clear interrupt sources */
0198     writew(status, ioaddr + RTC_RTCISR);
0199
0200     /* update irq data & counter */
0201     if (status & RTC_ALM_BIT) {
0202         events |= (RTC_AF | RTC_IRQF);
0203         /* RTC alarm should be one-shot */
0204         mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
0205     }
0206
0207     if (status & PIT_ALL_ON)
0208         events |= (RTC_PF | RTC_IRQF);
0209
0210     rtc_update_irq(pdata->rtc, 1, events);
0211     spin_unlock(&pdata->rtc->irq_lock);
0212
0213     return IRQ_HANDLED;
0214 }
0215
0216 static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0217 {
0218     mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
0219     return 0;
0220 }
0221
0222 /*
0223  * This function reads the current RTC time into tm in Gregorian date.
0224  */
0225 static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
0226 {
0227     time64_t val;
0228
0229     /* Avoid roll-over from reading the different registers */
0230     do {
0231         val = get_alarm_or_time(dev, MXC_RTC_TIME);
0232     } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
0233
0234     rtc_time64_to_tm(val, tm);
0235
0236     return 0;
0237 }
0238
0239 /*
0240  * This function sets the internal RTC time based on tm in Gregorian date.
0241  */
0242 static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
0243 {
0244     time64_t time = rtc_tm_to_time64(tm);
0245
0246     /* Avoid roll-over from reading the different registers */
0247     do {
0248         set_alarm_or_time(dev, MXC_RTC_TIME, time);
0249     } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
0250
0251     return 0;
0252 }
0253
0254 /*
0255  * This function reads the current alarm value into the passed in 'alrm'
0256  * argument. It updates the alrm's pending field value based on the whether
0257  * an alarm interrupt occurs or not.
0258  */
0259 static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0260 {
0261     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0262     void __iomem *ioaddr = pdata->ioaddr;
0263
0264     rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
0265     alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
0266
0267     return 0;
0268 }
0269
0270 /*
0271  * This function sets the RTC alarm based on passed in alrm.
0272  */
0273 static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0274 {
0275     struct rtc_plat_data *pdata = dev_get_drvdata(dev);
0276
0277     rtc_update_alarm(dev, &alrm->time);
0278
0279     memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
0280     mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
0281
0282     return 0;
0283 }
0284
0285 /* RTC layer */
0286 static const struct rtc_class_ops mxc_rtc_ops = {
0287     .read_time      = mxc_rtc_read_time,
0288     .set_time       = mxc_rtc_set_time,
0289     .read_alarm     = mxc_rtc_read_alarm,
0290     .set_alarm      = mxc_rtc_set_alarm,
0291     .alarm_irq_enable   = mxc_rtc_alarm_irq_enable,
0292 };
0293
0294 static void mxc_rtc_action(void *p)
0295 {
0296     struct rtc_plat_data *pdata = p;
0297
0298     clk_disable_unprepare(pdata->clk_ref);
0299     clk_disable_unprepare(pdata->clk_ipg);
0300 }
0301
0302 static int mxc_rtc_probe(struct platform_device *pdev)
0303 {
0304     struct rtc_device *rtc;
0305     struct rtc_plat_data *pdata = NULL;
0306     u32 reg;
0307     unsigned long rate;
0308     int ret;
0309
0310     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0311     if (!pdata)
0312         return -ENOMEM;
0313
0314     pdata->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
0315
0316     pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
0317     if (IS_ERR(pdata->ioaddr))
0318         return PTR_ERR(pdata->ioaddr);
0319
0320     rtc = devm_rtc_allocate_device(&pdev->dev);
0321     if (IS_ERR(rtc))
0322         return PTR_ERR(rtc);
0323
0324     pdata->rtc = rtc;
0325     rtc->ops = &mxc_rtc_ops;
0326     if (is_imx1_rtc(pdata)) {
0327         struct rtc_time tm;
0328
0329         /* 9bit days + hours minutes seconds */
0330         rtc->range_max = (1 << 9) * 86400 - 1;
0331
0332         /*
0333          * Set the start date as beginning of the current year. This can
0334          * be overridden using device tree.
0335          */
0336         rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
0337         rtc->start_secs =  mktime64(tm.tm_year, 1, 1, 0, 0, 0);
0338         rtc->set_start_time = true;
0339     } else {
0340         /* 16bit days + hours minutes seconds */
0341         rtc->range_max = (1 << 16) * 86400ULL - 1;
0342     }
0343
0344     pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
0345     if (IS_ERR(pdata->clk_ipg)) {
0346         dev_err(&pdev->dev, "unable to get ipg clock!\n");
0347         return PTR_ERR(pdata->clk_ipg);
0348     }
0349
0350     ret = clk_prepare_enable(pdata->clk_ipg);
0351     if (ret)
0352         return ret;
0353
0354     pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
0355     if (IS_ERR(pdata->clk_ref)) {
0356         clk_disable_unprepare(pdata->clk_ipg);
0357         dev_err(&pdev->dev, "unable to get ref clock!\n");
0358         return PTR_ERR(pdata->clk_ref);
0359     }
0360
0361     ret = clk_prepare_enable(pdata->clk_ref);
0362     if (ret) {
0363         clk_disable_unprepare(pdata->clk_ipg);
0364         return ret;
0365     }
0366
0367     ret = devm_add_action_or_reset(&pdev->dev, mxc_rtc_action, pdata);
0368     if (ret)
0369         return ret;
0370
0371     rate = clk_get_rate(pdata->clk_ref);
0372
0373     if (rate == 32768)
0374         reg = RTC_INPUT_CLK_32768HZ;
0375     else if (rate == 32000)
0376         reg = RTC_INPUT_CLK_32000HZ;
0377     else if (rate == 38400)
0378         reg = RTC_INPUT_CLK_38400HZ;
0379     else {
0380         dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
0381         return -EINVAL;
0382     }
0383
0384     reg |= RTC_ENABLE_BIT;
0385     writew(reg, (pdata->ioaddr + RTC_RTCCTL));
0386     if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
0387         dev_err(&pdev->dev, "hardware module can't be enabled!\n");
0388         return -EIO;
0389     }
0390
0391     platform_set_drvdata(pdev, pdata);
0392
0393     /* Configure and enable the RTC */
0394     pdata->irq = platform_get_irq(pdev, 0);
0395
0396     if (pdata->irq >= 0 &&
0397         devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
0398                  IRQF_SHARED, pdev->name, pdev) < 0) {
0399         dev_warn(&pdev->dev, "interrupt not available.\n");
0400         pdata->irq = -1;
0401     }
0402
0403     if (pdata->irq >= 0) {
0404         device_init_wakeup(&pdev->dev, 1);
0405         ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
0406         if (ret)
0407             dev_err(&pdev->dev, "failed to enable irq wake\n");
0408     }
0409
0410     ret = devm_rtc_register_device(rtc);
0411
0412     return ret;
0413 }
0414
0415 static struct platform_driver mxc_rtc_driver = {
0416     .driver = {
0417            .name    = "mxc_rtc",
0418            .of_match_table = imx_rtc_dt_ids,
0419     },
0420     .probe = mxc_rtc_probe,
0421 };
0422
0423 module_platform_driver(mxc_rtc_driver)
0424
0425 MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
0426 MODULE_DESCRIPTION("RTC driver for Freescale MXC");
0427 MODULE_LICENSE("GPL");
0428