drivers/rtc/rtc-msc313.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Real time clocks driver for MStar/SigmaStar ARMv7 SoCs.
0004  * Based on "Real Time Clock driver for msb252x." that was contained
0005  * in various MStar kernels.
0006  *
0007  * (C) 2019 Daniel Palmer
0008  * (C) 2021 Romain Perier
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/rtc.h>
0018
0019 /* Registers */
0020 #define REG_RTC_CTRL        0x00
0021 #define REG_RTC_FREQ_CW_L   0x04
0022 #define REG_RTC_FREQ_CW_H   0x08
0023 #define REG_RTC_LOAD_VAL_L  0x0C
0024 #define REG_RTC_LOAD_VAL_H  0x10
0025 #define REG_RTC_MATCH_VAL_L 0x14
0026 #define REG_RTC_MATCH_VAL_H 0x18
0027 #define REG_RTC_STATUS_INT  0x1C
0028 #define REG_RTC_CNT_VAL_L   0x20
0029 #define REG_RTC_CNT_VAL_H   0x24
0030
0031 /* Control bits for REG_RTC_CTRL */
0032 #define SOFT_RSTZ_BIT       BIT(0)
0033 #define CNT_EN_BIT      BIT(1)
0034 #define WRAP_EN_BIT     BIT(2)
0035 #define LOAD_EN_BIT     BIT(3)
0036 #define READ_EN_BIT     BIT(4)
0037 #define INT_MASK_BIT        BIT(5)
0038 #define INT_FORCE_BIT       BIT(6)
0039 #define INT_CLEAR_BIT       BIT(7)
0040
0041 /* Control bits for REG_RTC_STATUS_INT */
0042 #define RAW_INT_BIT     BIT(0)
0043 #define ALM_INT_BIT     BIT(1)
0044
0045 struct msc313_rtc {
0046     struct rtc_device *rtc_dev;
0047     void __iomem *rtc_base;
0048 };
0049
0050 static int msc313_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0051 {
0052     struct msc313_rtc *priv = dev_get_drvdata(dev);
0053     unsigned long seconds;
0054
0055     seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L)
0056             | ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16);
0057
0058     rtc_time64_to_tm(seconds, &alarm->time);
0059
0060     if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT))
0061         alarm->enabled = 1;
0062
0063     return 0;
0064 }
0065
0066 static int msc313_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0067 {
0068     struct msc313_rtc *priv = dev_get_drvdata(dev);
0069     u16 reg;
0070
0071     reg = readw(priv->rtc_base + REG_RTC_CTRL);
0072     if (enabled)
0073         reg &= ~INT_MASK_BIT;
0074     else
0075         reg |= INT_MASK_BIT;
0076     writew(reg, priv->rtc_base + REG_RTC_CTRL);
0077     return 0;
0078 }
0079
0080 static int msc313_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0081 {
0082     struct msc313_rtc *priv = dev_get_drvdata(dev);
0083     unsigned long seconds;
0084
0085     seconds = rtc_tm_to_time64(&alarm->time);
0086     writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L);
0087     writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H);
0088
0089     msc313_rtc_alarm_irq_enable(dev, alarm->enabled);
0090
0091     return 0;
0092 }
0093
0094 static bool msc313_rtc_get_enabled(struct msc313_rtc *priv)
0095 {
0096     return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT;
0097 }
0098
0099 static void msc313_rtc_set_enabled(struct msc313_rtc *priv)
0100 {
0101     u16 reg;
0102
0103     reg = readw(priv->rtc_base + REG_RTC_CTRL);
0104     reg |= CNT_EN_BIT;
0105     writew(reg, priv->rtc_base + REG_RTC_CTRL);
0106 }
0107
0108 static int msc313_rtc_read_time(struct device *dev, struct rtc_time *tm)
0109 {
0110     struct msc313_rtc *priv = dev_get_drvdata(dev);
0111     u32 seconds;
0112     u16 reg;
0113
0114     if (!msc313_rtc_get_enabled(priv))
0115         return -EINVAL;
0116
0117     reg = readw(priv->rtc_base + REG_RTC_CTRL);
0118     writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
0119
0120     /* Wait for HW latch done */
0121     while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT)
0122         udelay(1);
0123
0124     seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L)
0125             | ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16);
0126
0127     rtc_time64_to_tm(seconds, tm);
0128
0129     return 0;
0130 }
0131
0132 static int msc313_rtc_set_time(struct device *dev, struct rtc_time *tm)
0133 {
0134     struct msc313_rtc *priv = dev_get_drvdata(dev);
0135     unsigned long seconds;
0136     u16 reg;
0137
0138     seconds = rtc_tm_to_time64(tm);
0139     writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L);
0140     writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H);
0141
0142     /* Enable load for loading value into internal RTC counter */
0143     reg = readw(priv->rtc_base + REG_RTC_CTRL);
0144     writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL);
0145
0146     /* Wait for HW latch done */
0147     while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT)
0148         udelay(1);
0149     msc313_rtc_set_enabled(priv);
0150     return 0;
0151 }
0152
0153 static const struct rtc_class_ops msc313_rtc_ops = {
0154     .read_time = msc313_rtc_read_time,
0155     .set_time = msc313_rtc_set_time,
0156     .read_alarm = msc313_rtc_read_alarm,
0157     .set_alarm = msc313_rtc_set_alarm,
0158     .alarm_irq_enable = msc313_rtc_alarm_irq_enable,
0159 };
0160
0161 static irqreturn_t msc313_rtc_interrupt(s32 irq, void *dev_id)
0162 {
0163     struct msc313_rtc *priv = dev_get_drvdata(dev_id);
0164     u16 reg;
0165
0166     reg = readw(priv->rtc_base + REG_RTC_STATUS_INT);
0167     if (!(reg & ALM_INT_BIT))
0168         return IRQ_NONE;
0169
0170     reg = readw(priv->rtc_base + REG_RTC_CTRL);
0171     reg |= INT_CLEAR_BIT;
0172     reg &= ~INT_FORCE_BIT;
0173     writew(reg, priv->rtc_base + REG_RTC_CTRL);
0174
0175     rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);
0176
0177     return IRQ_HANDLED;
0178 }
0179
0180 static int msc313_rtc_probe(struct platform_device *pdev)
0181 {
0182     struct device *dev = &pdev->dev;
0183     struct msc313_rtc *priv;
0184     unsigned long rate;
0185     struct clk *clk;
0186     int ret;
0187     int irq;
0188
0189     priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL);
0190     if (!priv)
0191         return -ENOMEM;
0192
0193     priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);
0194     if (IS_ERR(priv->rtc_base))
0195         return PTR_ERR(priv->rtc_base);
0196
0197     irq = platform_get_irq(pdev, 0);
0198     if (irq < 0)
0199         return -EINVAL;
0200
0201     priv->rtc_dev = devm_rtc_allocate_device(dev);
0202     if (IS_ERR(priv->rtc_dev))
0203         return PTR_ERR(priv->rtc_dev);
0204
0205     priv->rtc_dev->ops = &msc313_rtc_ops;
0206     priv->rtc_dev->range_max = U32_MAX;
0207
0208     ret = devm_request_irq(dev, irq, msc313_rtc_interrupt, IRQF_SHARED,
0209                    dev_name(&pdev->dev), &pdev->dev);
0210     if (ret) {
0211         dev_err(dev, "Could not request IRQ\n");
0212         return ret;
0213     }
0214
0215     clk = devm_clk_get(dev, NULL);
0216     if (IS_ERR(clk)) {
0217         dev_err(dev, "No input reference clock\n");
0218         return PTR_ERR(clk);
0219     }
0220
0221     ret = clk_prepare_enable(clk);
0222     if (ret) {
0223         dev_err(dev, "Failed to enable the reference clock, %d\n", ret);
0224         return ret;
0225     }
0226
0227     ret = devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk);
0228     if (ret)
0229         return ret;
0230
0231     rate = clk_get_rate(clk);
0232     writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L);
0233     writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H);
0234
0235     platform_set_drvdata(pdev, priv);
0236
0237     return devm_rtc_register_device(priv->rtc_dev);
0238 }
0239
0240 static const struct of_device_id msc313_rtc_of_match_table[] = {
0241     { .compatible = "mstar,msc313-rtc" },
0242     { }
0243 };
0244 MODULE_DEVICE_TABLE(of, msc313_rtc_of_match_table);
0245
0246 static struct platform_driver msc313_rtc_driver = {
0247     .probe = msc313_rtc_probe,
0248     .driver = {
0249         .name = "msc313-rtc",
0250         .of_match_table = msc313_rtc_of_match_table,
0251     },
0252 };
0253
0254 module_platform_driver(msc313_rtc_driver);
0255
0256 MODULE_AUTHOR("Daniel Palmer <daniel@thingy.jp>");
0257 MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
0258 MODULE_DESCRIPTION("MStar RTC Driver");
0259 MODULE_LICENSE("GPL v2");