drivers/rtc/rtc-meson.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * RTC driver for the interal RTC block in the Amlogic Meson6, Meson8,
0004  * Meson8b and Meson8m2 SoCs.
0005  *
0006  * The RTC is split in to two parts, the AHB front end and a simple serial
0007  * connection to the actual registers. This driver manages both parts.
0008  *
0009  * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0010  * Copyright (c) 2015 Ben Dooks <ben.dooks@codethink.co.uk> for Codethink Ltd
0011  * Based on origin by Carlo Caione <carlo@endlessm.com>
0012  */
0013
0014 #include <linux/bitfield.h>
0015 #include <linux/delay.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/nvmem-provider.h>
0020 #include <linux/of.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/regmap.h>
0023 #include <linux/regulator/consumer.h>
0024 #include <linux/reset.h>
0025 #include <linux/rtc.h>
0026
0027 /* registers accessed from cpu bus */
0028 #define RTC_ADDR0               0x00
0029     #define RTC_ADDR0_LINE_SCLK     BIT(0)
0030     #define RTC_ADDR0_LINE_SEN      BIT(1)
0031     #define RTC_ADDR0_LINE_SDI      BIT(2)
0032     #define RTC_ADDR0_START_SER     BIT(17)
0033     #define RTC_ADDR0_WAIT_SER      BIT(22)
0034     #define RTC_ADDR0_DATA          GENMASK(31, 24)
0035
0036 #define RTC_ADDR1               0x04
0037     #define RTC_ADDR1_SDO           BIT(0)
0038     #define RTC_ADDR1_S_READY       BIT(1)
0039
0040 #define RTC_ADDR2               0x08
0041 #define RTC_ADDR3               0x0c
0042
0043 #define RTC_REG4                0x10
0044     #define RTC_REG4_STATIC_VALUE       GENMASK(7, 0)
0045
0046 /* rtc registers accessed via rtc-serial interface */
0047 #define RTC_COUNTER     (0)
0048 #define RTC_SEC_ADJ     (2)
0049 #define RTC_REGMEM_0        (4)
0050 #define RTC_REGMEM_1        (5)
0051 #define RTC_REGMEM_2        (6)
0052 #define RTC_REGMEM_3        (7)
0053
0054 #define RTC_ADDR_BITS       (3) /* number of address bits to send */
0055 #define RTC_DATA_BITS       (32)    /* number of data bits to tx/rx */
0056
0057 #define MESON_STATIC_BIAS_CUR   (0x5 << 1)
0058 #define MESON_STATIC_VOLTAGE    (0x3 << 11)
0059 #define MESON_STATIC_DEFAULT    (MESON_STATIC_BIAS_CUR | MESON_STATIC_VOLTAGE)
0060
0061 struct meson_rtc {
0062     struct rtc_device   *rtc;       /* rtc device we created */
0063     struct device       *dev;       /* device we bound from */
0064     struct reset_control    *reset;     /* reset source */
0065     struct regulator    *vdd;       /* voltage input */
0066     struct regmap       *peripheral;    /* peripheral registers */
0067     struct regmap       *serial;    /* serial registers */
0068 };
0069
0070 static const struct regmap_config meson_rtc_peripheral_regmap_config = {
0071     .name       = "peripheral-registers",
0072     .reg_bits   = 8,
0073     .val_bits   = 32,
0074     .reg_stride = 4,
0075     .max_register   = RTC_REG4,
0076     .fast_io    = true,
0077 };
0078
0079 /* RTC front-end serialiser controls */
0080
0081 static void meson_rtc_sclk_pulse(struct meson_rtc *rtc)
0082 {
0083     udelay(5);
0084     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0);
0085     udelay(5);
0086     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK,
0087                RTC_ADDR0_LINE_SCLK);
0088 }
0089
0090 static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit)
0091 {
0092     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI,
0093                bit ? RTC_ADDR0_LINE_SDI : 0);
0094     meson_rtc_sclk_pulse(rtc);
0095 }
0096
0097 static void meson_rtc_send_bits(struct meson_rtc *rtc, u32 data,
0098                 unsigned int nr)
0099 {
0100     u32 bit = 1 << (nr - 1);
0101
0102     while (bit) {
0103         meson_rtc_send_bit(rtc, data & bit);
0104         bit >>= 1;
0105     }
0106 }
0107
0108 static void meson_rtc_set_dir(struct meson_rtc *rtc, u32 mode)
0109 {
0110     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0);
0111     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
0112     meson_rtc_send_bit(rtc, mode);
0113     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
0114 }
0115
0116 static u32 meson_rtc_get_data(struct meson_rtc *rtc)
0117 {
0118     u32 tmp, val = 0;
0119     int bit;
0120
0121     for (bit = 0; bit < RTC_DATA_BITS; bit++) {
0122         meson_rtc_sclk_pulse(rtc);
0123         val <<= 1;
0124
0125         regmap_read(rtc->peripheral, RTC_ADDR1, &tmp);
0126         val |= tmp & RTC_ADDR1_SDO;
0127     }
0128
0129     return val;
0130 }
0131
0132 static int meson_rtc_get_bus(struct meson_rtc *rtc)
0133 {
0134     int ret, retries;
0135     u32 val;
0136
0137     /* prepare bus for transfers, set all lines low */
0138     val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK;
0139     regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0);
0140
0141     for (retries = 0; retries < 3; retries++) {
0142         /* wait for the bus to be ready */
0143         if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val,
0144                           val & RTC_ADDR1_S_READY, 10,
0145                           10000))
0146             return 0;
0147
0148         dev_warn(rtc->dev, "failed to get bus, resetting RTC\n");
0149
0150         ret = reset_control_reset(rtc->reset);
0151         if (ret)
0152             return ret;
0153     }
0154
0155     dev_err(rtc->dev, "bus is not ready\n");
0156     return -ETIMEDOUT;
0157 }
0158
0159 static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg,
0160                      unsigned int *data)
0161 {
0162     struct meson_rtc *rtc = context;
0163     int ret;
0164
0165     ret = meson_rtc_get_bus(rtc);
0166     if (ret)
0167         return ret;
0168
0169     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
0170                RTC_ADDR0_LINE_SEN);
0171     meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
0172     meson_rtc_set_dir(rtc, 0);
0173     *data = meson_rtc_get_data(rtc);
0174
0175     return 0;
0176 }
0177
0178 static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg,
0179                       unsigned int data)
0180 {
0181     struct meson_rtc *rtc = context;
0182     int ret;
0183
0184     ret = meson_rtc_get_bus(rtc);
0185     if (ret)
0186         return ret;
0187
0188     regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
0189                RTC_ADDR0_LINE_SEN);
0190     meson_rtc_send_bits(rtc, data, RTC_DATA_BITS);
0191     meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
0192     meson_rtc_set_dir(rtc, 1);
0193
0194     return 0;
0195 }
0196
0197 static const struct regmap_bus meson_rtc_serial_bus = {
0198     .reg_read   = meson_rtc_serial_bus_reg_read,
0199     .reg_write  = meson_rtc_serial_bus_reg_write,
0200 };
0201
0202 static const struct regmap_config meson_rtc_serial_regmap_config = {
0203     .name       = "serial-registers",
0204     .reg_bits   = 4,
0205     .reg_stride = 1,
0206     .val_bits   = 32,
0207     .max_register   = RTC_REGMEM_3,
0208     .fast_io    = false,
0209 };
0210
0211 static int meson_rtc_write_static(struct meson_rtc *rtc, u32 data)
0212 {
0213     u32 tmp;
0214
0215     regmap_write(rtc->peripheral, RTC_REG4,
0216              FIELD_PREP(RTC_REG4_STATIC_VALUE, (data >> 8)));
0217
0218     /* write the static value and start the auto serializer */
0219     tmp = FIELD_PREP(RTC_ADDR0_DATA, (data & 0xff)) | RTC_ADDR0_START_SER;
0220     regmap_update_bits(rtc->peripheral, RTC_ADDR0,
0221                RTC_ADDR0_DATA | RTC_ADDR0_START_SER, tmp);
0222
0223     /* wait for the auto serializer to complete */
0224     return regmap_read_poll_timeout(rtc->peripheral, RTC_REG4, tmp,
0225                     !(tmp & RTC_ADDR0_WAIT_SER), 10,
0226                     10000);
0227 }
0228
0229 /* RTC interface layer functions */
0230
0231 static int meson_rtc_gettime(struct device *dev, struct rtc_time *tm)
0232 {
0233     struct meson_rtc *rtc = dev_get_drvdata(dev);
0234     u32 time;
0235     int ret;
0236
0237     ret = regmap_read(rtc->serial, RTC_COUNTER, &time);
0238     if (!ret)
0239         rtc_time64_to_tm(time, tm);
0240
0241     return ret;
0242 }
0243
0244 static int meson_rtc_settime(struct device *dev, struct rtc_time *tm)
0245 {
0246     struct meson_rtc *rtc = dev_get_drvdata(dev);
0247
0248     return regmap_write(rtc->serial, RTC_COUNTER, rtc_tm_to_time64(tm));
0249 }
0250
0251 static const struct rtc_class_ops meson_rtc_ops = {
0252     .read_time  = meson_rtc_gettime,
0253     .set_time   = meson_rtc_settime,
0254 };
0255
0256 /* NVMEM interface layer functions */
0257
0258 static int meson_rtc_regmem_read(void *context, unsigned int offset,
0259                  void *buf, size_t bytes)
0260 {
0261     struct meson_rtc *rtc = context;
0262     unsigned int read_offset, read_size;
0263
0264     read_offset = RTC_REGMEM_0 + (offset / 4);
0265     read_size = bytes / 4;
0266
0267     return regmap_bulk_read(rtc->serial, read_offset, buf, read_size);
0268 }
0269
0270 static int meson_rtc_regmem_write(void *context, unsigned int offset,
0271                   void *buf, size_t bytes)
0272 {
0273     struct meson_rtc *rtc = context;
0274     unsigned int write_offset, write_size;
0275
0276     write_offset = RTC_REGMEM_0 + (offset / 4);
0277     write_size = bytes / 4;
0278
0279     return regmap_bulk_write(rtc->serial, write_offset, buf, write_size);
0280 }
0281
0282 static int meson_rtc_probe(struct platform_device *pdev)
0283 {
0284     struct nvmem_config meson_rtc_nvmem_config = {
0285         .name = "meson-rtc-regmem",
0286         .type = NVMEM_TYPE_BATTERY_BACKED,
0287         .word_size = 4,
0288         .stride = 4,
0289         .size = 4 * 4,
0290         .reg_read = meson_rtc_regmem_read,
0291         .reg_write = meson_rtc_regmem_write,
0292     };
0293     struct device *dev = &pdev->dev;
0294     struct meson_rtc *rtc;
0295     void __iomem *base;
0296     int ret;
0297     u32 tm;
0298
0299     rtc = devm_kzalloc(dev, sizeof(struct meson_rtc), GFP_KERNEL);
0300     if (!rtc)
0301         return -ENOMEM;
0302
0303     rtc->rtc = devm_rtc_allocate_device(dev);
0304     if (IS_ERR(rtc->rtc))
0305         return PTR_ERR(rtc->rtc);
0306
0307     platform_set_drvdata(pdev, rtc);
0308
0309     rtc->dev = dev;
0310
0311     rtc->rtc->ops = &meson_rtc_ops;
0312     rtc->rtc->range_max = U32_MAX;
0313
0314     base = devm_platform_ioremap_resource(pdev, 0);
0315     if (IS_ERR(base))
0316         return PTR_ERR(base);
0317
0318     rtc->peripheral = devm_regmap_init_mmio(dev, base,
0319                     &meson_rtc_peripheral_regmap_config);
0320     if (IS_ERR(rtc->peripheral)) {
0321         dev_err(dev, "failed to create peripheral regmap\n");
0322         return PTR_ERR(rtc->peripheral);
0323     }
0324
0325     rtc->reset = devm_reset_control_get(dev, NULL);
0326     if (IS_ERR(rtc->reset)) {
0327         dev_err(dev, "missing reset line\n");
0328         return PTR_ERR(rtc->reset);
0329     }
0330
0331     rtc->vdd = devm_regulator_get(dev, "vdd");
0332     if (IS_ERR(rtc->vdd)) {
0333         dev_err(dev, "failed to get the vdd-supply\n");
0334         return PTR_ERR(rtc->vdd);
0335     }
0336
0337     ret = regulator_enable(rtc->vdd);
0338     if (ret) {
0339         dev_err(dev, "failed to enable vdd-supply\n");
0340         return ret;
0341     }
0342
0343     ret = meson_rtc_write_static(rtc, MESON_STATIC_DEFAULT);
0344     if (ret) {
0345         dev_err(dev, "failed to set static values\n");
0346         goto out_disable_vdd;
0347     }
0348
0349     rtc->serial = devm_regmap_init(dev, &meson_rtc_serial_bus, rtc,
0350                        &meson_rtc_serial_regmap_config);
0351     if (IS_ERR(rtc->serial)) {
0352         dev_err(dev, "failed to create serial regmap\n");
0353         ret = PTR_ERR(rtc->serial);
0354         goto out_disable_vdd;
0355     }
0356
0357     /*
0358      * check if we can read RTC counter, if not then the RTC is probably
0359      * not functional. If it isn't probably best to not bind.
0360      */
0361     ret = regmap_read(rtc->serial, RTC_COUNTER, &tm);
0362     if (ret) {
0363         dev_err(dev, "cannot read RTC counter, RTC not functional\n");
0364         goto out_disable_vdd;
0365     }
0366
0367     meson_rtc_nvmem_config.priv = rtc;
0368     ret = devm_rtc_nvmem_register(rtc->rtc, &meson_rtc_nvmem_config);
0369     if (ret)
0370         goto out_disable_vdd;
0371
0372     ret = devm_rtc_register_device(rtc->rtc);
0373     if (ret)
0374         goto out_disable_vdd;
0375
0376     return 0;
0377
0378 out_disable_vdd:
0379     regulator_disable(rtc->vdd);
0380     return ret;
0381 }
0382
0383 static const __maybe_unused struct of_device_id meson_rtc_dt_match[] = {
0384     { .compatible = "amlogic,meson6-rtc", },
0385     { .compatible = "amlogic,meson8-rtc", },
0386     { .compatible = "amlogic,meson8b-rtc", },
0387     { .compatible = "amlogic,meson8m2-rtc", },
0388     { },
0389 };
0390 MODULE_DEVICE_TABLE(of, meson_rtc_dt_match);
0391
0392 static struct platform_driver meson_rtc_driver = {
0393     .probe      = meson_rtc_probe,
0394     .driver     = {
0395         .name       = "meson-rtc",
0396         .of_match_table = of_match_ptr(meson_rtc_dt_match),
0397     },
0398 };
0399 module_platform_driver(meson_rtc_driver);
0400
0401 MODULE_DESCRIPTION("Amlogic Meson RTC Driver");
0402 MODULE_AUTHOR("Ben Dooks <ben.dooks@codethink.co.uk>");
0403 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0404 MODULE_LICENSE("GPL v2");
0405 MODULE_ALIAS("platform:meson-rtc");