drivers/rtc/rtc-mcp795.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SPI Driver for Microchip MCP795 RTC
0004  *
0005  * Copyright (C) Josef Gajdusek <atx@atx.name>
0006  *
0007  * based on other Linux RTC drivers
0008  *
0009  * Device datasheet:
0010  * https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
0011  */
0012
0013 #include <linux/module.h>
0014 #include <linux/kernel.h>
0015 #include <linux/device.h>
0016 #include <linux/printk.h>
0017 #include <linux/spi/spi.h>
0018 #include <linux/rtc.h>
0019 #include <linux/of.h>
0020 #include <linux/bcd.h>
0021 #include <linux/delay.h>
0022
0023 /* MCP795 Instructions, see datasheet table 3-1 */
0024 #define MCP795_EEREAD   0x03
0025 #define MCP795_EEWRITE  0x02
0026 #define MCP795_EEWRDI   0x04
0027 #define MCP795_EEWREN   0x06
0028 #define MCP795_SRREAD   0x05
0029 #define MCP795_SRWRITE  0x01
0030 #define MCP795_READ 0x13
0031 #define MCP795_WRITE    0x12
0032 #define MCP795_UNLOCK   0x14
0033 #define MCP795_IDWRITE  0x32
0034 #define MCP795_IDREAD   0x33
0035 #define MCP795_CLRWDT   0x44
0036 #define MCP795_CLRRAM   0x54
0037
0038 /* MCP795 RTCC registers, see datasheet table 4-1 */
0039 #define MCP795_REG_SECONDS  0x01
0040 #define MCP795_REG_DAY      0x04
0041 #define MCP795_REG_MONTH    0x06
0042 #define MCP795_REG_CONTROL  0x08
0043 #define MCP795_REG_ALM0_SECONDS 0x0C
0044 #define MCP795_REG_ALM0_DAY 0x0F
0045
0046 #define MCP795_ST_BIT       BIT(7)
0047 #define MCP795_24_BIT       BIT(6)
0048 #define MCP795_LP_BIT       BIT(5)
0049 #define MCP795_EXTOSC_BIT   BIT(3)
0050 #define MCP795_OSCON_BIT    BIT(5)
0051 #define MCP795_ALM0_BIT     BIT(4)
0052 #define MCP795_ALM1_BIT     BIT(5)
0053 #define MCP795_ALM0IF_BIT   BIT(3)
0054 #define MCP795_ALM0C0_BIT   BIT(4)
0055 #define MCP795_ALM0C1_BIT   BIT(5)
0056 #define MCP795_ALM0C2_BIT   BIT(6)
0057
0058 #define SEC_PER_DAY     (24 * 60 * 60)
0059
0060 static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
0061 {
0062     struct spi_device *spi = to_spi_device(dev);
0063     int ret;
0064     u8 tx[2];
0065
0066     tx[0] = MCP795_READ;
0067     tx[1] = addr;
0068     ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
0069
0070     if (ret)
0071         dev_err(dev, "Failed reading %d bytes from address %x.\n",
0072                     count, addr);
0073
0074     return ret;
0075 }
0076
0077 static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
0078 {
0079     struct spi_device *spi = to_spi_device(dev);
0080     int ret;
0081     u8 tx[257];
0082
0083     tx[0] = MCP795_WRITE;
0084     tx[1] = addr;
0085     memcpy(&tx[2], data, count);
0086
0087     ret = spi_write(spi, tx, 2 + count);
0088
0089     if (ret)
0090         dev_err(dev, "Failed to write %d bytes to address %x.\n",
0091                     count, addr);
0092
0093     return ret;
0094 }
0095
0096 static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
0097 {
0098     int ret;
0099     u8 tmp;
0100
0101     ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
0102     if (ret)
0103         return ret;
0104
0105     if ((tmp & mask) != state) {
0106         tmp = (tmp & ~mask) | state;
0107         ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
0108     }
0109
0110     return ret;
0111 }
0112
0113 static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
0114 {
0115     int retries = 5;
0116     int ret;
0117     u8 data;
0118
0119     ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
0120     if (ret)
0121         return ret;
0122     ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
0123     if (ret)
0124         return ret;
0125     *extosc = !!(data & MCP795_EXTOSC_BIT);
0126     ret = mcp795_rtcc_set_bits(
0127                 dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
0128     if (ret)
0129         return ret;
0130     /* wait for the OSCON bit to clear */
0131     do {
0132         usleep_range(700, 800);
0133         ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
0134         if (ret)
0135             break;
0136         if (!(data & MCP795_OSCON_BIT))
0137             break;
0138
0139     } while (--retries);
0140
0141     return !retries ? -EIO : ret;
0142 }
0143
0144 static int mcp795_start_oscillator(struct device *dev, bool *extosc)
0145 {
0146     if (extosc) {
0147         u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
0148         int ret;
0149
0150         ret = mcp795_rtcc_set_bits(
0151             dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
0152         if (ret)
0153             return ret;
0154     }
0155     return mcp795_rtcc_set_bits(
0156             dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
0157 }
0158
0159 /* Enable or disable Alarm 0 in RTC */
0160 static int mcp795_update_alarm(struct device *dev, bool enable)
0161 {
0162     int ret;
0163
0164     dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
0165
0166     if (enable) {
0167         /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
0168         ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
0169                     MCP795_ALM0IF_BIT, 0);
0170         if (ret)
0171             return ret;
0172         /* enable alarm 0 */
0173         ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
0174                     MCP795_ALM0_BIT, MCP795_ALM0_BIT);
0175     } else {
0176         /* disable alarm 0 and alarm 1 */
0177         ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
0178                     MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
0179     }
0180     return ret;
0181 }
0182
0183 static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
0184 {
0185     int ret;
0186     u8 data[7];
0187     bool extosc;
0188
0189     /* Stop RTC and store current value of EXTOSC bit */
0190     ret = mcp795_stop_oscillator(dev, &extosc);
0191     if (ret)
0192         return ret;
0193
0194     /* Read first, so we can leave config bits untouched */
0195     ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
0196
0197     if (ret)
0198         return ret;
0199
0200     data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
0201     data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
0202     data[2] = bin2bcd(tim->tm_hour);
0203     data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
0204     data[4] = bin2bcd(tim->tm_mday);
0205     data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
0206
0207     if (tim->tm_year > 100)
0208         tim->tm_year -= 100;
0209
0210     data[6] = bin2bcd(tim->tm_year);
0211
0212     /* Always write the date and month using a separate Write command.
0213      * This is a workaround for a know silicon issue that some combinations
0214      * of date and month values may result in the date being reset to 1.
0215      */
0216     ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
0217     if (ret)
0218         return ret;
0219
0220     ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
0221     if (ret)
0222         return ret;
0223
0224     /* Start back RTC and restore previous value of EXTOSC bit.
0225      * There is no need to clear EXTOSC bit when the previous value was 0
0226      * because it was already cleared when stopping the RTC oscillator.
0227      */
0228     ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
0229     if (ret)
0230         return ret;
0231
0232     dev_dbg(dev, "Set mcp795: %ptR\n", tim);
0233
0234     return 0;
0235 }
0236
0237 static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
0238 {
0239     int ret;
0240     u8 data[7];
0241
0242     ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
0243
0244     if (ret)
0245         return ret;
0246
0247     tim->tm_sec = bcd2bin(data[0] & 0x7F);
0248     tim->tm_min = bcd2bin(data[1] & 0x7F);
0249     tim->tm_hour    = bcd2bin(data[2] & 0x3F);
0250     tim->tm_wday    = bcd2bin(data[3] & 0x07) - 1;
0251     tim->tm_mday    = bcd2bin(data[4] & 0x3F);
0252     tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
0253     tim->tm_year    = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
0254
0255     dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
0256
0257     return 0;
0258 }
0259
0260 static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
0261 {
0262     struct rtc_time now_tm;
0263     time64_t now;
0264     time64_t later;
0265     u8 tmp[6];
0266     int ret;
0267
0268     /* Read current time from RTC hardware */
0269     ret = mcp795_read_time(dev, &now_tm);
0270     if (ret)
0271         return ret;
0272     /* Get the number of seconds since 1970 */
0273     now = rtc_tm_to_time64(&now_tm);
0274     later = rtc_tm_to_time64(&alm->time);
0275     if (later <= now)
0276         return -EINVAL;
0277     /* make sure alarm fires within the next one year */
0278     if ((later - now) >=
0279         (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
0280         return -EDOM;
0281     /* disable alarm */
0282     ret = mcp795_update_alarm(dev, false);
0283     if (ret)
0284         return ret;
0285     /* Read registers, so we can leave configuration bits untouched */
0286     ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
0287     if (ret)
0288         return ret;
0289
0290     alm->time.tm_year   = -1;
0291     alm->time.tm_isdst  = -1;
0292     alm->time.tm_yday   = -1;
0293
0294     tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
0295     tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
0296     tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
0297     tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
0298     /* set alarm match: seconds, minutes, hour, day, date and month */
0299     tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
0300     tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
0301     tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
0302
0303     ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
0304     if (ret)
0305         return ret;
0306
0307     /* enable alarm if requested */
0308     if (alm->enabled) {
0309         ret = mcp795_update_alarm(dev, true);
0310         if (ret)
0311             return ret;
0312         dev_dbg(dev, "Alarm IRQ armed\n");
0313     }
0314     dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
0315         &alm->time, alm->time.tm_wday, &alm->time);
0316     return 0;
0317 }
0318
0319 static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
0320 {
0321     u8 data[6];
0322     int ret;
0323
0324     ret = mcp795_rtcc_read(
0325             dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
0326     if (ret)
0327         return ret;
0328
0329     alm->time.tm_sec    = bcd2bin(data[0] & 0x7F);
0330     alm->time.tm_min    = bcd2bin(data[1] & 0x7F);
0331     alm->time.tm_hour   = bcd2bin(data[2] & 0x1F);
0332     alm->time.tm_wday   = bcd2bin(data[3] & 0x07) - 1;
0333     alm->time.tm_mday   = bcd2bin(data[4] & 0x3F);
0334     alm->time.tm_mon    = bcd2bin(data[5] & 0x1F) - 1;
0335     alm->time.tm_year   = -1;
0336     alm->time.tm_isdst  = -1;
0337     alm->time.tm_yday   = -1;
0338
0339     dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
0340         &alm->time, alm->time.tm_wday, &alm->time);
0341     return 0;
0342 }
0343
0344 static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
0345 {
0346     return mcp795_update_alarm(dev, !!enabled);
0347 }
0348
0349 static irqreturn_t mcp795_irq(int irq, void *data)
0350 {
0351     struct spi_device *spi = data;
0352     struct rtc_device *rtc = spi_get_drvdata(spi);
0353     int ret;
0354
0355     rtc_lock(rtc);
0356
0357     /* Disable alarm.
0358      * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
0359      * because it is done every time when alarm is enabled.
0360      */
0361     ret = mcp795_update_alarm(&spi->dev, false);
0362     if (ret)
0363         dev_err(&spi->dev,
0364             "Failed to disable alarm in IRQ (ret=%d)\n", ret);
0365     rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
0366
0367     rtc_unlock(rtc);
0368
0369     return IRQ_HANDLED;
0370 }
0371
0372 static const struct rtc_class_ops mcp795_rtc_ops = {
0373         .read_time = mcp795_read_time,
0374         .set_time = mcp795_set_time,
0375         .read_alarm = mcp795_read_alarm,
0376         .set_alarm = mcp795_set_alarm,
0377         .alarm_irq_enable = mcp795_alarm_irq_enable
0378 };
0379
0380 static int mcp795_probe(struct spi_device *spi)
0381 {
0382     struct rtc_device *rtc;
0383     int ret;
0384
0385     spi->mode = SPI_MODE_0;
0386     spi->bits_per_word = 8;
0387     ret = spi_setup(spi);
0388     if (ret) {
0389         dev_err(&spi->dev, "Unable to setup SPI\n");
0390         return ret;
0391     }
0392
0393     /* Start the oscillator but don't set the value of EXTOSC bit */
0394     mcp795_start_oscillator(&spi->dev, NULL);
0395     /* Clear the 12 hour mode flag*/
0396     mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
0397
0398     rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
0399                     &mcp795_rtc_ops, THIS_MODULE);
0400     if (IS_ERR(rtc))
0401         return PTR_ERR(rtc);
0402
0403     spi_set_drvdata(spi, rtc);
0404
0405     if (spi->irq > 0) {
0406         dev_dbg(&spi->dev, "Alarm support enabled\n");
0407
0408         /* Clear any pending alarm (ALM0IF bit) before requesting
0409          * the interrupt.
0410          */
0411         mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
0412                     MCP795_ALM0IF_BIT, 0);
0413         ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
0414                 mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
0415                 dev_name(&rtc->dev), spi);
0416         if (ret)
0417             dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
0418                         spi->irq, ret);
0419         else
0420             device_init_wakeup(&spi->dev, true);
0421     }
0422     return 0;
0423 }
0424
0425 #ifdef CONFIG_OF
0426 static const struct of_device_id mcp795_of_match[] = {
0427     { .compatible = "maxim,mcp795" },
0428     { }
0429 };
0430 MODULE_DEVICE_TABLE(of, mcp795_of_match);
0431 #endif
0432
0433 static const struct spi_device_id mcp795_spi_ids[] = {
0434     { .name = "mcp795" },
0435     { }
0436 };
0437 MODULE_DEVICE_TABLE(spi, mcp795_spi_ids);
0438
0439 static struct spi_driver mcp795_driver = {
0440         .driver = {
0441                 .name = "rtc-mcp795",
0442                 .of_match_table = of_match_ptr(mcp795_of_match),
0443         },
0444         .probe = mcp795_probe,
0445         .id_table = mcp795_spi_ids,
0446 };
0447
0448 module_spi_driver(mcp795_driver);
0449
0450 MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
0451 MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
0452 MODULE_LICENSE("GPL");
0453 MODULE_ALIAS("spi:mcp795");