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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // RTC driver for Maxim MAX77686 and MAX77802
0004 //
0005 // Copyright (C) 2012 Samsung Electronics Co.Ltd
0006 //
0007 //  based on rtc-max8997.c
0008 
0009 #include <linux/i2c.h>
0010 #include <linux/slab.h>
0011 #include <linux/rtc.h>
0012 #include <linux/delay.h>
0013 #include <linux/mutex.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/mfd/max77686-private.h>
0017 #include <linux/irqdomain.h>
0018 #include <linux/regmap.h>
0019 
0020 #define MAX77686_I2C_ADDR_RTC       (0x0C >> 1)
0021 #define MAX77620_I2C_ADDR_RTC       0x68
0022 #define MAX77714_I2C_ADDR_RTC       0x48
0023 #define MAX77686_INVALID_I2C_ADDR   (-1)
0024 
0025 /* Define non existing register */
0026 #define MAX77686_INVALID_REG        (-1)
0027 
0028 /* RTC Control Register */
0029 #define BCD_EN_SHIFT            0
0030 #define BCD_EN_MASK         BIT(BCD_EN_SHIFT)
0031 #define MODEL24_SHIFT           1
0032 #define MODEL24_MASK            BIT(MODEL24_SHIFT)
0033 /* RTC Update Register1 */
0034 #define RTC_UDR_SHIFT           0
0035 #define RTC_UDR_MASK            BIT(RTC_UDR_SHIFT)
0036 #define RTC_RBUDR_SHIFT         4
0037 #define RTC_RBUDR_MASK          BIT(RTC_RBUDR_SHIFT)
0038 /* RTC Alarm Enable */
0039 #define ALARM_ENABLE_SHIFT      7
0040 #define ALARM_ENABLE_MASK       BIT(ALARM_ENABLE_SHIFT)
0041 
0042 #define REG_RTC_NONE            0xdeadbeef
0043 
0044 /*
0045  * MAX77802 has separate register (RTCAE1) for alarm enable instead
0046  * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
0047  * as in done in MAX77686.
0048  */
0049 #define MAX77802_ALARM_ENABLE_VALUE 0x77
0050 
0051 enum {
0052     RTC_SEC = 0,
0053     RTC_MIN,
0054     RTC_HOUR,
0055     RTC_WEEKDAY,
0056     RTC_MONTH,
0057     RTC_YEAR,
0058     RTC_MONTHDAY,
0059     RTC_NR_TIME
0060 };
0061 
0062 /**
0063  * struct max77686_rtc_driver_data - model-specific configuration
0064  * @delay: Minimum usecs needed for a RTC update
0065  * @mask: Mask used to read RTC registers value
0066  * @map: Registers offset to I2C addresses map
0067  * @alarm_enable_reg: Has a separate alarm enable register?
0068  * @rtc_i2c_addr: I2C address for RTC block
0069  * @rtc_irq_from_platform: RTC interrupt via platform resource
0070  * @alarm_pending_status_reg: Pending alarm status register
0071  * @rtc_irq_chip: RTC IRQ CHIP for regmap
0072  * @regmap_config: regmap configuration for the chip
0073  */
0074 struct max77686_rtc_driver_data {
0075     unsigned long       delay;
0076     u8          mask;
0077     const unsigned int  *map;
0078     bool            alarm_enable_reg;
0079     int         rtc_i2c_addr;
0080     bool            rtc_irq_from_platform;
0081     int         alarm_pending_status_reg;
0082     const struct regmap_irq_chip *rtc_irq_chip;
0083     const struct regmap_config *regmap_config;
0084 };
0085 
0086 struct max77686_rtc_info {
0087     struct device       *dev;
0088     struct i2c_client   *rtc;
0089     struct rtc_device   *rtc_dev;
0090     struct mutex        lock;
0091 
0092     struct regmap       *regmap;
0093     struct regmap       *rtc_regmap;
0094 
0095     const struct max77686_rtc_driver_data *drv_data;
0096     struct regmap_irq_chip_data *rtc_irq_data;
0097 
0098     int rtc_irq;
0099     int virq;
0100 };
0101 
0102 enum MAX77686_RTC_OP {
0103     MAX77686_RTC_WRITE,
0104     MAX77686_RTC_READ,
0105 };
0106 
0107 /* These are not registers but just offsets that are mapped to addresses */
0108 enum max77686_rtc_reg_offset {
0109     REG_RTC_CONTROLM = 0,
0110     REG_RTC_CONTROL,
0111     REG_RTC_UPDATE0,
0112     REG_WTSR_SMPL_CNTL,
0113     REG_RTC_SEC,
0114     REG_RTC_MIN,
0115     REG_RTC_HOUR,
0116     REG_RTC_WEEKDAY,
0117     REG_RTC_MONTH,
0118     REG_RTC_YEAR,
0119     REG_RTC_MONTHDAY,
0120     REG_ALARM1_SEC,
0121     REG_ALARM1_MIN,
0122     REG_ALARM1_HOUR,
0123     REG_ALARM1_WEEKDAY,
0124     REG_ALARM1_MONTH,
0125     REG_ALARM1_YEAR,
0126     REG_ALARM1_DATE,
0127     REG_ALARM2_SEC,
0128     REG_ALARM2_MIN,
0129     REG_ALARM2_HOUR,
0130     REG_ALARM2_WEEKDAY,
0131     REG_ALARM2_MONTH,
0132     REG_ALARM2_YEAR,
0133     REG_ALARM2_DATE,
0134     REG_RTC_AE1,
0135     REG_RTC_END,
0136 };
0137 
0138 /* Maps RTC registers offset to the MAX77686 register addresses */
0139 static const unsigned int max77686_map[REG_RTC_END] = {
0140     [REG_RTC_CONTROLM]   = MAX77686_RTC_CONTROLM,
0141     [REG_RTC_CONTROL]    = MAX77686_RTC_CONTROL,
0142     [REG_RTC_UPDATE0]    = MAX77686_RTC_UPDATE0,
0143     [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
0144     [REG_RTC_SEC]        = MAX77686_RTC_SEC,
0145     [REG_RTC_MIN]        = MAX77686_RTC_MIN,
0146     [REG_RTC_HOUR]       = MAX77686_RTC_HOUR,
0147     [REG_RTC_WEEKDAY]    = MAX77686_RTC_WEEKDAY,
0148     [REG_RTC_MONTH]      = MAX77686_RTC_MONTH,
0149     [REG_RTC_YEAR]       = MAX77686_RTC_YEAR,
0150     [REG_RTC_MONTHDAY]   = MAX77686_RTC_MONTHDAY,
0151     [REG_ALARM1_SEC]     = MAX77686_ALARM1_SEC,
0152     [REG_ALARM1_MIN]     = MAX77686_ALARM1_MIN,
0153     [REG_ALARM1_HOUR]    = MAX77686_ALARM1_HOUR,
0154     [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
0155     [REG_ALARM1_MONTH]   = MAX77686_ALARM1_MONTH,
0156     [REG_ALARM1_YEAR]    = MAX77686_ALARM1_YEAR,
0157     [REG_ALARM1_DATE]    = MAX77686_ALARM1_DATE,
0158     [REG_ALARM2_SEC]     = MAX77686_ALARM2_SEC,
0159     [REG_ALARM2_MIN]     = MAX77686_ALARM2_MIN,
0160     [REG_ALARM2_HOUR]    = MAX77686_ALARM2_HOUR,
0161     [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
0162     [REG_ALARM2_MONTH]   = MAX77686_ALARM2_MONTH,
0163     [REG_ALARM2_YEAR]    = MAX77686_ALARM2_YEAR,
0164     [REG_ALARM2_DATE]    = MAX77686_ALARM2_DATE,
0165     [REG_RTC_AE1]        = REG_RTC_NONE,
0166 };
0167 
0168 static const struct regmap_irq max77686_rtc_irqs[] = {
0169     /* RTC interrupts */
0170     REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
0171     REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
0172     REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
0173     REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
0174     REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
0175     REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
0176 };
0177 
0178 static const struct regmap_irq_chip max77686_rtc_irq_chip = {
0179     .name       = "max77686-rtc",
0180     .status_base    = MAX77686_RTC_INT,
0181     .mask_base  = MAX77686_RTC_INTM,
0182     .num_regs   = 1,
0183     .irqs       = max77686_rtc_irqs,
0184     .num_irqs   = ARRAY_SIZE(max77686_rtc_irqs),
0185 };
0186 
0187 static const struct regmap_config max77686_rtc_regmap_config = {
0188     .reg_bits = 8,
0189     .val_bits = 8,
0190 };
0191 
0192 static const struct max77686_rtc_driver_data max77686_drv_data = {
0193     .delay = 16000,
0194     .mask  = 0x7f,
0195     .map   = max77686_map,
0196     .alarm_enable_reg  = false,
0197     .rtc_irq_from_platform = false,
0198     .alarm_pending_status_reg = MAX77686_REG_STATUS2,
0199     .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
0200     .rtc_irq_chip = &max77686_rtc_irq_chip,
0201     .regmap_config = &max77686_rtc_regmap_config,
0202 };
0203 
0204 static const struct regmap_irq_chip max77714_rtc_irq_chip = {
0205     .name       = "max77714-rtc",
0206     .status_base    = MAX77686_RTC_INT,
0207     .mask_base  = MAX77686_RTC_INTM,
0208     .num_regs   = 1,
0209     .irqs       = max77686_rtc_irqs,
0210     .num_irqs   = ARRAY_SIZE(max77686_rtc_irqs) - 1, /* no WTSR on 77714 */
0211 };
0212 
0213 static const struct max77686_rtc_driver_data max77714_drv_data = {
0214     .delay = 16000,
0215     .mask  = 0x7f,
0216     .map   = max77686_map,
0217     .alarm_enable_reg = false,
0218     .rtc_irq_from_platform = false,
0219     /* On MAX77714 RTCA1 is BIT 1 of RTCINT (0x00). Not supported by this driver. */
0220     .alarm_pending_status_reg = MAX77686_INVALID_REG,
0221     .rtc_i2c_addr = MAX77714_I2C_ADDR_RTC,
0222     .rtc_irq_chip = &max77714_rtc_irq_chip,
0223     .regmap_config = &max77686_rtc_regmap_config,
0224 };
0225 
0226 static const struct regmap_config max77620_rtc_regmap_config = {
0227     .reg_bits = 8,
0228     .val_bits = 8,
0229     .use_single_write = true,
0230 };
0231 
0232 static const struct max77686_rtc_driver_data max77620_drv_data = {
0233     .delay = 16000,
0234     .mask  = 0x7f,
0235     .map   = max77686_map,
0236     .alarm_enable_reg  = false,
0237     .rtc_irq_from_platform = true,
0238     .alarm_pending_status_reg = MAX77686_INVALID_REG,
0239     .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
0240     .rtc_irq_chip = &max77686_rtc_irq_chip,
0241     .regmap_config = &max77620_rtc_regmap_config,
0242 };
0243 
0244 static const unsigned int max77802_map[REG_RTC_END] = {
0245     [REG_RTC_CONTROLM]   = MAX77802_RTC_CONTROLM,
0246     [REG_RTC_CONTROL]    = MAX77802_RTC_CONTROL,
0247     [REG_RTC_UPDATE0]    = MAX77802_RTC_UPDATE0,
0248     [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
0249     [REG_RTC_SEC]        = MAX77802_RTC_SEC,
0250     [REG_RTC_MIN]        = MAX77802_RTC_MIN,
0251     [REG_RTC_HOUR]       = MAX77802_RTC_HOUR,
0252     [REG_RTC_WEEKDAY]    = MAX77802_RTC_WEEKDAY,
0253     [REG_RTC_MONTH]      = MAX77802_RTC_MONTH,
0254     [REG_RTC_YEAR]       = MAX77802_RTC_YEAR,
0255     [REG_RTC_MONTHDAY]   = MAX77802_RTC_MONTHDAY,
0256     [REG_ALARM1_SEC]     = MAX77802_ALARM1_SEC,
0257     [REG_ALARM1_MIN]     = MAX77802_ALARM1_MIN,
0258     [REG_ALARM1_HOUR]    = MAX77802_ALARM1_HOUR,
0259     [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
0260     [REG_ALARM1_MONTH]   = MAX77802_ALARM1_MONTH,
0261     [REG_ALARM1_YEAR]    = MAX77802_ALARM1_YEAR,
0262     [REG_ALARM1_DATE]    = MAX77802_ALARM1_DATE,
0263     [REG_ALARM2_SEC]     = MAX77802_ALARM2_SEC,
0264     [REG_ALARM2_MIN]     = MAX77802_ALARM2_MIN,
0265     [REG_ALARM2_HOUR]    = MAX77802_ALARM2_HOUR,
0266     [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
0267     [REG_ALARM2_MONTH]   = MAX77802_ALARM2_MONTH,
0268     [REG_ALARM2_YEAR]    = MAX77802_ALARM2_YEAR,
0269     [REG_ALARM2_DATE]    = MAX77802_ALARM2_DATE,
0270     [REG_RTC_AE1]        = MAX77802_RTC_AE1,
0271 };
0272 
0273 static const struct regmap_irq_chip max77802_rtc_irq_chip = {
0274     .name       = "max77802-rtc",
0275     .status_base    = MAX77802_RTC_INT,
0276     .mask_base  = MAX77802_RTC_INTM,
0277     .num_regs   = 1,
0278     .irqs       = max77686_rtc_irqs, /* same masks as 77686 */
0279     .num_irqs   = ARRAY_SIZE(max77686_rtc_irqs),
0280 };
0281 
0282 static const struct max77686_rtc_driver_data max77802_drv_data = {
0283     .delay = 200,
0284     .mask  = 0xff,
0285     .map   = max77802_map,
0286     .alarm_enable_reg  = true,
0287     .rtc_irq_from_platform = false,
0288     .alarm_pending_status_reg = MAX77686_REG_STATUS2,
0289     .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
0290     .rtc_irq_chip = &max77802_rtc_irq_chip,
0291 };
0292 
0293 static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
0294                     struct max77686_rtc_info *info)
0295 {
0296     u8 mask = info->drv_data->mask;
0297 
0298     tm->tm_sec = data[RTC_SEC] & mask;
0299     tm->tm_min = data[RTC_MIN] & mask;
0300     tm->tm_hour = data[RTC_HOUR] & 0x1f;
0301 
0302     /* Only a single bit is set in data[], so fls() would be equivalent */
0303     tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
0304     tm->tm_mday = data[RTC_MONTHDAY] & 0x1f;
0305     tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
0306     tm->tm_year = data[RTC_YEAR] & mask;
0307     tm->tm_yday = 0;
0308     tm->tm_isdst = 0;
0309 
0310     /*
0311      * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
0312      * year values are just 0..99 so add 100 to support up to 2099.
0313      */
0314     if (!info->drv_data->alarm_enable_reg)
0315         tm->tm_year += 100;
0316 }
0317 
0318 static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
0319                    struct max77686_rtc_info *info)
0320 {
0321     data[RTC_SEC] = tm->tm_sec;
0322     data[RTC_MIN] = tm->tm_min;
0323     data[RTC_HOUR] = tm->tm_hour;
0324     data[RTC_WEEKDAY] = 1 << tm->tm_wday;
0325     data[RTC_MONTHDAY] = tm->tm_mday;
0326     data[RTC_MONTH] = tm->tm_mon + 1;
0327 
0328     if (info->drv_data->alarm_enable_reg) {
0329         data[RTC_YEAR] = tm->tm_year;
0330         return 0;
0331     }
0332 
0333     data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
0334 
0335     if (tm->tm_year < 100) {
0336         dev_err(info->dev, "RTC cannot handle the year %d.\n",
0337             1900 + tm->tm_year);
0338         return -EINVAL;
0339     }
0340 
0341     return 0;
0342 }
0343 
0344 static int max77686_rtc_update(struct max77686_rtc_info *info,
0345                    enum MAX77686_RTC_OP op)
0346 {
0347     int ret;
0348     unsigned int data;
0349     unsigned long delay = info->drv_data->delay;
0350 
0351     if (op == MAX77686_RTC_WRITE)
0352         data = 1 << RTC_UDR_SHIFT;
0353     else
0354         data = 1 << RTC_RBUDR_SHIFT;
0355 
0356     ret = regmap_update_bits(info->rtc_regmap,
0357                  info->drv_data->map[REG_RTC_UPDATE0],
0358                  data, data);
0359     if (ret < 0)
0360         dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
0361             ret, data);
0362     else {
0363         /* Minimum delay required before RTC update. */
0364         usleep_range(delay, delay * 2);
0365     }
0366 
0367     return ret;
0368 }
0369 
0370 static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
0371 {
0372     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0373     u8 data[RTC_NR_TIME];
0374     int ret;
0375 
0376     mutex_lock(&info->lock);
0377 
0378     ret = max77686_rtc_update(info, MAX77686_RTC_READ);
0379     if (ret < 0)
0380         goto out;
0381 
0382     ret = regmap_bulk_read(info->rtc_regmap,
0383                    info->drv_data->map[REG_RTC_SEC],
0384                    data, ARRAY_SIZE(data));
0385     if (ret < 0) {
0386         dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
0387         goto out;
0388     }
0389 
0390     max77686_rtc_data_to_tm(data, tm, info);
0391 
0392 out:
0393     mutex_unlock(&info->lock);
0394     return ret;
0395 }
0396 
0397 static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
0398 {
0399     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0400     u8 data[RTC_NR_TIME];
0401     int ret;
0402 
0403     ret = max77686_rtc_tm_to_data(tm, data, info);
0404     if (ret < 0)
0405         return ret;
0406 
0407     mutex_lock(&info->lock);
0408 
0409     ret = regmap_bulk_write(info->rtc_regmap,
0410                 info->drv_data->map[REG_RTC_SEC],
0411                 data, ARRAY_SIZE(data));
0412     if (ret < 0) {
0413         dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
0414         goto out;
0415     }
0416 
0417     ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
0418 
0419 out:
0420     mutex_unlock(&info->lock);
0421     return ret;
0422 }
0423 
0424 static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0425 {
0426     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0427     u8 data[RTC_NR_TIME];
0428     unsigned int val;
0429     const unsigned int *map = info->drv_data->map;
0430     int i, ret;
0431 
0432     mutex_lock(&info->lock);
0433 
0434     ret = max77686_rtc_update(info, MAX77686_RTC_READ);
0435     if (ret < 0)
0436         goto out;
0437 
0438     ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
0439                    data, ARRAY_SIZE(data));
0440     if (ret < 0) {
0441         dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
0442         goto out;
0443     }
0444 
0445     max77686_rtc_data_to_tm(data, &alrm->time, info);
0446 
0447     alrm->enabled = 0;
0448 
0449     if (info->drv_data->alarm_enable_reg) {
0450         if (map[REG_RTC_AE1] == REG_RTC_NONE) {
0451             ret = -EINVAL;
0452             dev_err(info->dev,
0453                 "alarm enable register not set(%d)\n", ret);
0454             goto out;
0455         }
0456 
0457         ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
0458         if (ret < 0) {
0459             dev_err(info->dev,
0460                 "fail to read alarm enable(%d)\n", ret);
0461             goto out;
0462         }
0463 
0464         if (val)
0465             alrm->enabled = 1;
0466     } else {
0467         for (i = 0; i < ARRAY_SIZE(data); i++) {
0468             if (data[i] & ALARM_ENABLE_MASK) {
0469                 alrm->enabled = 1;
0470                 break;
0471             }
0472         }
0473     }
0474 
0475     alrm->pending = 0;
0476 
0477     if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
0478         goto out;
0479 
0480     ret = regmap_read(info->regmap,
0481               info->drv_data->alarm_pending_status_reg, &val);
0482     if (ret < 0) {
0483         dev_err(info->dev,
0484             "Fail to read alarm pending status reg(%d)\n", ret);
0485         goto out;
0486     }
0487 
0488     if (val & (1 << 4)) /* RTCA1 */
0489         alrm->pending = 1;
0490 
0491 out:
0492     mutex_unlock(&info->lock);
0493     return ret;
0494 }
0495 
0496 static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
0497 {
0498     u8 data[RTC_NR_TIME];
0499     int ret, i;
0500     struct rtc_time tm;
0501     const unsigned int *map = info->drv_data->map;
0502 
0503     if (!mutex_is_locked(&info->lock))
0504         dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
0505 
0506     ret = max77686_rtc_update(info, MAX77686_RTC_READ);
0507     if (ret < 0)
0508         goto out;
0509 
0510     if (info->drv_data->alarm_enable_reg) {
0511         if (map[REG_RTC_AE1] == REG_RTC_NONE) {
0512             ret = -EINVAL;
0513             dev_err(info->dev,
0514                 "alarm enable register not set(%d)\n", ret);
0515             goto out;
0516         }
0517 
0518         ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
0519     } else {
0520         ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
0521                        data, ARRAY_SIZE(data));
0522         if (ret < 0) {
0523             dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
0524             goto out;
0525         }
0526 
0527         max77686_rtc_data_to_tm(data, &tm, info);
0528 
0529         for (i = 0; i < ARRAY_SIZE(data); i++)
0530             data[i] &= ~ALARM_ENABLE_MASK;
0531 
0532         ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
0533                     data, ARRAY_SIZE(data));
0534     }
0535 
0536     if (ret < 0) {
0537         dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
0538         goto out;
0539     }
0540 
0541     ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
0542 out:
0543     return ret;
0544 }
0545 
0546 static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
0547 {
0548     u8 data[RTC_NR_TIME];
0549     int ret;
0550     struct rtc_time tm;
0551     const unsigned int *map = info->drv_data->map;
0552 
0553     if (!mutex_is_locked(&info->lock))
0554         dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
0555 
0556     ret = max77686_rtc_update(info, MAX77686_RTC_READ);
0557     if (ret < 0)
0558         goto out;
0559 
0560     if (info->drv_data->alarm_enable_reg) {
0561         ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
0562                    MAX77802_ALARM_ENABLE_VALUE);
0563     } else {
0564         ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
0565                        data, ARRAY_SIZE(data));
0566         if (ret < 0) {
0567             dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
0568             goto out;
0569         }
0570 
0571         max77686_rtc_data_to_tm(data, &tm, info);
0572 
0573         data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
0574         data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
0575         data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
0576         data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
0577         if (data[RTC_MONTH] & 0xf)
0578             data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
0579         if (data[RTC_YEAR] & info->drv_data->mask)
0580             data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
0581         if (data[RTC_MONTHDAY] & 0x1f)
0582             data[RTC_MONTHDAY] |= (1 << ALARM_ENABLE_SHIFT);
0583 
0584         ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
0585                     data, ARRAY_SIZE(data));
0586     }
0587 
0588     if (ret < 0) {
0589         dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
0590         goto out;
0591     }
0592 
0593     ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
0594 out:
0595     return ret;
0596 }
0597 
0598 static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0599 {
0600     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0601     u8 data[RTC_NR_TIME];
0602     int ret;
0603 
0604     ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
0605     if (ret < 0)
0606         return ret;
0607 
0608     mutex_lock(&info->lock);
0609 
0610     ret = max77686_rtc_stop_alarm(info);
0611     if (ret < 0)
0612         goto out;
0613 
0614     ret = regmap_bulk_write(info->rtc_regmap,
0615                 info->drv_data->map[REG_ALARM1_SEC],
0616                 data, ARRAY_SIZE(data));
0617 
0618     if (ret < 0) {
0619         dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
0620         goto out;
0621     }
0622 
0623     ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
0624     if (ret < 0)
0625         goto out;
0626 
0627     if (alrm->enabled)
0628         ret = max77686_rtc_start_alarm(info);
0629 out:
0630     mutex_unlock(&info->lock);
0631     return ret;
0632 }
0633 
0634 static int max77686_rtc_alarm_irq_enable(struct device *dev,
0635                      unsigned int enabled)
0636 {
0637     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0638     int ret;
0639 
0640     mutex_lock(&info->lock);
0641     if (enabled)
0642         ret = max77686_rtc_start_alarm(info);
0643     else
0644         ret = max77686_rtc_stop_alarm(info);
0645     mutex_unlock(&info->lock);
0646 
0647     return ret;
0648 }
0649 
0650 static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
0651 {
0652     struct max77686_rtc_info *info = data;
0653 
0654     dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
0655 
0656     rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
0657 
0658     return IRQ_HANDLED;
0659 }
0660 
0661 static const struct rtc_class_ops max77686_rtc_ops = {
0662     .read_time = max77686_rtc_read_time,
0663     .set_time = max77686_rtc_set_time,
0664     .read_alarm = max77686_rtc_read_alarm,
0665     .set_alarm = max77686_rtc_set_alarm,
0666     .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
0667 };
0668 
0669 static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
0670 {
0671     u8 data[2];
0672     int ret;
0673 
0674     /* Set RTC control register : Binary mode, 24hour mdoe */
0675     data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
0676     data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
0677 
0678     ret = regmap_bulk_write(info->rtc_regmap,
0679                 info->drv_data->map[REG_RTC_CONTROLM],
0680                 data, ARRAY_SIZE(data));
0681     if (ret < 0) {
0682         dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
0683         return ret;
0684     }
0685 
0686     ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
0687     return ret;
0688 }
0689 
0690 static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
0691 {
0692     struct device *parent = info->dev->parent;
0693     struct i2c_client *parent_i2c = to_i2c_client(parent);
0694     int ret;
0695 
0696     if (info->drv_data->rtc_irq_from_platform) {
0697         struct platform_device *pdev = to_platform_device(info->dev);
0698 
0699         info->rtc_irq = platform_get_irq(pdev, 0);
0700         if (info->rtc_irq < 0)
0701             return info->rtc_irq;
0702     } else {
0703         info->rtc_irq =  parent_i2c->irq;
0704     }
0705 
0706     info->regmap = dev_get_regmap(parent, NULL);
0707     if (!info->regmap) {
0708         dev_err(info->dev, "Failed to get rtc regmap\n");
0709         return -ENODEV;
0710     }
0711 
0712     if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
0713         info->rtc_regmap = info->regmap;
0714         goto add_rtc_irq;
0715     }
0716 
0717     info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
0718                           info->drv_data->rtc_i2c_addr);
0719     if (IS_ERR(info->rtc)) {
0720         dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
0721         return PTR_ERR(info->rtc);
0722     }
0723 
0724     info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
0725                         info->drv_data->regmap_config);
0726     if (IS_ERR(info->rtc_regmap)) {
0727         ret = PTR_ERR(info->rtc_regmap);
0728         dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
0729         return ret;
0730     }
0731 
0732 add_rtc_irq:
0733     ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
0734                   IRQF_ONESHOT | IRQF_SHARED,
0735                   0, info->drv_data->rtc_irq_chip,
0736                   &info->rtc_irq_data);
0737     if (ret < 0) {
0738         dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
0739         return ret;
0740     }
0741 
0742     return 0;
0743 }
0744 
0745 static int max77686_rtc_probe(struct platform_device *pdev)
0746 {
0747     struct max77686_rtc_info *info;
0748     const struct platform_device_id *id = platform_get_device_id(pdev);
0749     int ret;
0750 
0751     info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
0752                 GFP_KERNEL);
0753     if (!info)
0754         return -ENOMEM;
0755 
0756     mutex_init(&info->lock);
0757     info->dev = &pdev->dev;
0758     info->drv_data = (const struct max77686_rtc_driver_data *)
0759         id->driver_data;
0760 
0761     ret = max77686_init_rtc_regmap(info);
0762     if (ret < 0)
0763         return ret;
0764 
0765     platform_set_drvdata(pdev, info);
0766 
0767     ret = max77686_rtc_init_reg(info);
0768     if (ret < 0) {
0769         dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
0770         goto err_rtc;
0771     }
0772 
0773     device_init_wakeup(&pdev->dev, 1);
0774 
0775     info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
0776                     &max77686_rtc_ops, THIS_MODULE);
0777 
0778     if (IS_ERR(info->rtc_dev)) {
0779         ret = PTR_ERR(info->rtc_dev);
0780         dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
0781         if (ret == 0)
0782             ret = -EINVAL;
0783         goto err_rtc;
0784     }
0785 
0786     info->virq = regmap_irq_get_virq(info->rtc_irq_data,
0787                      MAX77686_RTCIRQ_RTCA1);
0788     if (info->virq <= 0) {
0789         ret = -ENXIO;
0790         goto err_rtc;
0791     }
0792 
0793     ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
0794                    "rtc-alarm1", info);
0795     if (ret < 0) {
0796         dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
0797             info->virq, ret);
0798         goto err_rtc;
0799     }
0800 
0801     return 0;
0802 
0803 err_rtc:
0804     regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
0805 
0806     return ret;
0807 }
0808 
0809 static int max77686_rtc_remove(struct platform_device *pdev)
0810 {
0811     struct max77686_rtc_info *info = platform_get_drvdata(pdev);
0812 
0813     free_irq(info->virq, info);
0814     regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
0815 
0816     return 0;
0817 }
0818 
0819 #ifdef CONFIG_PM_SLEEP
0820 static int max77686_rtc_suspend(struct device *dev)
0821 {
0822     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0823     int ret = 0;
0824 
0825     if (device_may_wakeup(dev)) {
0826         struct max77686_rtc_info *info = dev_get_drvdata(dev);
0827 
0828         ret = enable_irq_wake(info->virq);
0829     }
0830 
0831     /*
0832      * If the main IRQ (not virtual) is the parent IRQ, then it must be
0833      * disabled during suspend because if it happens while suspended it
0834      * will be handled before resuming I2C.
0835      *
0836      * Since Main IRQ is shared, all its users should disable it to be sure
0837      * it won't fire while one of them is still suspended.
0838      */
0839     if (!info->drv_data->rtc_irq_from_platform)
0840         disable_irq(info->rtc_irq);
0841 
0842     return ret;
0843 }
0844 
0845 static int max77686_rtc_resume(struct device *dev)
0846 {
0847     struct max77686_rtc_info *info = dev_get_drvdata(dev);
0848 
0849     if (!info->drv_data->rtc_irq_from_platform)
0850         enable_irq(info->rtc_irq);
0851 
0852     if (device_may_wakeup(dev)) {
0853         struct max77686_rtc_info *info = dev_get_drvdata(dev);
0854 
0855         return disable_irq_wake(info->virq);
0856     }
0857 
0858     return 0;
0859 }
0860 #endif
0861 
0862 static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
0863              max77686_rtc_suspend, max77686_rtc_resume);
0864 
0865 static const struct platform_device_id rtc_id[] = {
0866     { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
0867     { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
0868     { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
0869     { "max77714-rtc", .driver_data = (kernel_ulong_t)&max77714_drv_data, },
0870     {},
0871 };
0872 MODULE_DEVICE_TABLE(platform, rtc_id);
0873 
0874 static struct platform_driver max77686_rtc_driver = {
0875     .driver     = {
0876         .name   = "max77686-rtc",
0877         .pm = &max77686_rtc_pm_ops,
0878     },
0879     .probe      = max77686_rtc_probe,
0880     .remove     = max77686_rtc_remove,
0881     .id_table   = rtc_id,
0882 };
0883 
0884 module_platform_driver(max77686_rtc_driver);
0885 
0886 MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
0887 MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
0888 MODULE_LICENSE("GPL");
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