drivers/rtc/rtc-lpc32xx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2010 NXP Semiconductors
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/module.h>
0008 #include <linux/init.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/spinlock.h>
0011 #include <linux/rtc.h>
0012 #include <linux/slab.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015
0016 /*
0017  * Clock and Power control register offsets
0018  */
0019 #define LPC32XX_RTC_UCOUNT      0x00
0020 #define LPC32XX_RTC_DCOUNT      0x04
0021 #define LPC32XX_RTC_MATCH0      0x08
0022 #define LPC32XX_RTC_MATCH1      0x0C
0023 #define LPC32XX_RTC_CTRL        0x10
0024 #define LPC32XX_RTC_INTSTAT     0x14
0025 #define LPC32XX_RTC_KEY         0x18
0026 #define LPC32XX_RTC_SRAM        0x80
0027
0028 #define LPC32XX_RTC_CTRL_MATCH0     (1 << 0)
0029 #define LPC32XX_RTC_CTRL_MATCH1     (1 << 1)
0030 #define LPC32XX_RTC_CTRL_ONSW_MATCH0    (1 << 2)
0031 #define LPC32XX_RTC_CTRL_ONSW_MATCH1    (1 << 3)
0032 #define LPC32XX_RTC_CTRL_SW_RESET   (1 << 4)
0033 #define LPC32XX_RTC_CTRL_CNTR_DIS   (1 << 6)
0034 #define LPC32XX_RTC_CTRL_ONSW_FORCE_HI  (1 << 7)
0035
0036 #define LPC32XX_RTC_INTSTAT_MATCH0  (1 << 0)
0037 #define LPC32XX_RTC_INTSTAT_MATCH1  (1 << 1)
0038 #define LPC32XX_RTC_INTSTAT_ONSW    (1 << 2)
0039
0040 #define LPC32XX_RTC_KEY_ONSW_LOADVAL    0xB5C13F27
0041
0042 #define rtc_readl(dev, reg) \
0043     __raw_readl((dev)->rtc_base + (reg))
0044 #define rtc_writel(dev, reg, val) \
0045     __raw_writel((val), (dev)->rtc_base + (reg))
0046
0047 struct lpc32xx_rtc {
0048     void __iomem *rtc_base;
0049     int irq;
0050     unsigned char alarm_enabled;
0051     struct rtc_device *rtc;
0052     spinlock_t lock;
0053 };
0054
0055 static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
0056 {
0057     unsigned long elapsed_sec;
0058     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0059
0060     elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
0061     rtc_time64_to_tm(elapsed_sec, time);
0062
0063     return 0;
0064 }
0065
0066 static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
0067 {
0068     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0069     u32 secs = rtc_tm_to_time64(time);
0070     u32 tmp;
0071
0072     spin_lock_irq(&rtc->lock);
0073
0074     /* RTC must be disabled during count update */
0075     tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
0076     rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
0077     rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
0078     rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
0079     rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
0080
0081     spin_unlock_irq(&rtc->lock);
0082
0083     return 0;
0084 }
0085
0086 static int lpc32xx_rtc_read_alarm(struct device *dev,
0087     struct rtc_wkalrm *wkalrm)
0088 {
0089     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0090
0091     rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
0092     wkalrm->enabled = rtc->alarm_enabled;
0093     wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
0094         LPC32XX_RTC_INTSTAT_MATCH0);
0095
0096     return rtc_valid_tm(&wkalrm->time);
0097 }
0098
0099 static int lpc32xx_rtc_set_alarm(struct device *dev,
0100     struct rtc_wkalrm *wkalrm)
0101 {
0102     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0103     unsigned long alarmsecs;
0104     u32 tmp;
0105
0106     alarmsecs = rtc_tm_to_time64(&wkalrm->time);
0107
0108     spin_lock_irq(&rtc->lock);
0109
0110     /* Disable alarm during update */
0111     tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
0112     rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
0113
0114     rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
0115
0116     rtc->alarm_enabled = wkalrm->enabled;
0117     if (wkalrm->enabled) {
0118         rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
0119                LPC32XX_RTC_INTSTAT_MATCH0);
0120         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
0121                LPC32XX_RTC_CTRL_MATCH0);
0122     }
0123
0124     spin_unlock_irq(&rtc->lock);
0125
0126     return 0;
0127 }
0128
0129 static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
0130     unsigned int enabled)
0131 {
0132     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0133     u32 tmp;
0134
0135     spin_lock_irq(&rtc->lock);
0136     tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
0137
0138     if (enabled) {
0139         rtc->alarm_enabled = 1;
0140         tmp |= LPC32XX_RTC_CTRL_MATCH0;
0141     } else {
0142         rtc->alarm_enabled = 0;
0143         tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
0144     }
0145
0146     rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
0147     spin_unlock_irq(&rtc->lock);
0148
0149     return 0;
0150 }
0151
0152 static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
0153 {
0154     struct lpc32xx_rtc *rtc = dev;
0155
0156     spin_lock(&rtc->lock);
0157
0158     /* Disable alarm interrupt */
0159     rtc_writel(rtc, LPC32XX_RTC_CTRL,
0160         rtc_readl(rtc, LPC32XX_RTC_CTRL) &
0161               ~LPC32XX_RTC_CTRL_MATCH0);
0162     rtc->alarm_enabled = 0;
0163
0164     /*
0165      * Write a large value to the match value so the RTC won't
0166      * keep firing the match status
0167      */
0168     rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
0169     rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
0170
0171     spin_unlock(&rtc->lock);
0172
0173     rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
0174
0175     return IRQ_HANDLED;
0176 }
0177
0178 static const struct rtc_class_ops lpc32xx_rtc_ops = {
0179     .read_time      = lpc32xx_rtc_read_time,
0180     .set_time       = lpc32xx_rtc_set_time,
0181     .read_alarm     = lpc32xx_rtc_read_alarm,
0182     .set_alarm      = lpc32xx_rtc_set_alarm,
0183     .alarm_irq_enable   = lpc32xx_rtc_alarm_irq_enable,
0184 };
0185
0186 static int lpc32xx_rtc_probe(struct platform_device *pdev)
0187 {
0188     struct lpc32xx_rtc *rtc;
0189     int err;
0190     u32 tmp;
0191
0192     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
0193     if (unlikely(!rtc))
0194         return -ENOMEM;
0195
0196     rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
0197     if (IS_ERR(rtc->rtc_base))
0198         return PTR_ERR(rtc->rtc_base);
0199
0200     spin_lock_init(&rtc->lock);
0201
0202     /*
0203      * The RTC is on a separate power domain and can keep it's state
0204      * across a chip power cycle. If the RTC has never been previously
0205      * setup, then set it up now for the first time.
0206      */
0207     tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
0208     if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
0209         tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
0210             LPC32XX_RTC_CTRL_CNTR_DIS |
0211             LPC32XX_RTC_CTRL_MATCH0 |
0212             LPC32XX_RTC_CTRL_MATCH1 |
0213             LPC32XX_RTC_CTRL_ONSW_MATCH0 |
0214             LPC32XX_RTC_CTRL_ONSW_MATCH1 |
0215             LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
0216         rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
0217
0218         /* Clear latched interrupt states */
0219         rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
0220         rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
0221                LPC32XX_RTC_INTSTAT_MATCH0 |
0222                LPC32XX_RTC_INTSTAT_MATCH1 |
0223                LPC32XX_RTC_INTSTAT_ONSW);
0224
0225         /* Write key value to RTC so it won't reload on reset */
0226         rtc_writel(rtc, LPC32XX_RTC_KEY,
0227                LPC32XX_RTC_KEY_ONSW_LOADVAL);
0228     } else {
0229         rtc_writel(rtc, LPC32XX_RTC_CTRL,
0230                tmp & ~LPC32XX_RTC_CTRL_MATCH0);
0231     }
0232
0233     platform_set_drvdata(pdev, rtc);
0234
0235     rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
0236     if (IS_ERR(rtc->rtc))
0237         return PTR_ERR(rtc->rtc);
0238
0239     rtc->rtc->ops = &lpc32xx_rtc_ops;
0240     rtc->rtc->range_max = U32_MAX;
0241
0242     err = devm_rtc_register_device(rtc->rtc);
0243     if (err)
0244         return err;
0245
0246     /*
0247      * IRQ is enabled after device registration in case alarm IRQ
0248      * is pending upon suspend exit.
0249      */
0250     rtc->irq = platform_get_irq(pdev, 0);
0251     if (rtc->irq < 0) {
0252         dev_warn(&pdev->dev, "Can't get interrupt resource\n");
0253     } else {
0254         if (devm_request_irq(&pdev->dev, rtc->irq,
0255                      lpc32xx_rtc_alarm_interrupt,
0256                      0, pdev->name, rtc) < 0) {
0257             dev_warn(&pdev->dev, "Can't request interrupt.\n");
0258             rtc->irq = -1;
0259         } else {
0260             device_init_wakeup(&pdev->dev, 1);
0261         }
0262     }
0263
0264     return 0;
0265 }
0266
0267 #ifdef CONFIG_PM
0268 static int lpc32xx_rtc_suspend(struct device *dev)
0269 {
0270     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0271
0272     if (rtc->irq >= 0) {
0273         if (device_may_wakeup(dev))
0274             enable_irq_wake(rtc->irq);
0275         else
0276             disable_irq_wake(rtc->irq);
0277     }
0278
0279     return 0;
0280 }
0281
0282 static int lpc32xx_rtc_resume(struct device *dev)
0283 {
0284     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0285
0286     if (rtc->irq >= 0 && device_may_wakeup(dev))
0287         disable_irq_wake(rtc->irq);
0288
0289     return 0;
0290 }
0291
0292 /* Unconditionally disable the alarm */
0293 static int lpc32xx_rtc_freeze(struct device *dev)
0294 {
0295     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0296
0297     spin_lock_irq(&rtc->lock);
0298
0299     rtc_writel(rtc, LPC32XX_RTC_CTRL,
0300         rtc_readl(rtc, LPC32XX_RTC_CTRL) &
0301               ~LPC32XX_RTC_CTRL_MATCH0);
0302
0303     spin_unlock_irq(&rtc->lock);
0304
0305     return 0;
0306 }
0307
0308 static int lpc32xx_rtc_thaw(struct device *dev)
0309 {
0310     struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
0311
0312     if (rtc->alarm_enabled) {
0313         spin_lock_irq(&rtc->lock);
0314
0315         rtc_writel(rtc, LPC32XX_RTC_CTRL,
0316                rtc_readl(rtc, LPC32XX_RTC_CTRL) |
0317                LPC32XX_RTC_CTRL_MATCH0);
0318
0319         spin_unlock_irq(&rtc->lock);
0320     }
0321
0322     return 0;
0323 }
0324
0325 static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
0326     .suspend = lpc32xx_rtc_suspend,
0327     .resume = lpc32xx_rtc_resume,
0328     .freeze = lpc32xx_rtc_freeze,
0329     .thaw = lpc32xx_rtc_thaw,
0330     .restore = lpc32xx_rtc_resume
0331 };
0332
0333 #define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
0334 #else
0335 #define LPC32XX_RTC_PM_OPS NULL
0336 #endif
0337
0338 #ifdef CONFIG_OF
0339 static const struct of_device_id lpc32xx_rtc_match[] = {
0340     { .compatible = "nxp,lpc3220-rtc" },
0341     { }
0342 };
0343 MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
0344 #endif
0345
0346 static struct platform_driver lpc32xx_rtc_driver = {
0347     .probe      = lpc32xx_rtc_probe,
0348     .driver = {
0349         .name   = "rtc-lpc32xx",
0350         .pm = LPC32XX_RTC_PM_OPS,
0351         .of_match_table = of_match_ptr(lpc32xx_rtc_match),
0352     },
0353 };
0354
0355 module_platform_driver(lpc32xx_rtc_driver);
0356
0357 MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
0358 MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
0359 MODULE_LICENSE("GPL");
0360 MODULE_ALIAS("platform:rtc-lpc32xx");