drivers/rtc/rtc-jz4740.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
0004  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
0005  *   JZ4740 SoC RTC driver
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_wakeirq.h>
0015 #include <linux/reboot.h>
0016 #include <linux/rtc.h>
0017 #include <linux/slab.h>
0018 #include <linux/spinlock.h>
0019
0020 #define JZ_REG_RTC_CTRL     0x00
0021 #define JZ_REG_RTC_SEC      0x04
0022 #define JZ_REG_RTC_SEC_ALARM    0x08
0023 #define JZ_REG_RTC_REGULATOR    0x0C
0024 #define JZ_REG_RTC_HIBERNATE    0x20
0025 #define JZ_REG_RTC_WAKEUP_FILTER    0x24
0026 #define JZ_REG_RTC_RESET_COUNTER    0x28
0027 #define JZ_REG_RTC_SCRATCHPAD   0x34
0028
0029 /* The following are present on the jz4780 */
0030 #define JZ_REG_RTC_WENR 0x3C
0031 #define JZ_RTC_WENR_WEN BIT(31)
0032
0033 #define JZ_RTC_CTRL_WRDY    BIT(7)
0034 #define JZ_RTC_CTRL_1HZ     BIT(6)
0035 #define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
0036 #define JZ_RTC_CTRL_AF      BIT(4)
0037 #define JZ_RTC_CTRL_AF_IRQ  BIT(3)
0038 #define JZ_RTC_CTRL_AE      BIT(2)
0039 #define JZ_RTC_CTRL_ENABLE  BIT(0)
0040
0041 /* Magic value to enable writes on jz4780 */
0042 #define JZ_RTC_WENR_MAGIC   0xA55A
0043
0044 #define JZ_RTC_WAKEUP_FILTER_MASK   0x0000FFE0
0045 #define JZ_RTC_RESET_COUNTER_MASK   0x00000FE0
0046
0047 enum jz4740_rtc_type {
0048     ID_JZ4740,
0049     ID_JZ4760,
0050     ID_JZ4780,
0051 };
0052
0053 struct jz4740_rtc {
0054     void __iomem *base;
0055     enum jz4740_rtc_type type;
0056
0057     struct rtc_device *rtc;
0058
0059     spinlock_t lock;
0060 };
0061
0062 static struct device *dev_for_power_off;
0063
0064 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
0065 {
0066     return readl(rtc->base + reg);
0067 }
0068
0069 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
0070 {
0071     uint32_t ctrl;
0072     int timeout = 10000;
0073
0074     do {
0075         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
0076     } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
0077
0078     return timeout ? 0 : -EIO;
0079 }
0080
0081 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
0082 {
0083     uint32_t ctrl;
0084     int ret, timeout = 10000;
0085
0086     ret = jz4740_rtc_wait_write_ready(rtc);
0087     if (ret != 0)
0088         return ret;
0089
0090     writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
0091
0092     do {
0093         ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
0094     } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
0095
0096     return timeout ? 0 : -EIO;
0097 }
0098
0099 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
0100     uint32_t val)
0101 {
0102     int ret = 0;
0103
0104     if (rtc->type >= ID_JZ4760)
0105         ret = jz4780_rtc_enable_write(rtc);
0106     if (ret == 0)
0107         ret = jz4740_rtc_wait_write_ready(rtc);
0108     if (ret == 0)
0109         writel(val, rtc->base + reg);
0110
0111     return ret;
0112 }
0113
0114 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
0115     bool set)
0116 {
0117     int ret;
0118     unsigned long flags;
0119     uint32_t ctrl;
0120
0121     spin_lock_irqsave(&rtc->lock, flags);
0122
0123     ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
0124
0125     /* Don't clear interrupt flags by accident */
0126     ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
0127
0128     if (set)
0129         ctrl |= mask;
0130     else
0131         ctrl &= ~mask;
0132
0133     ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
0134
0135     spin_unlock_irqrestore(&rtc->lock, flags);
0136
0137     return ret;
0138 }
0139
0140 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
0141 {
0142     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0143     uint32_t secs, secs2;
0144     int timeout = 5;
0145
0146     if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
0147         return -EINVAL;
0148
0149     /* If the seconds register is read while it is updated, it can contain a
0150      * bogus value. This can be avoided by making sure that two consecutive
0151      * reads have the same value.
0152      */
0153     secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
0154     secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
0155
0156     while (secs != secs2 && --timeout) {
0157         secs = secs2;
0158         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
0159     }
0160
0161     if (timeout == 0)
0162         return -EIO;
0163
0164     rtc_time64_to_tm(secs, time);
0165
0166     return 0;
0167 }
0168
0169 static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
0170 {
0171     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0172     int ret;
0173
0174     ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
0175     if (ret)
0176         return ret;
0177
0178     return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
0179 }
0180
0181 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0182 {
0183     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0184     uint32_t secs;
0185     uint32_t ctrl;
0186
0187     secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
0188
0189     ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
0190
0191     alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
0192     alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
0193
0194     rtc_time64_to_tm(secs, &alrm->time);
0195
0196     return 0;
0197 }
0198
0199 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0200 {
0201     int ret;
0202     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0203     uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
0204
0205     ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
0206     if (!ret)
0207         ret = jz4740_rtc_ctrl_set_bits(rtc,
0208             JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
0209
0210     return ret;
0211 }
0212
0213 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
0214 {
0215     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0216     return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
0217 }
0218
0219 static const struct rtc_class_ops jz4740_rtc_ops = {
0220     .read_time  = jz4740_rtc_read_time,
0221     .set_time   = jz4740_rtc_set_time,
0222     .read_alarm = jz4740_rtc_read_alarm,
0223     .set_alarm  = jz4740_rtc_set_alarm,
0224     .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
0225 };
0226
0227 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
0228 {
0229     struct jz4740_rtc *rtc = data;
0230     uint32_t ctrl;
0231     unsigned long events = 0;
0232
0233     ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
0234
0235     if (ctrl & JZ_RTC_CTRL_1HZ)
0236         events |= (RTC_UF | RTC_IRQF);
0237
0238     if (ctrl & JZ_RTC_CTRL_AF)
0239         events |= (RTC_AF | RTC_IRQF);
0240
0241     rtc_update_irq(rtc->rtc, 1, events);
0242
0243     jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
0244
0245     return IRQ_HANDLED;
0246 }
0247
0248 static void jz4740_rtc_poweroff(struct device *dev)
0249 {
0250     struct jz4740_rtc *rtc = dev_get_drvdata(dev);
0251     jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
0252 }
0253
0254 static void jz4740_rtc_power_off(void)
0255 {
0256     jz4740_rtc_poweroff(dev_for_power_off);
0257     kernel_halt();
0258 }
0259
0260 static void jz4740_rtc_clk_disable(void *data)
0261 {
0262     clk_disable_unprepare(data);
0263 }
0264
0265 static const struct of_device_id jz4740_rtc_of_match[] = {
0266     { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
0267     { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
0268     { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
0269     {},
0270 };
0271 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
0272
0273 static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
0274                      struct device_node *np,
0275                      unsigned long rate)
0276 {
0277     unsigned long wakeup_ticks, reset_ticks;
0278     unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
0279     unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
0280
0281     of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
0282                  &reset_pin_assert_time);
0283     of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
0284                  &min_wakeup_pin_assert_time);
0285
0286     /*
0287      * Set minimum wakeup pin assertion time: 100 ms.
0288      * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
0289      */
0290     wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
0291     if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
0292         wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
0293     else
0294         wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
0295     jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
0296
0297     /*
0298      * Set reset pin low-level assertion time after wakeup: 60 ms.
0299      * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
0300      */
0301     reset_ticks = (reset_pin_assert_time * rate) / 1000;
0302     if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
0303         reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
0304     else
0305         reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
0306     jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
0307 }
0308
0309 static int jz4740_rtc_probe(struct platform_device *pdev)
0310 {
0311     struct device *dev = &pdev->dev;
0312     struct device_node *np = dev->of_node;
0313     struct jz4740_rtc *rtc;
0314     unsigned long rate;
0315     struct clk *clk;
0316     int ret, irq;
0317
0318     rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
0319     if (!rtc)
0320         return -ENOMEM;
0321
0322     rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
0323
0324     irq = platform_get_irq(pdev, 0);
0325     if (irq < 0)
0326         return irq;
0327
0328     rtc->base = devm_platform_ioremap_resource(pdev, 0);
0329     if (IS_ERR(rtc->base))
0330         return PTR_ERR(rtc->base);
0331
0332     clk = devm_clk_get(dev, "rtc");
0333     if (IS_ERR(clk)) {
0334         dev_err(dev, "Failed to get RTC clock\n");
0335         return PTR_ERR(clk);
0336     }
0337
0338     ret = clk_prepare_enable(clk);
0339     if (ret) {
0340         dev_err(dev, "Failed to enable clock\n");
0341         return ret;
0342     }
0343
0344     ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
0345     if (ret) {
0346         dev_err(dev, "Failed to register devm action\n");
0347         return ret;
0348     }
0349
0350     spin_lock_init(&rtc->lock);
0351
0352     platform_set_drvdata(pdev, rtc);
0353
0354     device_init_wakeup(dev, 1);
0355
0356     ret = dev_pm_set_wake_irq(dev, irq);
0357     if (ret) {
0358         dev_err(dev, "Failed to set wake irq: %d\n", ret);
0359         return ret;
0360     }
0361
0362     rtc->rtc = devm_rtc_allocate_device(dev);
0363     if (IS_ERR(rtc->rtc)) {
0364         ret = PTR_ERR(rtc->rtc);
0365         dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
0366         return ret;
0367     }
0368
0369     rtc->rtc->ops = &jz4740_rtc_ops;
0370     rtc->rtc->range_max = U32_MAX;
0371
0372     rate = clk_get_rate(clk);
0373     jz4740_rtc_set_wakeup_params(rtc, np, rate);
0374
0375     /* Each 1 Hz pulse should happen after (rate) ticks */
0376     jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
0377
0378     ret = devm_rtc_register_device(rtc->rtc);
0379     if (ret)
0380         return ret;
0381
0382     ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
0383                    pdev->name, rtc);
0384     if (ret) {
0385         dev_err(dev, "Failed to request rtc irq: %d\n", ret);
0386         return ret;
0387     }
0388
0389     if (of_device_is_system_power_controller(np)) {
0390         dev_for_power_off = dev;
0391
0392         if (!pm_power_off)
0393             pm_power_off = jz4740_rtc_power_off;
0394         else
0395             dev_warn(dev, "Poweroff handler already present!\n");
0396     }
0397
0398     return 0;
0399 }
0400
0401 static struct platform_driver jz4740_rtc_driver = {
0402     .probe   = jz4740_rtc_probe,
0403     .driver  = {
0404         .name  = "jz4740-rtc",
0405         .of_match_table = jz4740_rtc_of_match,
0406     },
0407 };
0408
0409 module_platform_driver(jz4740_rtc_driver);
0410
0411 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
0412 MODULE_LICENSE("GPL");
0413 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
0414 MODULE_ALIAS("platform:jz4740-rtc");