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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Haoyu HYM8563 RTC driver
0004  *
0005  * Copyright (C) 2013 MundoReader S.L.
0006  * Author: Heiko Stuebner <heiko@sntech.de>
0007  *
0008  * based on rtc-HYM8563
0009  * Copyright (C) 2010 ROCKCHIP, Inc.
0010  */
0011 
0012 #include <linux/module.h>
0013 #include <linux/clk-provider.h>
0014 #include <linux/i2c.h>
0015 #include <linux/bcd.h>
0016 #include <linux/rtc.h>
0017 
0018 #define HYM8563_CTL1        0x00
0019 #define HYM8563_CTL1_TEST   BIT(7)
0020 #define HYM8563_CTL1_STOP   BIT(5)
0021 #define HYM8563_CTL1_TESTC  BIT(3)
0022 
0023 #define HYM8563_CTL2        0x01
0024 #define HYM8563_CTL2_TI_TP  BIT(4)
0025 #define HYM8563_CTL2_AF     BIT(3)
0026 #define HYM8563_CTL2_TF     BIT(2)
0027 #define HYM8563_CTL2_AIE    BIT(1)
0028 #define HYM8563_CTL2_TIE    BIT(0)
0029 
0030 #define HYM8563_SEC     0x02
0031 #define HYM8563_SEC_VL      BIT(7)
0032 #define HYM8563_SEC_MASK    0x7f
0033 
0034 #define HYM8563_MIN     0x03
0035 #define HYM8563_MIN_MASK    0x7f
0036 
0037 #define HYM8563_HOUR        0x04
0038 #define HYM8563_HOUR_MASK   0x3f
0039 
0040 #define HYM8563_DAY     0x05
0041 #define HYM8563_DAY_MASK    0x3f
0042 
0043 #define HYM8563_WEEKDAY     0x06
0044 #define HYM8563_WEEKDAY_MASK    0x07
0045 
0046 #define HYM8563_MONTH       0x07
0047 #define HYM8563_MONTH_CENTURY   BIT(7)
0048 #define HYM8563_MONTH_MASK  0x1f
0049 
0050 #define HYM8563_YEAR        0x08
0051 
0052 #define HYM8563_ALM_MIN     0x09
0053 #define HYM8563_ALM_HOUR    0x0a
0054 #define HYM8563_ALM_DAY     0x0b
0055 #define HYM8563_ALM_WEEK    0x0c
0056 
0057 /* Each alarm check can be disabled by setting this bit in the register */
0058 #define HYM8563_ALM_BIT_DISABLE BIT(7)
0059 
0060 #define HYM8563_CLKOUT      0x0d
0061 #define HYM8563_CLKOUT_ENABLE   BIT(7)
0062 #define HYM8563_CLKOUT_32768    0
0063 #define HYM8563_CLKOUT_1024 1
0064 #define HYM8563_CLKOUT_32   2
0065 #define HYM8563_CLKOUT_1    3
0066 #define HYM8563_CLKOUT_MASK 3
0067 
0068 #define HYM8563_TMR_CTL     0x0e
0069 #define HYM8563_TMR_CTL_ENABLE  BIT(7)
0070 #define HYM8563_TMR_CTL_4096    0
0071 #define HYM8563_TMR_CTL_64  1
0072 #define HYM8563_TMR_CTL_1   2
0073 #define HYM8563_TMR_CTL_1_60    3
0074 #define HYM8563_TMR_CTL_MASK    3
0075 
0076 #define HYM8563_TMR_CNT     0x0f
0077 
0078 struct hym8563 {
0079     struct i2c_client   *client;
0080     struct rtc_device   *rtc;
0081 #ifdef CONFIG_COMMON_CLK
0082     struct clk_hw       clkout_hw;
0083 #endif
0084 };
0085 
0086 /*
0087  * RTC handling
0088  */
0089 
0090 static int hym8563_rtc_read_time(struct device *dev, struct rtc_time *tm)
0091 {
0092     struct i2c_client *client = to_i2c_client(dev);
0093     u8 buf[7];
0094     int ret;
0095 
0096     ret = i2c_smbus_read_i2c_block_data(client, HYM8563_SEC, 7, buf);
0097     if (ret < 0)
0098         return ret;
0099 
0100     if (buf[0] & HYM8563_SEC_VL) {
0101         dev_warn(&client->dev,
0102              "no valid clock/calendar values available\n");
0103         return -EINVAL;
0104     }
0105 
0106     tm->tm_sec = bcd2bin(buf[0] & HYM8563_SEC_MASK);
0107     tm->tm_min = bcd2bin(buf[1] & HYM8563_MIN_MASK);
0108     tm->tm_hour = bcd2bin(buf[2] & HYM8563_HOUR_MASK);
0109     tm->tm_mday = bcd2bin(buf[3] & HYM8563_DAY_MASK);
0110     tm->tm_wday = bcd2bin(buf[4] & HYM8563_WEEKDAY_MASK); /* 0 = Sun */
0111     tm->tm_mon = bcd2bin(buf[5] & HYM8563_MONTH_MASK) - 1; /* 0 = Jan */
0112     tm->tm_year = bcd2bin(buf[6]) + 100;
0113 
0114     return 0;
0115 }
0116 
0117 static int hym8563_rtc_set_time(struct device *dev, struct rtc_time *tm)
0118 {
0119     struct i2c_client *client = to_i2c_client(dev);
0120     u8 buf[7];
0121     int ret;
0122 
0123     /* Years >= 2100 are to far in the future, 19XX is to early */
0124     if (tm->tm_year < 100 || tm->tm_year >= 200)
0125         return -EINVAL;
0126 
0127     buf[0] = bin2bcd(tm->tm_sec);
0128     buf[1] = bin2bcd(tm->tm_min);
0129     buf[2] = bin2bcd(tm->tm_hour);
0130     buf[3] = bin2bcd(tm->tm_mday);
0131     buf[4] = bin2bcd(tm->tm_wday);
0132     buf[5] = bin2bcd(tm->tm_mon + 1);
0133 
0134     /*
0135      * While the HYM8563 has a century flag in the month register,
0136      * it does not seem to carry it over a subsequent write/read.
0137      * So we'll limit ourself to 100 years, starting at 2000 for now.
0138      */
0139     buf[6] = bin2bcd(tm->tm_year - 100);
0140 
0141     /*
0142      * CTL1 only contains TEST-mode bits apart from stop,
0143      * so no need to read the value first
0144      */
0145     ret = i2c_smbus_write_byte_data(client, HYM8563_CTL1,
0146                         HYM8563_CTL1_STOP);
0147     if (ret < 0)
0148         return ret;
0149 
0150     ret = i2c_smbus_write_i2c_block_data(client, HYM8563_SEC, 7, buf);
0151     if (ret < 0)
0152         return ret;
0153 
0154     ret = i2c_smbus_write_byte_data(client, HYM8563_CTL1, 0);
0155     if (ret < 0)
0156         return ret;
0157 
0158     return 0;
0159 }
0160 
0161 static int hym8563_rtc_alarm_irq_enable(struct device *dev,
0162                     unsigned int enabled)
0163 {
0164     struct i2c_client *client = to_i2c_client(dev);
0165     int data;
0166 
0167     data = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
0168     if (data < 0)
0169         return data;
0170 
0171     if (enabled)
0172         data |= HYM8563_CTL2_AIE;
0173     else
0174         data &= ~HYM8563_CTL2_AIE;
0175 
0176     return i2c_smbus_write_byte_data(client, HYM8563_CTL2, data);
0177 };
0178 
0179 static int hym8563_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
0180 {
0181     struct i2c_client *client = to_i2c_client(dev);
0182     struct rtc_time *alm_tm = &alm->time;
0183     u8 buf[4];
0184     int ret;
0185 
0186     ret = i2c_smbus_read_i2c_block_data(client, HYM8563_ALM_MIN, 4, buf);
0187     if (ret < 0)
0188         return ret;
0189 
0190     /* The alarm only has a minute accuracy */
0191     alm_tm->tm_sec = 0;
0192 
0193     alm_tm->tm_min = (buf[0] & HYM8563_ALM_BIT_DISABLE) ?
0194                     -1 :
0195                     bcd2bin(buf[0] & HYM8563_MIN_MASK);
0196     alm_tm->tm_hour = (buf[1] & HYM8563_ALM_BIT_DISABLE) ?
0197                     -1 :
0198                     bcd2bin(buf[1] & HYM8563_HOUR_MASK);
0199     alm_tm->tm_mday = (buf[2] & HYM8563_ALM_BIT_DISABLE) ?
0200                     -1 :
0201                     bcd2bin(buf[2] & HYM8563_DAY_MASK);
0202     alm_tm->tm_wday = (buf[3] & HYM8563_ALM_BIT_DISABLE) ?
0203                     -1 :
0204                     bcd2bin(buf[3] & HYM8563_WEEKDAY_MASK);
0205 
0206     ret = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
0207     if (ret < 0)
0208         return ret;
0209 
0210     if (ret & HYM8563_CTL2_AIE)
0211         alm->enabled = 1;
0212 
0213     return 0;
0214 }
0215 
0216 static int hym8563_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
0217 {
0218     struct i2c_client *client = to_i2c_client(dev);
0219     struct rtc_time *alm_tm = &alm->time;
0220     u8 buf[4];
0221     int ret;
0222 
0223     ret = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
0224     if (ret < 0)
0225         return ret;
0226 
0227     ret &= ~HYM8563_CTL2_AIE;
0228 
0229     ret = i2c_smbus_write_byte_data(client, HYM8563_CTL2, ret);
0230     if (ret < 0)
0231         return ret;
0232 
0233     buf[0] = (alm_tm->tm_min < 60 && alm_tm->tm_min >= 0) ?
0234             bin2bcd(alm_tm->tm_min) : HYM8563_ALM_BIT_DISABLE;
0235 
0236     buf[1] = (alm_tm->tm_hour < 24 && alm_tm->tm_hour >= 0) ?
0237             bin2bcd(alm_tm->tm_hour) : HYM8563_ALM_BIT_DISABLE;
0238 
0239     buf[2] = (alm_tm->tm_mday <= 31 && alm_tm->tm_mday >= 1) ?
0240             bin2bcd(alm_tm->tm_mday) : HYM8563_ALM_BIT_DISABLE;
0241 
0242     buf[3] = (alm_tm->tm_wday < 7 && alm_tm->tm_wday >= 0) ?
0243             bin2bcd(alm_tm->tm_wday) : HYM8563_ALM_BIT_DISABLE;
0244 
0245     ret = i2c_smbus_write_i2c_block_data(client, HYM8563_ALM_MIN, 4, buf);
0246     if (ret < 0)
0247         return ret;
0248 
0249     return hym8563_rtc_alarm_irq_enable(dev, alm->enabled);
0250 }
0251 
0252 static const struct rtc_class_ops hym8563_rtc_ops = {
0253     .read_time      = hym8563_rtc_read_time,
0254     .set_time       = hym8563_rtc_set_time,
0255     .alarm_irq_enable   = hym8563_rtc_alarm_irq_enable,
0256     .read_alarm     = hym8563_rtc_read_alarm,
0257     .set_alarm      = hym8563_rtc_set_alarm,
0258 };
0259 
0260 /*
0261  * Handling of the clkout
0262  */
0263 
0264 #ifdef CONFIG_COMMON_CLK
0265 #define clkout_hw_to_hym8563(_hw) container_of(_hw, struct hym8563, clkout_hw)
0266 
0267 static int clkout_rates[] = {
0268     32768,
0269     1024,
0270     32,
0271     1,
0272 };
0273 
0274 static unsigned long hym8563_clkout_recalc_rate(struct clk_hw *hw,
0275                         unsigned long parent_rate)
0276 {
0277     struct hym8563 *hym8563 = clkout_hw_to_hym8563(hw);
0278     struct i2c_client *client = hym8563->client;
0279     int ret = i2c_smbus_read_byte_data(client, HYM8563_CLKOUT);
0280 
0281     if (ret < 0)
0282         return 0;
0283 
0284     ret &= HYM8563_CLKOUT_MASK;
0285     return clkout_rates[ret];
0286 }
0287 
0288 static long hym8563_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
0289                       unsigned long *prate)
0290 {
0291     int i;
0292 
0293     for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
0294         if (clkout_rates[i] <= rate)
0295             return clkout_rates[i];
0296 
0297     return 0;
0298 }
0299 
0300 static int hym8563_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
0301                    unsigned long parent_rate)
0302 {
0303     struct hym8563 *hym8563 = clkout_hw_to_hym8563(hw);
0304     struct i2c_client *client = hym8563->client;
0305     int ret = i2c_smbus_read_byte_data(client, HYM8563_CLKOUT);
0306     int i;
0307 
0308     if (ret < 0)
0309         return ret;
0310 
0311     for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
0312         if (clkout_rates[i] == rate) {
0313             ret &= ~HYM8563_CLKOUT_MASK;
0314             ret |= i;
0315             return i2c_smbus_write_byte_data(client,
0316                              HYM8563_CLKOUT, ret);
0317         }
0318 
0319     return -EINVAL;
0320 }
0321 
0322 static int hym8563_clkout_control(struct clk_hw *hw, bool enable)
0323 {
0324     struct hym8563 *hym8563 = clkout_hw_to_hym8563(hw);
0325     struct i2c_client *client = hym8563->client;
0326     int ret = i2c_smbus_read_byte_data(client, HYM8563_CLKOUT);
0327 
0328     if (ret < 0)
0329         return ret;
0330 
0331     if (enable)
0332         ret |= HYM8563_CLKOUT_ENABLE;
0333     else
0334         ret &= ~HYM8563_CLKOUT_ENABLE;
0335 
0336     return i2c_smbus_write_byte_data(client, HYM8563_CLKOUT, ret);
0337 }
0338 
0339 static int hym8563_clkout_prepare(struct clk_hw *hw)
0340 {
0341     return hym8563_clkout_control(hw, 1);
0342 }
0343 
0344 static void hym8563_clkout_unprepare(struct clk_hw *hw)
0345 {
0346     hym8563_clkout_control(hw, 0);
0347 }
0348 
0349 static int hym8563_clkout_is_prepared(struct clk_hw *hw)
0350 {
0351     struct hym8563 *hym8563 = clkout_hw_to_hym8563(hw);
0352     struct i2c_client *client = hym8563->client;
0353     int ret = i2c_smbus_read_byte_data(client, HYM8563_CLKOUT);
0354 
0355     if (ret < 0)
0356         return ret;
0357 
0358     return !!(ret & HYM8563_CLKOUT_ENABLE);
0359 }
0360 
0361 static const struct clk_ops hym8563_clkout_ops = {
0362     .prepare = hym8563_clkout_prepare,
0363     .unprepare = hym8563_clkout_unprepare,
0364     .is_prepared = hym8563_clkout_is_prepared,
0365     .recalc_rate = hym8563_clkout_recalc_rate,
0366     .round_rate = hym8563_clkout_round_rate,
0367     .set_rate = hym8563_clkout_set_rate,
0368 };
0369 
0370 static struct clk *hym8563_clkout_register_clk(struct hym8563 *hym8563)
0371 {
0372     struct i2c_client *client = hym8563->client;
0373     struct device_node *node = client->dev.of_node;
0374     struct clk *clk;
0375     struct clk_init_data init;
0376     int ret;
0377 
0378     ret = i2c_smbus_write_byte_data(client, HYM8563_CLKOUT,
0379                         0);
0380     if (ret < 0)
0381         return ERR_PTR(ret);
0382 
0383     init.name = "hym8563-clkout";
0384     init.ops = &hym8563_clkout_ops;
0385     init.flags = 0;
0386     init.parent_names = NULL;
0387     init.num_parents = 0;
0388     hym8563->clkout_hw.init = &init;
0389 
0390     /* optional override of the clockname */
0391     of_property_read_string(node, "clock-output-names", &init.name);
0392 
0393     /* register the clock */
0394     clk = clk_register(&client->dev, &hym8563->clkout_hw);
0395 
0396     if (!IS_ERR(clk))
0397         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0398 
0399     return clk;
0400 }
0401 #endif
0402 
0403 /*
0404  * The alarm interrupt is implemented as a level-low interrupt in the
0405  * hym8563, while the timer interrupt uses a falling edge.
0406  * We don't use the timer at all, so the interrupt is requested to
0407  * use the level-low trigger.
0408  */
0409 static irqreturn_t hym8563_irq(int irq, void *dev_id)
0410 {
0411     struct hym8563 *hym8563 = (struct hym8563 *)dev_id;
0412     struct i2c_client *client = hym8563->client;
0413     int data, ret;
0414 
0415     rtc_lock(hym8563->rtc);
0416 
0417     /* Clear the alarm flag */
0418 
0419     data = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
0420     if (data < 0) {
0421         dev_err(&client->dev, "%s: error reading i2c data %d\n",
0422             __func__, data);
0423         goto out;
0424     }
0425 
0426     data &= ~HYM8563_CTL2_AF;
0427 
0428     ret = i2c_smbus_write_byte_data(client, HYM8563_CTL2, data);
0429     if (ret < 0) {
0430         dev_err(&client->dev, "%s: error writing i2c data %d\n",
0431             __func__, ret);
0432     }
0433 
0434 out:
0435     rtc_unlock(hym8563->rtc);
0436     return IRQ_HANDLED;
0437 }
0438 
0439 static int hym8563_init_device(struct i2c_client *client)
0440 {
0441     int ret;
0442 
0443     /* Clear stop flag if present */
0444     ret = i2c_smbus_write_byte_data(client, HYM8563_CTL1, 0);
0445     if (ret < 0)
0446         return ret;
0447 
0448     ret = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
0449     if (ret < 0)
0450         return ret;
0451 
0452     /* Disable alarm and timer interrupts */
0453     ret &= ~HYM8563_CTL2_AIE;
0454     ret &= ~HYM8563_CTL2_TIE;
0455 
0456     /* Clear any pending alarm and timer flags */
0457     if (ret & HYM8563_CTL2_AF)
0458         ret &= ~HYM8563_CTL2_AF;
0459 
0460     if (ret & HYM8563_CTL2_TF)
0461         ret &= ~HYM8563_CTL2_TF;
0462 
0463     ret &= ~HYM8563_CTL2_TI_TP;
0464 
0465     return i2c_smbus_write_byte_data(client, HYM8563_CTL2, ret);
0466 }
0467 
0468 #ifdef CONFIG_PM_SLEEP
0469 static int hym8563_suspend(struct device *dev)
0470 {
0471     struct i2c_client *client = to_i2c_client(dev);
0472     int ret;
0473 
0474     if (device_may_wakeup(dev)) {
0475         ret = enable_irq_wake(client->irq);
0476         if (ret) {
0477             dev_err(dev, "enable_irq_wake failed, %d\n", ret);
0478             return ret;
0479         }
0480     }
0481 
0482     return 0;
0483 }
0484 
0485 static int hym8563_resume(struct device *dev)
0486 {
0487     struct i2c_client *client = to_i2c_client(dev);
0488 
0489     if (device_may_wakeup(dev))
0490         disable_irq_wake(client->irq);
0491 
0492     return 0;
0493 }
0494 #endif
0495 
0496 static SIMPLE_DEV_PM_OPS(hym8563_pm_ops, hym8563_suspend, hym8563_resume);
0497 
0498 static int hym8563_probe(struct i2c_client *client)
0499 {
0500     struct hym8563 *hym8563;
0501     int ret;
0502 
0503     hym8563 = devm_kzalloc(&client->dev, sizeof(*hym8563), GFP_KERNEL);
0504     if (!hym8563)
0505         return -ENOMEM;
0506 
0507     hym8563->rtc = devm_rtc_allocate_device(&client->dev);
0508     if (IS_ERR(hym8563->rtc))
0509         return PTR_ERR(hym8563->rtc);
0510 
0511     hym8563->client = client;
0512     i2c_set_clientdata(client, hym8563);
0513 
0514     ret = hym8563_init_device(client);
0515     if (ret) {
0516         dev_err(&client->dev, "could not init device, %d\n", ret);
0517         return ret;
0518     }
0519 
0520     if (client->irq > 0) {
0521         ret = devm_request_threaded_irq(&client->dev, client->irq,
0522                         NULL, hym8563_irq,
0523                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0524                         client->name, hym8563);
0525         if (ret < 0) {
0526             dev_err(&client->dev, "irq %d request failed, %d\n",
0527                 client->irq, ret);
0528             return ret;
0529         }
0530     }
0531 
0532     if (client->irq > 0 ||
0533         device_property_read_bool(&client->dev, "wakeup-source")) {
0534         device_init_wakeup(&client->dev, true);
0535     }
0536 
0537     /* check state of calendar information */
0538     ret = i2c_smbus_read_byte_data(client, HYM8563_SEC);
0539     if (ret < 0)
0540         return ret;
0541 
0542     dev_dbg(&client->dev, "rtc information is %s\n",
0543         (ret & HYM8563_SEC_VL) ? "invalid" : "valid");
0544 
0545     hym8563->rtc->ops = &hym8563_rtc_ops;
0546     set_bit(RTC_FEATURE_ALARM_RES_MINUTE, hym8563->rtc->features);
0547     clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, hym8563->rtc->features);
0548 
0549 #ifdef CONFIG_COMMON_CLK
0550     hym8563_clkout_register_clk(hym8563);
0551 #endif
0552 
0553     return devm_rtc_register_device(hym8563->rtc);
0554 }
0555 
0556 static const struct i2c_device_id hym8563_id[] = {
0557     { "hym8563", 0 },
0558     {},
0559 };
0560 MODULE_DEVICE_TABLE(i2c, hym8563_id);
0561 
0562 static const struct of_device_id hym8563_dt_idtable[] = {
0563     { .compatible = "haoyu,hym8563" },
0564     {},
0565 };
0566 MODULE_DEVICE_TABLE(of, hym8563_dt_idtable);
0567 
0568 static struct i2c_driver hym8563_driver = {
0569     .driver     = {
0570         .name   = "rtc-hym8563",
0571         .pm = &hym8563_pm_ops,
0572         .of_match_table = hym8563_dt_idtable,
0573     },
0574     .probe_new  = hym8563_probe,
0575     .id_table   = hym8563_id,
0576 };
0577 
0578 module_i2c_driver(hym8563_driver);
0579 
0580 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
0581 MODULE_DESCRIPTION("HYM8563 RTC driver");
0582 MODULE_LICENSE("GPL");
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