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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
0004  * chips.
0005  *
0006  * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
0007  * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
0008  *
0009  * References:
0010  *    DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
0011  *    DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
0012  *    DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
0013  *    Application Note 90, Using the Multiplex Bus RTC Extended Features.
0014  */
0015 
0016 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0017 
0018 #include <linux/bcd.h>
0019 #include <linux/delay.h>
0020 #include <linux/io.h>
0021 #include <linux/module.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/rtc.h>
0024 #include <linux/workqueue.h>
0025 
0026 #include <linux/rtc/ds1685.h>
0027 
0028 #ifdef CONFIG_PROC_FS
0029 #include <linux/proc_fs.h>
0030 #endif
0031 
0032 
0033 /* ----------------------------------------------------------------------- */
0034 /*
0035  *  Standard read/write
0036  *  all registers are mapped in CPU address space
0037  */
0038 
0039 /**
0040  * ds1685_read - read a value from an rtc register.
0041  * @rtc: pointer to the ds1685 rtc structure.
0042  * @reg: the register address to read.
0043  */
0044 static u8
0045 ds1685_read(struct ds1685_priv *rtc, int reg)
0046 {
0047     return readb((u8 __iomem *)rtc->regs +
0048              (reg * rtc->regstep));
0049 }
0050 
0051 /**
0052  * ds1685_write - write a value to an rtc register.
0053  * @rtc: pointer to the ds1685 rtc structure.
0054  * @reg: the register address to write.
0055  * @value: value to write to the register.
0056  */
0057 static void
0058 ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
0059 {
0060     writeb(value, ((u8 __iomem *)rtc->regs +
0061                (reg * rtc->regstep)));
0062 }
0063 /* ----------------------------------------------------------------------- */
0064 
0065 /*
0066  * Indirect read/write functions
0067  * access happens via address and data register mapped in CPU address space
0068  */
0069 
0070 /**
0071  * ds1685_indirect_read - read a value from an rtc register.
0072  * @rtc: pointer to the ds1685 rtc structure.
0073  * @reg: the register address to read.
0074  */
0075 static u8
0076 ds1685_indirect_read(struct ds1685_priv *rtc, int reg)
0077 {
0078     writeb(reg, rtc->regs);
0079     return readb(rtc->data);
0080 }
0081 
0082 /**
0083  * ds1685_indirect_write - write a value to an rtc register.
0084  * @rtc: pointer to the ds1685 rtc structure.
0085  * @reg: the register address to write.
0086  * @value: value to write to the register.
0087  */
0088 static void
0089 ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value)
0090 {
0091     writeb(reg, rtc->regs);
0092     writeb(value, rtc->data);
0093 }
0094 
0095 /* ----------------------------------------------------------------------- */
0096 /* Inlined functions */
0097 
0098 /**
0099  * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
0100  * @rtc: pointer to the ds1685 rtc structure.
0101  * @val: u8 time value to consider converting.
0102  * @bcd_mask: u8 mask value if BCD mode is used.
0103  * @bin_mask: u8 mask value if BIN mode is used.
0104  *
0105  * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
0106  */
0107 static inline u8
0108 ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
0109 {
0110     if (rtc->bcd_mode)
0111         return (bcd2bin(val) & bcd_mask);
0112 
0113     return (val & bin_mask);
0114 }
0115 
0116 /**
0117  * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
0118  * @rtc: pointer to the ds1685 rtc structure.
0119  * @val: u8 time value to consider converting.
0120  * @bin_mask: u8 mask value if BIN mode is used.
0121  * @bcd_mask: u8 mask value if BCD mode is used.
0122  *
0123  * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
0124  */
0125 static inline u8
0126 ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
0127 {
0128     if (rtc->bcd_mode)
0129         return (bin2bcd(val) & bcd_mask);
0130 
0131     return (val & bin_mask);
0132 }
0133 
0134 /**
0135  * s1685_rtc_check_mday - check validity of the day of month.
0136  * @rtc: pointer to the ds1685 rtc structure.
0137  * @mday: day of month.
0138  *
0139  * Returns -EDOM if the day of month is not within 1..31 range.
0140  */
0141 static inline int
0142 ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
0143 {
0144     if (rtc->bcd_mode) {
0145         if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
0146             return -EDOM;
0147     } else {
0148         if (mday < 1 || mday > 31)
0149             return -EDOM;
0150     }
0151     return 0;
0152 }
0153 
0154 /**
0155  * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
0156  * @rtc: pointer to the ds1685 rtc structure.
0157  */
0158 static inline void
0159 ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
0160 {
0161     rtc->write(rtc, RTC_CTRL_A,
0162            (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
0163 }
0164 
0165 /**
0166  * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
0167  * @rtc: pointer to the ds1685 rtc structure.
0168  */
0169 static inline void
0170 ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
0171 {
0172     rtc->write(rtc, RTC_CTRL_A,
0173            (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
0174 }
0175 
0176 /**
0177  * ds1685_rtc_begin_data_access - prepare the rtc for data access.
0178  * @rtc: pointer to the ds1685 rtc structure.
0179  *
0180  * This takes several steps to prepare the rtc for access to get/set time
0181  * and alarm values from the rtc registers:
0182  *  - Sets the SET bit in Control Register B.
0183  *  - Reads Ext Control Register 4A and checks the INCR bit.
0184  *  - If INCR is active, a short delay is added before Ext Control Register 4A
0185  *    is read again in a loop until INCR is inactive.
0186  *  - Switches the rtc to bank 1.  This allows access to all relevant
0187  *    data for normal rtc operation, as bank 0 contains only the nvram.
0188  */
0189 static inline void
0190 ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
0191 {
0192     /* Set the SET bit in Ctrl B */
0193     rtc->write(rtc, RTC_CTRL_B,
0194            (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
0195 
0196     /* Switch to Bank 1 */
0197     ds1685_rtc_switch_to_bank1(rtc);
0198 
0199     /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
0200     while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
0201         cpu_relax();
0202 }
0203 
0204 /**
0205  * ds1685_rtc_end_data_access - end data access on the rtc.
0206  * @rtc: pointer to the ds1685 rtc structure.
0207  *
0208  * This ends what was started by ds1685_rtc_begin_data_access:
0209  *  - Switches the rtc back to bank 0.
0210  *  - Clears the SET bit in Control Register B.
0211  */
0212 static inline void
0213 ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
0214 {
0215     /* Switch back to Bank 0 */
0216     ds1685_rtc_switch_to_bank0(rtc);
0217 
0218     /* Clear the SET bit in Ctrl B */
0219     rtc->write(rtc, RTC_CTRL_B,
0220            (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
0221 }
0222 
0223 /**
0224  * ds1685_rtc_get_ssn - retrieve the silicon serial number.
0225  * @rtc: pointer to the ds1685 rtc structure.
0226  * @ssn: u8 array to hold the bits of the silicon serial number.
0227  *
0228  * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
0229  * first byte is the model number, the next six bytes are the serial number
0230  * digits, and the final byte is a CRC check byte.  Together, they form the
0231  * silicon serial number.
0232  *
0233  * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
0234  * called first before calling this function, else data will be read out of
0235  * the bank0 NVRAM.  Be sure to call ds1685_rtc_switch_to_bank0 when done.
0236  */
0237 static inline void
0238 ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
0239 {
0240     ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
0241     ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
0242     ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
0243     ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
0244     ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
0245     ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
0246     ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
0247     ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
0248 }
0249 /* ----------------------------------------------------------------------- */
0250 
0251 
0252 /* ----------------------------------------------------------------------- */
0253 /* Read/Set Time & Alarm functions */
0254 
0255 /**
0256  * ds1685_rtc_read_time - reads the time registers.
0257  * @dev: pointer to device structure.
0258  * @tm: pointer to rtc_time structure.
0259  */
0260 static int
0261 ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
0262 {
0263     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0264     u8 century;
0265     u8 seconds, minutes, hours, wday, mday, month, years;
0266 
0267     /* Fetch the time info from the RTC registers. */
0268     ds1685_rtc_begin_data_access(rtc);
0269     seconds = rtc->read(rtc, RTC_SECS);
0270     minutes = rtc->read(rtc, RTC_MINS);
0271     hours   = rtc->read(rtc, RTC_HRS);
0272     wday    = rtc->read(rtc, RTC_WDAY);
0273     mday    = rtc->read(rtc, RTC_MDAY);
0274     month   = rtc->read(rtc, RTC_MONTH);
0275     years   = rtc->read(rtc, RTC_YEAR);
0276     century = rtc->read(rtc, RTC_CENTURY);
0277     ds1685_rtc_end_data_access(rtc);
0278 
0279     /* bcd2bin if needed, perform fixups, and store to rtc_time. */
0280     years        = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
0281                       RTC_YEAR_BIN_MASK);
0282     century      = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
0283                       RTC_CENTURY_MASK);
0284     tm->tm_sec   = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
0285                       RTC_SECS_BIN_MASK);
0286     tm->tm_min   = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
0287                       RTC_MINS_BIN_MASK);
0288     tm->tm_hour  = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
0289                       RTC_HRS_24_BIN_MASK);
0290     tm->tm_wday  = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
0291                        RTC_WDAY_MASK) - 1);
0292     tm->tm_mday  = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
0293                       RTC_MDAY_BIN_MASK);
0294     tm->tm_mon   = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
0295                        RTC_MONTH_BIN_MASK) - 1);
0296     tm->tm_year  = ((years + (century * 100)) - 1900);
0297     tm->tm_yday  = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
0298     tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
0299 
0300     return 0;
0301 }
0302 
0303 /**
0304  * ds1685_rtc_set_time - sets the time registers.
0305  * @dev: pointer to device structure.
0306  * @tm: pointer to rtc_time structure.
0307  */
0308 static int
0309 ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
0310 {
0311     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0312     u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
0313 
0314     /* Fetch the time info from rtc_time. */
0315     seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
0316                      RTC_SECS_BCD_MASK);
0317     minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
0318                      RTC_MINS_BCD_MASK);
0319     hours   = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
0320                      RTC_HRS_24_BCD_MASK);
0321     wday    = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
0322                      RTC_WDAY_MASK);
0323     mday    = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
0324                      RTC_MDAY_BCD_MASK);
0325     month   = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
0326                      RTC_MONTH_BCD_MASK);
0327     years   = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
0328                      RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
0329     century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
0330                      RTC_CENTURY_MASK, RTC_CENTURY_MASK);
0331 
0332     /*
0333      * Perform Sanity Checks:
0334      *   - Months: !> 12, Month Day != 0.
0335      *   - Month Day !> Max days in current month.
0336      *   - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
0337      */
0338     if ((tm->tm_mon > 11) || (mday == 0))
0339         return -EDOM;
0340 
0341     if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
0342         return -EDOM;
0343 
0344     if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
0345         (tm->tm_sec >= 60)  || (wday > 7))
0346         return -EDOM;
0347 
0348     /*
0349      * Set the data mode to use and store the time values in the
0350      * RTC registers.
0351      */
0352     ds1685_rtc_begin_data_access(rtc);
0353     ctrlb = rtc->read(rtc, RTC_CTRL_B);
0354     if (rtc->bcd_mode)
0355         ctrlb &= ~(RTC_CTRL_B_DM);
0356     else
0357         ctrlb |= RTC_CTRL_B_DM;
0358     rtc->write(rtc, RTC_CTRL_B, ctrlb);
0359     rtc->write(rtc, RTC_SECS, seconds);
0360     rtc->write(rtc, RTC_MINS, minutes);
0361     rtc->write(rtc, RTC_HRS, hours);
0362     rtc->write(rtc, RTC_WDAY, wday);
0363     rtc->write(rtc, RTC_MDAY, mday);
0364     rtc->write(rtc, RTC_MONTH, month);
0365     rtc->write(rtc, RTC_YEAR, years);
0366     rtc->write(rtc, RTC_CENTURY, century);
0367     ds1685_rtc_end_data_access(rtc);
0368 
0369     return 0;
0370 }
0371 
0372 /**
0373  * ds1685_rtc_read_alarm - reads the alarm registers.
0374  * @dev: pointer to device structure.
0375  * @alrm: pointer to rtc_wkalrm structure.
0376  *
0377  * There are three primary alarm registers: seconds, minutes, and hours.
0378  * A fourth alarm register for the month date is also available in bank1 for
0379  * kickstart/wakeup features.  The DS1685/DS1687 manual states that a
0380  * "don't care" value ranging from 0xc0 to 0xff may be written into one or
0381  * more of the three alarm bytes to act as a wildcard value.  The fourth
0382  * byte doesn't support a "don't care" value.
0383  */
0384 static int
0385 ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0386 {
0387     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0388     u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
0389     int ret;
0390 
0391     /* Fetch the alarm info from the RTC alarm registers. */
0392     ds1685_rtc_begin_data_access(rtc);
0393     seconds = rtc->read(rtc, RTC_SECS_ALARM);
0394     minutes = rtc->read(rtc, RTC_MINS_ALARM);
0395     hours   = rtc->read(rtc, RTC_HRS_ALARM);
0396     mday    = rtc->read(rtc, RTC_MDAY_ALARM);
0397     ctrlb   = rtc->read(rtc, RTC_CTRL_B);
0398     ctrlc   = rtc->read(rtc, RTC_CTRL_C);
0399     ds1685_rtc_end_data_access(rtc);
0400 
0401     /* Check the month date for validity. */
0402     ret = ds1685_rtc_check_mday(rtc, mday);
0403     if (ret)
0404         return ret;
0405 
0406     /*
0407      * Check the three alarm bytes.
0408      *
0409      * The Linux RTC system doesn't support the "don't care" capability
0410      * of this RTC chip.  We check for it anyways in case support is
0411      * added in the future and only assign when we care.
0412      */
0413     if (likely(seconds < 0xc0))
0414         alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
0415                                RTC_SECS_BCD_MASK,
0416                                RTC_SECS_BIN_MASK);
0417 
0418     if (likely(minutes < 0xc0))
0419         alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
0420                                RTC_MINS_BCD_MASK,
0421                                RTC_MINS_BIN_MASK);
0422 
0423     if (likely(hours < 0xc0))
0424         alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
0425                             RTC_HRS_24_BCD_MASK,
0426                             RTC_HRS_24_BIN_MASK);
0427 
0428     /* Write the data to rtc_wkalrm. */
0429     alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
0430                         RTC_MDAY_BIN_MASK);
0431     alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
0432     alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
0433 
0434     return 0;
0435 }
0436 
0437 /**
0438  * ds1685_rtc_set_alarm - sets the alarm in registers.
0439  * @dev: pointer to device structure.
0440  * @alrm: pointer to rtc_wkalrm structure.
0441  */
0442 static int
0443 ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0444 {
0445     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0446     u8 ctrlb, seconds, minutes, hours, mday;
0447     int ret;
0448 
0449     /* Fetch the alarm info and convert to BCD. */
0450     seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
0451                      RTC_SECS_BIN_MASK,
0452                      RTC_SECS_BCD_MASK);
0453     minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
0454                      RTC_MINS_BIN_MASK,
0455                      RTC_MINS_BCD_MASK);
0456     hours   = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
0457                      RTC_HRS_24_BIN_MASK,
0458                      RTC_HRS_24_BCD_MASK);
0459     mday    = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
0460                      RTC_MDAY_BIN_MASK,
0461                      RTC_MDAY_BCD_MASK);
0462 
0463     /* Check the month date for validity. */
0464     ret = ds1685_rtc_check_mday(rtc, mday);
0465     if (ret)
0466         return ret;
0467 
0468     /*
0469      * Check the three alarm bytes.
0470      *
0471      * The Linux RTC system doesn't support the "don't care" capability
0472      * of this RTC chip because rtc_valid_tm tries to validate every
0473      * field, and we only support four fields.  We put the support
0474      * here anyways for the future.
0475      */
0476     if (unlikely(seconds >= 0xc0))
0477         seconds = 0xff;
0478 
0479     if (unlikely(minutes >= 0xc0))
0480         minutes = 0xff;
0481 
0482     if (unlikely(hours >= 0xc0))
0483         hours = 0xff;
0484 
0485     alrm->time.tm_mon   = -1;
0486     alrm->time.tm_year  = -1;
0487     alrm->time.tm_wday  = -1;
0488     alrm->time.tm_yday  = -1;
0489     alrm->time.tm_isdst = -1;
0490 
0491     /* Disable the alarm interrupt first. */
0492     ds1685_rtc_begin_data_access(rtc);
0493     ctrlb = rtc->read(rtc, RTC_CTRL_B);
0494     rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
0495 
0496     /* Read ctrlc to clear RTC_CTRL_C_AF. */
0497     rtc->read(rtc, RTC_CTRL_C);
0498 
0499     /*
0500      * Set the data mode to use and store the time values in the
0501      * RTC registers.
0502      */
0503     ctrlb = rtc->read(rtc, RTC_CTRL_B);
0504     if (rtc->bcd_mode)
0505         ctrlb &= ~(RTC_CTRL_B_DM);
0506     else
0507         ctrlb |= RTC_CTRL_B_DM;
0508     rtc->write(rtc, RTC_CTRL_B, ctrlb);
0509     rtc->write(rtc, RTC_SECS_ALARM, seconds);
0510     rtc->write(rtc, RTC_MINS_ALARM, minutes);
0511     rtc->write(rtc, RTC_HRS_ALARM, hours);
0512     rtc->write(rtc, RTC_MDAY_ALARM, mday);
0513 
0514     /* Re-enable the alarm if needed. */
0515     if (alrm->enabled) {
0516         ctrlb = rtc->read(rtc, RTC_CTRL_B);
0517         ctrlb |= RTC_CTRL_B_AIE;
0518         rtc->write(rtc, RTC_CTRL_B, ctrlb);
0519     }
0520 
0521     /* Done! */
0522     ds1685_rtc_end_data_access(rtc);
0523 
0524     return 0;
0525 }
0526 /* ----------------------------------------------------------------------- */
0527 
0528 
0529 /* ----------------------------------------------------------------------- */
0530 /* /dev/rtcX Interface functions */
0531 
0532 /**
0533  * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
0534  * @dev: pointer to device structure.
0535  * @enabled: flag indicating whether to enable or disable.
0536  */
0537 static int
0538 ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0539 {
0540     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0541 
0542     /* Flip the requisite interrupt-enable bit. */
0543     if (enabled)
0544         rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
0545                          RTC_CTRL_B_AIE));
0546     else
0547         rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
0548                          ~(RTC_CTRL_B_AIE)));
0549 
0550     /* Read Control C to clear all the flag bits. */
0551     rtc->read(rtc, RTC_CTRL_C);
0552 
0553     return 0;
0554 }
0555 /* ----------------------------------------------------------------------- */
0556 
0557 
0558 /* ----------------------------------------------------------------------- */
0559 /* IRQ handler */
0560 
0561 /**
0562  * ds1685_rtc_extended_irq - take care of extended interrupts
0563  * @rtc: pointer to the ds1685 rtc structure.
0564  * @pdev: platform device pointer.
0565  */
0566 static void
0567 ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev)
0568 {
0569     u8 ctrl4a, ctrl4b;
0570 
0571     ds1685_rtc_switch_to_bank1(rtc);
0572     ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
0573     ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
0574 
0575     /*
0576      * Check for a kickstart interrupt. With Vcc applied, this
0577      * typically means that the power button was pressed, so we
0578      * begin the shutdown sequence.
0579      */
0580     if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
0581         /* Briefly disable kickstarts to debounce button presses. */
0582         rtc->write(rtc, RTC_EXT_CTRL_4B,
0583                (rtc->read(rtc, RTC_EXT_CTRL_4B) &
0584                 ~(RTC_CTRL_4B_KSE)));
0585 
0586         /* Clear the kickstart flag. */
0587         rtc->write(rtc, RTC_EXT_CTRL_4A,
0588                (ctrl4a & ~(RTC_CTRL_4A_KF)));
0589 
0590 
0591         /*
0592          * Sleep 500ms before re-enabling kickstarts.  This allows
0593          * adequate time to avoid reading signal jitter as additional
0594          * button presses.
0595          */
0596         msleep(500);
0597         rtc->write(rtc, RTC_EXT_CTRL_4B,
0598                (rtc->read(rtc, RTC_EXT_CTRL_4B) |
0599                 RTC_CTRL_4B_KSE));
0600 
0601         /* Call the platform pre-poweroff function. Else, shutdown. */
0602         if (rtc->prepare_poweroff != NULL)
0603             rtc->prepare_poweroff();
0604         else
0605             ds1685_rtc_poweroff(pdev);
0606     }
0607 
0608     /*
0609      * Check for a wake-up interrupt.  With Vcc applied, this is
0610      * essentially a second alarm interrupt, except it takes into
0611      * account the 'date' register in bank1 in addition to the
0612      * standard three alarm registers.
0613      */
0614     if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
0615         rtc->write(rtc, RTC_EXT_CTRL_4A,
0616                (ctrl4a & ~(RTC_CTRL_4A_WF)));
0617 
0618         /* Call the platform wake_alarm function if defined. */
0619         if (rtc->wake_alarm != NULL)
0620             rtc->wake_alarm();
0621         else
0622             dev_warn(&pdev->dev,
0623                  "Wake Alarm IRQ just occurred!\n");
0624     }
0625 
0626     /*
0627      * Check for a ram-clear interrupt.  This happens if RIE=1 and RF=0
0628      * when RCE=1 in 4B.  This clears all NVRAM bytes in bank0 by setting
0629      * each byte to a logic 1.  This has no effect on any extended
0630      * NV-SRAM that might be present, nor on the time/calendar/alarm
0631      * registers.  After a ram-clear is completed, there is a minimum
0632      * recovery time of ~150ms in which all reads/writes are locked out.
0633      * NOTE: A ram-clear can still occur if RCE=1 and RIE=0.  We cannot
0634      * catch this scenario.
0635      */
0636     if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
0637         rtc->write(rtc, RTC_EXT_CTRL_4A,
0638                (ctrl4a & ~(RTC_CTRL_4A_RF)));
0639         msleep(150);
0640 
0641         /* Call the platform post_ram_clear function if defined. */
0642         if (rtc->post_ram_clear != NULL)
0643             rtc->post_ram_clear();
0644         else
0645             dev_warn(&pdev->dev,
0646                  "RAM-Clear IRQ just occurred!\n");
0647     }
0648     ds1685_rtc_switch_to_bank0(rtc);
0649 }
0650 
0651 /**
0652  * ds1685_rtc_irq_handler - IRQ handler.
0653  * @irq: IRQ number.
0654  * @dev_id: platform device pointer.
0655  */
0656 static irqreturn_t
0657 ds1685_rtc_irq_handler(int irq, void *dev_id)
0658 {
0659     struct platform_device *pdev = dev_id;
0660     struct ds1685_priv *rtc = platform_get_drvdata(pdev);
0661     u8 ctrlb, ctrlc;
0662     unsigned long events = 0;
0663     u8 num_irqs = 0;
0664 
0665     /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
0666     if (unlikely(!rtc))
0667         return IRQ_HANDLED;
0668 
0669     rtc_lock(rtc->dev);
0670 
0671     /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
0672     ctrlb = rtc->read(rtc, RTC_CTRL_B);
0673     ctrlc = rtc->read(rtc, RTC_CTRL_C);
0674 
0675     /* Is the IRQF bit set? */
0676     if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
0677         /*
0678          * We need to determine if it was one of the standard
0679          * events: PF, AF, or UF.  If so, we handle them and
0680          * update the RTC core.
0681          */
0682         if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
0683             events = RTC_IRQF;
0684 
0685             /* Check for a periodic interrupt. */
0686             if ((ctrlb & RTC_CTRL_B_PIE) &&
0687                 (ctrlc & RTC_CTRL_C_PF)) {
0688                 events |= RTC_PF;
0689                 num_irqs++;
0690             }
0691 
0692             /* Check for an alarm interrupt. */
0693             if ((ctrlb & RTC_CTRL_B_AIE) &&
0694                 (ctrlc & RTC_CTRL_C_AF)) {
0695                 events |= RTC_AF;
0696                 num_irqs++;
0697             }
0698 
0699             /* Check for an update interrupt. */
0700             if ((ctrlb & RTC_CTRL_B_UIE) &&
0701                 (ctrlc & RTC_CTRL_C_UF)) {
0702                 events |= RTC_UF;
0703                 num_irqs++;
0704             }
0705         } else {
0706             /*
0707              * One of the "extended" interrupts was received that
0708              * is not recognized by the RTC core.
0709              */
0710             ds1685_rtc_extended_irq(rtc, pdev);
0711         }
0712     }
0713     rtc_update_irq(rtc->dev, num_irqs, events);
0714     rtc_unlock(rtc->dev);
0715 
0716     return events ? IRQ_HANDLED : IRQ_NONE;
0717 }
0718 /* ----------------------------------------------------------------------- */
0719 
0720 
0721 /* ----------------------------------------------------------------------- */
0722 /* ProcFS interface */
0723 
0724 #ifdef CONFIG_PROC_FS
0725 #define NUM_REGS    6   /* Num of control registers. */
0726 #define NUM_BITS    8   /* Num bits per register. */
0727 #define NUM_SPACES  4   /* Num spaces between each bit. */
0728 
0729 /*
0730  * Periodic Interrupt Rates.
0731  */
0732 static const char *ds1685_rtc_pirq_rate[16] = {
0733     "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
0734     "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
0735     "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
0736 };
0737 
0738 /*
0739  * Square-Wave Output Frequencies.
0740  */
0741 static const char *ds1685_rtc_sqw_freq[16] = {
0742     "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
0743     "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
0744 };
0745 
0746 /**
0747  * ds1685_rtc_proc - procfs access function.
0748  * @dev: pointer to device structure.
0749  * @seq: pointer to seq_file structure.
0750  */
0751 static int
0752 ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
0753 {
0754     struct ds1685_priv *rtc = dev_get_drvdata(dev);
0755     u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8];
0756     char *model;
0757 
0758     /* Read all the relevant data from the control registers. */
0759     ds1685_rtc_switch_to_bank1(rtc);
0760     ds1685_rtc_get_ssn(rtc, ssn);
0761     ctrla = rtc->read(rtc, RTC_CTRL_A);
0762     ctrlb = rtc->read(rtc, RTC_CTRL_B);
0763     ctrld = rtc->read(rtc, RTC_CTRL_D);
0764     ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
0765     ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
0766     ds1685_rtc_switch_to_bank0(rtc);
0767 
0768     /* Determine the RTC model. */
0769     switch (ssn[0]) {
0770     case RTC_MODEL_DS1685:
0771         model = "DS1685/DS1687\0";
0772         break;
0773     case RTC_MODEL_DS1689:
0774         model = "DS1689/DS1693\0";
0775         break;
0776     case RTC_MODEL_DS17285:
0777         model = "DS17285/DS17287\0";
0778         break;
0779     case RTC_MODEL_DS17485:
0780         model = "DS17485/DS17487\0";
0781         break;
0782     case RTC_MODEL_DS17885:
0783         model = "DS17885/DS17887\0";
0784         break;
0785     default:
0786         model = "Unknown\0";
0787         break;
0788     }
0789 
0790     /* Print out the information. */
0791     seq_printf(seq,
0792        "Model\t\t: %s\n"
0793        "Oscillator\t: %s\n"
0794        "12/24hr\t\t: %s\n"
0795        "DST\t\t: %s\n"
0796        "Data mode\t: %s\n"
0797        "Battery\t\t: %s\n"
0798        "Aux batt\t: %s\n"
0799        "Update IRQ\t: %s\n"
0800        "Periodic IRQ\t: %s\n"
0801        "Periodic Rate\t: %s\n"
0802        "SQW Freq\t: %s\n"
0803        "Serial #\t: %8phC\n",
0804        model,
0805        ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
0806        ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
0807        ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
0808        ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
0809        ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
0810        ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
0811        ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
0812        ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
0813        (!(ctrl4b & RTC_CTRL_4B_E32K) ?
0814         ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
0815        (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
0816         ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
0817        ssn);
0818     return 0;
0819 }
0820 #else
0821 #define ds1685_rtc_proc NULL
0822 #endif /* CONFIG_PROC_FS */
0823 /* ----------------------------------------------------------------------- */
0824 
0825 
0826 /* ----------------------------------------------------------------------- */
0827 /* RTC Class operations */
0828 
0829 static const struct rtc_class_ops
0830 ds1685_rtc_ops = {
0831     .proc = ds1685_rtc_proc,
0832     .read_time = ds1685_rtc_read_time,
0833     .set_time = ds1685_rtc_set_time,
0834     .read_alarm = ds1685_rtc_read_alarm,
0835     .set_alarm = ds1685_rtc_set_alarm,
0836     .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
0837 };
0838 /* ----------------------------------------------------------------------- */
0839 
0840 static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
0841                  size_t size)
0842 {
0843     struct ds1685_priv *rtc = priv;
0844     struct mutex *rtc_mutex = &rtc->dev->ops_lock;
0845     ssize_t count;
0846     u8 *buf = val;
0847     int err;
0848 
0849     err = mutex_lock_interruptible(rtc_mutex);
0850     if (err)
0851         return err;
0852 
0853     ds1685_rtc_switch_to_bank0(rtc);
0854 
0855     /* Read NVRAM in time and bank0 registers. */
0856     for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
0857          count++, size--) {
0858         if (count < NVRAM_SZ_TIME)
0859             *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
0860         else
0861             *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
0862     }
0863 
0864 #ifndef CONFIG_RTC_DRV_DS1689
0865     if (size > 0) {
0866         ds1685_rtc_switch_to_bank1(rtc);
0867 
0868 #ifndef CONFIG_RTC_DRV_DS1685
0869         /* Enable burst-mode on DS17x85/DS17x87 */
0870         rtc->write(rtc, RTC_EXT_CTRL_4A,
0871                (rtc->read(rtc, RTC_EXT_CTRL_4A) |
0872                 RTC_CTRL_4A_BME));
0873 
0874         /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
0875          * reading with burst-mode */
0876         rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
0877                (pos - NVRAM_TOTAL_SZ_BANK0));
0878 #endif
0879 
0880         /* Read NVRAM in bank1 registers. */
0881         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
0882              count++, size--) {
0883 #ifdef CONFIG_RTC_DRV_DS1685
0884             /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
0885              * before each read. */
0886             rtc->write(rtc, RTC_BANK1_RAM_ADDR,
0887                    (pos - NVRAM_TOTAL_SZ_BANK0));
0888 #endif
0889             *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
0890             pos++;
0891         }
0892 
0893 #ifndef CONFIG_RTC_DRV_DS1685
0894         /* Disable burst-mode on DS17x85/DS17x87 */
0895         rtc->write(rtc, RTC_EXT_CTRL_4A,
0896                (rtc->read(rtc, RTC_EXT_CTRL_4A) &
0897                 ~(RTC_CTRL_4A_BME)));
0898 #endif
0899         ds1685_rtc_switch_to_bank0(rtc);
0900     }
0901 #endif /* !CONFIG_RTC_DRV_DS1689 */
0902     mutex_unlock(rtc_mutex);
0903 
0904     return 0;
0905 }
0906 
0907 static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
0908                   size_t size)
0909 {
0910     struct ds1685_priv *rtc = priv;
0911     struct mutex *rtc_mutex = &rtc->dev->ops_lock;
0912     ssize_t count;
0913     u8 *buf = val;
0914     int err;
0915 
0916     err = mutex_lock_interruptible(rtc_mutex);
0917     if (err)
0918         return err;
0919 
0920     ds1685_rtc_switch_to_bank0(rtc);
0921 
0922     /* Write NVRAM in time and bank0 registers. */
0923     for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
0924          count++, size--)
0925         if (count < NVRAM_SZ_TIME)
0926             rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
0927                    *buf++);
0928         else
0929             rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
0930 
0931 #ifndef CONFIG_RTC_DRV_DS1689
0932     if (size > 0) {
0933         ds1685_rtc_switch_to_bank1(rtc);
0934 
0935 #ifndef CONFIG_RTC_DRV_DS1685
0936         /* Enable burst-mode on DS17x85/DS17x87 */
0937         rtc->write(rtc, RTC_EXT_CTRL_4A,
0938                (rtc->read(rtc, RTC_EXT_CTRL_4A) |
0939                 RTC_CTRL_4A_BME));
0940 
0941         /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
0942          * writing with burst-mode */
0943         rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
0944                (pos - NVRAM_TOTAL_SZ_BANK0));
0945 #endif
0946 
0947         /* Write NVRAM in bank1 registers. */
0948         for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
0949              count++, size--) {
0950 #ifdef CONFIG_RTC_DRV_DS1685
0951             /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
0952              * before each read. */
0953             rtc->write(rtc, RTC_BANK1_RAM_ADDR,
0954                    (pos - NVRAM_TOTAL_SZ_BANK0));
0955 #endif
0956             rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
0957             pos++;
0958         }
0959 
0960 #ifndef CONFIG_RTC_DRV_DS1685
0961         /* Disable burst-mode on DS17x85/DS17x87 */
0962         rtc->write(rtc, RTC_EXT_CTRL_4A,
0963                (rtc->read(rtc, RTC_EXT_CTRL_4A) &
0964                 ~(RTC_CTRL_4A_BME)));
0965 #endif
0966         ds1685_rtc_switch_to_bank0(rtc);
0967     }
0968 #endif /* !CONFIG_RTC_DRV_DS1689 */
0969     mutex_unlock(rtc_mutex);
0970 
0971     return 0;
0972 }
0973 
0974 /* ----------------------------------------------------------------------- */
0975 /* SysFS interface */
0976 
0977 /**
0978  * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
0979  * @dev: pointer to device structure.
0980  * @attr: pointer to device_attribute structure.
0981  * @buf: pointer to char array to hold the output.
0982  */
0983 static ssize_t
0984 ds1685_rtc_sysfs_battery_show(struct device *dev,
0985                   struct device_attribute *attr, char *buf)
0986 {
0987     struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
0988     u8 ctrld;
0989 
0990     ctrld = rtc->read(rtc, RTC_CTRL_D);
0991 
0992     return sprintf(buf, "%s\n",
0993             (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
0994 }
0995 static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
0996 
0997 /**
0998  * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
0999  * @dev: pointer to device structure.
1000  * @attr: pointer to device_attribute structure.
1001  * @buf: pointer to char array to hold the output.
1002  */
1003 static ssize_t
1004 ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
1005                   struct device_attribute *attr, char *buf)
1006 {
1007     struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
1008     u8 ctrl4a;
1009 
1010     ds1685_rtc_switch_to_bank1(rtc);
1011     ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1012     ds1685_rtc_switch_to_bank0(rtc);
1013 
1014     return sprintf(buf, "%s\n",
1015             (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
1016 }
1017 static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
1018 
1019 /**
1020  * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
1021  * @dev: pointer to device structure.
1022  * @attr: pointer to device_attribute structure.
1023  * @buf: pointer to char array to hold the output.
1024  */
1025 static ssize_t
1026 ds1685_rtc_sysfs_serial_show(struct device *dev,
1027                  struct device_attribute *attr, char *buf)
1028 {
1029     struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
1030     u8 ssn[8];
1031 
1032     ds1685_rtc_switch_to_bank1(rtc);
1033     ds1685_rtc_get_ssn(rtc, ssn);
1034     ds1685_rtc_switch_to_bank0(rtc);
1035 
1036     return sprintf(buf, "%8phC\n", ssn);
1037 }
1038 static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
1039 
1040 /*
1041  * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
1042  */
1043 static struct attribute*
1044 ds1685_rtc_sysfs_misc_attrs[] = {
1045     &dev_attr_battery.attr,
1046     &dev_attr_auxbatt.attr,
1047     &dev_attr_serial.attr,
1048     NULL,
1049 };
1050 
1051 /*
1052  * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
1053  */
1054 static const struct attribute_group
1055 ds1685_rtc_sysfs_misc_grp = {
1056     .name = "misc",
1057     .attrs = ds1685_rtc_sysfs_misc_attrs,
1058 };
1059 
1060 /* ----------------------------------------------------------------------- */
1061 /* Driver Probe/Removal */
1062 
1063 /**
1064  * ds1685_rtc_probe - initializes rtc driver.
1065  * @pdev: pointer to platform_device structure.
1066  */
1067 static int
1068 ds1685_rtc_probe(struct platform_device *pdev)
1069 {
1070     struct rtc_device *rtc_dev;
1071     struct ds1685_priv *rtc;
1072     struct ds1685_rtc_platform_data *pdata;
1073     u8 ctrla, ctrlb, hours;
1074     unsigned char am_pm;
1075     int ret = 0;
1076     struct nvmem_config nvmem_cfg = {
1077         .name = "ds1685_nvram",
1078         .size = NVRAM_TOTAL_SZ,
1079         .reg_read = ds1685_nvram_read,
1080         .reg_write = ds1685_nvram_write,
1081     };
1082 
1083     /* Get the platform data. */
1084     pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
1085     if (!pdata)
1086         return -ENODEV;
1087 
1088     /* Allocate memory for the rtc device. */
1089     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1090     if (!rtc)
1091         return -ENOMEM;
1092 
1093     /* Setup resources and access functions */
1094     switch (pdata->access_type) {
1095     case ds1685_reg_direct:
1096         rtc->regs = devm_platform_ioremap_resource(pdev, 0);
1097         if (IS_ERR(rtc->regs))
1098             return PTR_ERR(rtc->regs);
1099         rtc->read = ds1685_read;
1100         rtc->write = ds1685_write;
1101         break;
1102     case ds1685_reg_indirect:
1103         rtc->regs = devm_platform_ioremap_resource(pdev, 0);
1104         if (IS_ERR(rtc->regs))
1105             return PTR_ERR(rtc->regs);
1106         rtc->data = devm_platform_ioremap_resource(pdev, 1);
1107         if (IS_ERR(rtc->data))
1108             return PTR_ERR(rtc->data);
1109         rtc->read = ds1685_indirect_read;
1110         rtc->write = ds1685_indirect_write;
1111         break;
1112     }
1113 
1114     if (!rtc->read || !rtc->write)
1115         return -ENXIO;
1116 
1117     /* Get the register step size. */
1118     if (pdata->regstep > 0)
1119         rtc->regstep = pdata->regstep;
1120     else
1121         rtc->regstep = 1;
1122 
1123     /* Platform pre-shutdown function, if defined. */
1124     if (pdata->plat_prepare_poweroff)
1125         rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
1126 
1127     /* Platform wake_alarm function, if defined. */
1128     if (pdata->plat_wake_alarm)
1129         rtc->wake_alarm = pdata->plat_wake_alarm;
1130 
1131     /* Platform post_ram_clear function, if defined. */
1132     if (pdata->plat_post_ram_clear)
1133         rtc->post_ram_clear = pdata->plat_post_ram_clear;
1134 
1135     /* set the driver data. */
1136     platform_set_drvdata(pdev, rtc);
1137 
1138     /* Turn the oscillator on if is not already on (DV1 = 1). */
1139     ctrla = rtc->read(rtc, RTC_CTRL_A);
1140     if (!(ctrla & RTC_CTRL_A_DV1))
1141         ctrla |= RTC_CTRL_A_DV1;
1142 
1143     /* Enable the countdown chain (DV2 = 0) */
1144     ctrla &= ~(RTC_CTRL_A_DV2);
1145 
1146     /* Clear RS3-RS0 in Control A. */
1147     ctrla &= ~(RTC_CTRL_A_RS_MASK);
1148 
1149     /*
1150      * All done with Control A.  Switch to Bank 1 for the remainder of
1151      * the RTC setup so we have access to the extended functions.
1152      */
1153     ctrla |= RTC_CTRL_A_DV0;
1154     rtc->write(rtc, RTC_CTRL_A, ctrla);
1155 
1156     /* Default to 32768kHz output. */
1157     rtc->write(rtc, RTC_EXT_CTRL_4B,
1158            (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
1159 
1160     /* Set the SET bit in Control B so we can do some housekeeping. */
1161     rtc->write(rtc, RTC_CTRL_B,
1162            (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
1163 
1164     /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
1165     while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
1166         cpu_relax();
1167 
1168     /*
1169      * If the platform supports BCD mode, then set DM=0 in Control B.
1170      * Otherwise, set DM=1 for BIN mode.
1171      */
1172     ctrlb = rtc->read(rtc, RTC_CTRL_B);
1173     if (pdata->bcd_mode)
1174         ctrlb &= ~(RTC_CTRL_B_DM);
1175     else
1176         ctrlb |= RTC_CTRL_B_DM;
1177     rtc->bcd_mode = pdata->bcd_mode;
1178 
1179     /*
1180      * Disable Daylight Savings Time (DSE = 0).
1181      * The RTC has hardcoded timezone information that is rendered
1182      * obselete.  We'll let the OS deal with DST settings instead.
1183      */
1184     if (ctrlb & RTC_CTRL_B_DSE)
1185         ctrlb &= ~(RTC_CTRL_B_DSE);
1186 
1187     /* Force 24-hour mode (2412 = 1). */
1188     if (!(ctrlb & RTC_CTRL_B_2412)) {
1189         /* Reinitialize the time hours. */
1190         hours = rtc->read(rtc, RTC_HRS);
1191         am_pm = hours & RTC_HRS_AMPM_MASK;
1192         hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1193                        RTC_HRS_12_BIN_MASK);
1194         hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1195 
1196         /* Enable 24-hour mode. */
1197         ctrlb |= RTC_CTRL_B_2412;
1198 
1199         /* Write back to Control B, including DM & DSE bits. */
1200         rtc->write(rtc, RTC_CTRL_B, ctrlb);
1201 
1202         /* Write the time hours back. */
1203         rtc->write(rtc, RTC_HRS,
1204                ds1685_rtc_bin2bcd(rtc, hours,
1205                           RTC_HRS_24_BIN_MASK,
1206                           RTC_HRS_24_BCD_MASK));
1207 
1208         /* Reinitialize the alarm hours. */
1209         hours = rtc->read(rtc, RTC_HRS_ALARM);
1210         am_pm = hours & RTC_HRS_AMPM_MASK;
1211         hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
1212                        RTC_HRS_12_BIN_MASK);
1213         hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
1214 
1215         /* Write the alarm hours back. */
1216         rtc->write(rtc, RTC_HRS_ALARM,
1217                ds1685_rtc_bin2bcd(rtc, hours,
1218                           RTC_HRS_24_BIN_MASK,
1219                           RTC_HRS_24_BCD_MASK));
1220     } else {
1221         /* 24-hour mode is already set, so write Control B back. */
1222         rtc->write(rtc, RTC_CTRL_B, ctrlb);
1223     }
1224 
1225     /* Unset the SET bit in Control B so the RTC can update. */
1226     rtc->write(rtc, RTC_CTRL_B,
1227            (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
1228 
1229     /* Check the main battery. */
1230     if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
1231         dev_warn(&pdev->dev,
1232              "Main battery is exhausted! RTC may be invalid!\n");
1233 
1234     /* Check the auxillary battery.  It is optional. */
1235     if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
1236         dev_warn(&pdev->dev,
1237              "Aux battery is exhausted or not available.\n");
1238 
1239     /* Read Ctrl B and clear PIE/AIE/UIE. */
1240     rtc->write(rtc, RTC_CTRL_B,
1241            (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
1242 
1243     /* Reading Ctrl C auto-clears PF/AF/UF. */
1244     rtc->read(rtc, RTC_CTRL_C);
1245 
1246     /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1247     rtc->write(rtc, RTC_EXT_CTRL_4B,
1248            (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
1249 
1250     /* Clear RF/WF/KF in Ctrl 4A. */
1251     rtc->write(rtc, RTC_EXT_CTRL_4A,
1252            (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
1253 
1254     /*
1255      * Re-enable KSE to handle power button events.  We do not enable
1256      * WIE or RIE by default.
1257      */
1258     rtc->write(rtc, RTC_EXT_CTRL_4B,
1259            (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
1260 
1261     rtc_dev = devm_rtc_allocate_device(&pdev->dev);
1262     if (IS_ERR(rtc_dev))
1263         return PTR_ERR(rtc_dev);
1264 
1265     rtc_dev->ops = &ds1685_rtc_ops;
1266 
1267     /* Century bit is useless because leap year fails in 1900 and 2100 */
1268     rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
1269     rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
1270 
1271     /* Maximum periodic rate is 8192Hz (0.122070ms). */
1272     rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
1273 
1274     /* See if the platform doesn't support UIE. */
1275     if (pdata->uie_unsupported)
1276         clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc_dev->features);
1277 
1278     rtc->dev = rtc_dev;
1279 
1280     /*
1281      * Fetch the IRQ and setup the interrupt handler.
1282      *
1283      * Not all platforms have the IRQF pin tied to something.  If not, the
1284      * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
1285      * there won't be an automatic way of notifying the kernel about it,
1286      * unless ctrlc is explicitly polled.
1287      */
1288     rtc->irq_num = platform_get_irq(pdev, 0);
1289     if (rtc->irq_num <= 0) {
1290         clear_bit(RTC_FEATURE_ALARM, rtc_dev->features);
1291     } else {
1292         /* Request an IRQ. */
1293         ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num,
1294                        NULL, ds1685_rtc_irq_handler,
1295                        IRQF_SHARED | IRQF_ONESHOT,
1296                        pdev->name, pdev);
1297 
1298         /* Check to see if something came back. */
1299         if (unlikely(ret)) {
1300             dev_warn(&pdev->dev,
1301                  "RTC interrupt not available\n");
1302             rtc->irq_num = 0;
1303         }
1304     }
1305 
1306     /* Setup complete. */
1307     ds1685_rtc_switch_to_bank0(rtc);
1308 
1309     ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
1310     if (ret)
1311         return ret;
1312 
1313     nvmem_cfg.priv = rtc;
1314     ret = devm_rtc_nvmem_register(rtc_dev, &nvmem_cfg);
1315     if (ret)
1316         return ret;
1317 
1318     return devm_rtc_register_device(rtc_dev);
1319 }
1320 
1321 /**
1322  * ds1685_rtc_remove - removes rtc driver.
1323  * @pdev: pointer to platform_device structure.
1324  */
1325 static int
1326 ds1685_rtc_remove(struct platform_device *pdev)
1327 {
1328     struct ds1685_priv *rtc = platform_get_drvdata(pdev);
1329 
1330     /* Read Ctrl B and clear PIE/AIE/UIE. */
1331     rtc->write(rtc, RTC_CTRL_B,
1332            (rtc->read(rtc, RTC_CTRL_B) &
1333             ~(RTC_CTRL_B_PAU_MASK)));
1334 
1335     /* Reading Ctrl C auto-clears PF/AF/UF. */
1336     rtc->read(rtc, RTC_CTRL_C);
1337 
1338     /* Read Ctrl 4B and clear RIE/WIE/KSE. */
1339     rtc->write(rtc, RTC_EXT_CTRL_4B,
1340            (rtc->read(rtc, RTC_EXT_CTRL_4B) &
1341             ~(RTC_CTRL_4B_RWK_MASK)));
1342 
1343     /* Manually clear RF/WF/KF in Ctrl 4A. */
1344     rtc->write(rtc, RTC_EXT_CTRL_4A,
1345            (rtc->read(rtc, RTC_EXT_CTRL_4A) &
1346             ~(RTC_CTRL_4A_RWK_MASK)));
1347 
1348     return 0;
1349 }
1350 
1351 /*
1352  * ds1685_rtc_driver - rtc driver properties.
1353  */
1354 static struct platform_driver ds1685_rtc_driver = {
1355     .driver     = {
1356         .name   = "rtc-ds1685",
1357     },
1358     .probe      = ds1685_rtc_probe,
1359     .remove     = ds1685_rtc_remove,
1360 };
1361 module_platform_driver(ds1685_rtc_driver);
1362 /* ----------------------------------------------------------------------- */
1363 
1364 
1365 /* ----------------------------------------------------------------------- */
1366 /* Poweroff function */
1367 
1368 /**
1369  * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
1370  * @pdev: pointer to platform_device structure.
1371  */
1372 void __noreturn
1373 ds1685_rtc_poweroff(struct platform_device *pdev)
1374 {
1375     u8 ctrla, ctrl4a, ctrl4b;
1376     struct ds1685_priv *rtc;
1377 
1378     /* Check for valid RTC data, else, spin forever. */
1379     if (unlikely(!pdev)) {
1380         pr_emerg("platform device data not available, spinning forever ...\n");
1381         while(1);
1382         unreachable();
1383     } else {
1384         /* Get the rtc data. */
1385         rtc = platform_get_drvdata(pdev);
1386 
1387         /*
1388          * Disable our IRQ.  We're powering down, so we're not
1389          * going to worry about cleaning up.  Most of that should
1390          * have been taken care of by the shutdown scripts and this
1391          * is the final function call.
1392          */
1393         if (rtc->irq_num)
1394             disable_irq_nosync(rtc->irq_num);
1395 
1396         /* Oscillator must be on and the countdown chain enabled. */
1397         ctrla = rtc->read(rtc, RTC_CTRL_A);
1398         ctrla |= RTC_CTRL_A_DV1;
1399         ctrla &= ~(RTC_CTRL_A_DV2);
1400         rtc->write(rtc, RTC_CTRL_A, ctrla);
1401 
1402         /*
1403          * Read Control 4A and check the status of the auxillary
1404          * battery.  This must be present and working (VRT2 = 1)
1405          * for wakeup and kickstart functionality to be useful.
1406          */
1407         ds1685_rtc_switch_to_bank1(rtc);
1408         ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
1409         if (ctrl4a & RTC_CTRL_4A_VRT2) {
1410             /* Clear all of the interrupt flags on Control 4A. */
1411             ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
1412             rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
1413 
1414             /*
1415              * The auxillary battery is present and working.
1416              * Enable extended functions (ABE=1), enable
1417              * wake-up (WIE=1), and enable kickstart (KSE=1)
1418              * in Control 4B.
1419              */
1420             ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
1421             ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
1422                    RTC_CTRL_4B_KSE);
1423             rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
1424         }
1425 
1426         /* Set PAB to 1 in Control 4A to power the system down. */
1427         dev_warn(&pdev->dev, "Powerdown.\n");
1428         msleep(20);
1429         rtc->write(rtc, RTC_EXT_CTRL_4A,
1430                (ctrl4a | RTC_CTRL_4A_PAB));
1431 
1432         /* Spin ... we do not switch back to bank0. */
1433         while(1);
1434         unreachable();
1435     }
1436 }
1437 EXPORT_SYMBOL(ds1685_rtc_poweroff);
1438 /* ----------------------------------------------------------------------- */
1439 
1440 
1441 MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
1442 MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
1443 MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
1444 MODULE_LICENSE("GPL");
1445 MODULE_ALIAS("platform:rtc-ds1685");
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