drivers/rtc/rtc-ds1343.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* rtc-ds1343.c
0003  *
0004  * Driver for Dallas Semiconductor DS1343 Low Current, SPI Compatible
0005  * Real Time Clock
0006  *
0007  * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>
0008  *      Ankur Srivastava <sankurece@gmail.com> : DS1343 Nvram Support
0009  */
0010
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/device.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/regmap.h>
0017 #include <linux/rtc.h>
0018 #include <linux/bcd.h>
0019 #include <linux/pm.h>
0020 #include <linux/pm_wakeirq.h>
0021 #include <linux/slab.h>
0022
0023 #define DALLAS_MAXIM_DS1343 0
0024 #define DALLAS_MAXIM_DS1344 1
0025
0026 /* RTC DS1343 Registers */
0027 #define DS1343_SECONDS_REG  0x00
0028 #define DS1343_MINUTES_REG  0x01
0029 #define DS1343_HOURS_REG    0x02
0030 #define DS1343_DAY_REG      0x03
0031 #define DS1343_DATE_REG     0x04
0032 #define DS1343_MONTH_REG    0x05
0033 #define DS1343_YEAR_REG     0x06
0034 #define DS1343_ALM0_SEC_REG 0x07
0035 #define DS1343_ALM0_MIN_REG 0x08
0036 #define DS1343_ALM0_HOUR_REG    0x09
0037 #define DS1343_ALM0_DAY_REG 0x0A
0038 #define DS1343_ALM1_SEC_REG 0x0B
0039 #define DS1343_ALM1_MIN_REG 0x0C
0040 #define DS1343_ALM1_HOUR_REG    0x0D
0041 #define DS1343_ALM1_DAY_REG 0x0E
0042 #define DS1343_CONTROL_REG  0x0F
0043 #define DS1343_STATUS_REG   0x10
0044 #define DS1343_TRICKLE_REG  0x11
0045 #define DS1343_NVRAM        0x20
0046
0047 #define DS1343_NVRAM_LEN    96
0048
0049 /* DS1343 Control Registers bits */
0050 #define DS1343_EOSC     0x80
0051 #define DS1343_DOSF     0x20
0052 #define DS1343_EGFIL        0x10
0053 #define DS1343_SQW      0x08
0054 #define DS1343_INTCN        0x04
0055 #define DS1343_A1IE     0x02
0056 #define DS1343_A0IE     0x01
0057
0058 /* DS1343 Status Registers bits */
0059 #define DS1343_OSF      0x80
0060 #define DS1343_IRQF1        0x02
0061 #define DS1343_IRQF0        0x01
0062
0063 /* DS1343 Trickle Charger Registers bits */
0064 #define DS1343_TRICKLE_MAGIC    0xa0
0065 #define DS1343_TRICKLE_DS1  0x08
0066 #define DS1343_TRICKLE_1K   0x01
0067 #define DS1343_TRICKLE_2K   0x02
0068 #define DS1343_TRICKLE_4K   0x03
0069
0070 static const struct spi_device_id ds1343_id[] = {
0071     { "ds1343", DALLAS_MAXIM_DS1343 },
0072     { "ds1344", DALLAS_MAXIM_DS1344 },
0073     { }
0074 };
0075 MODULE_DEVICE_TABLE(spi, ds1343_id);
0076
0077 struct ds1343_priv {
0078     struct rtc_device *rtc;
0079     struct regmap *map;
0080     int irq;
0081 };
0082
0083 static ssize_t ds1343_show_glitchfilter(struct device *dev,
0084                 struct device_attribute *attr, char *buf)
0085 {
0086     struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
0087     int glitch_filt_status, data;
0088     int res;
0089
0090     res = regmap_read(priv->map, DS1343_CONTROL_REG, &data);
0091     if (res)
0092         return res;
0093
0094     glitch_filt_status = !!(data & DS1343_EGFIL);
0095
0096     if (glitch_filt_status)
0097         return sprintf(buf, "enabled\n");
0098     else
0099         return sprintf(buf, "disabled\n");
0100 }
0101
0102 static ssize_t ds1343_store_glitchfilter(struct device *dev,
0103                     struct device_attribute *attr,
0104                     const char *buf, size_t count)
0105 {
0106     struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
0107     int data = 0;
0108     int res;
0109
0110     if (strncmp(buf, "enabled", 7) == 0)
0111         data = DS1343_EGFIL;
0112     else if (strncmp(buf, "disabled", 8))
0113         return -EINVAL;
0114
0115     res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
0116                  DS1343_EGFIL, data);
0117     if (res)
0118         return res;
0119
0120     return count;
0121 }
0122
0123 static DEVICE_ATTR(glitch_filter, S_IRUGO | S_IWUSR, ds1343_show_glitchfilter,
0124             ds1343_store_glitchfilter);
0125
0126 static int ds1343_nvram_write(void *priv, unsigned int off, void *val,
0127                   size_t bytes)
0128 {
0129     struct ds1343_priv *ds1343 = priv;
0130
0131     return regmap_bulk_write(ds1343->map, DS1343_NVRAM + off, val, bytes);
0132 }
0133
0134 static int ds1343_nvram_read(void *priv, unsigned int off, void *val,
0135                  size_t bytes)
0136 {
0137     struct ds1343_priv *ds1343 = priv;
0138
0139     return regmap_bulk_read(ds1343->map, DS1343_NVRAM + off, val, bytes);
0140 }
0141
0142 static ssize_t ds1343_show_tricklecharger(struct device *dev,
0143                 struct device_attribute *attr, char *buf)
0144 {
0145     struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
0146     int res, data;
0147     char *diodes = "disabled", *resistors = " ";
0148
0149     res = regmap_read(priv->map, DS1343_TRICKLE_REG, &data);
0150     if (res)
0151         return res;
0152
0153     if ((data & 0xf0) == DS1343_TRICKLE_MAGIC) {
0154         switch (data & 0x0c) {
0155         case DS1343_TRICKLE_DS1:
0156             diodes = "one diode,";
0157             break;
0158
0159         default:
0160             diodes = "no diode,";
0161             break;
0162         }
0163
0164         switch (data & 0x03) {
0165         case DS1343_TRICKLE_1K:
0166             resistors = "1k Ohm";
0167             break;
0168
0169         case DS1343_TRICKLE_2K:
0170             resistors = "2k Ohm";
0171             break;
0172
0173         case DS1343_TRICKLE_4K:
0174             resistors = "4k Ohm";
0175             break;
0176
0177         default:
0178             diodes = "disabled";
0179             break;
0180         }
0181     }
0182
0183     return sprintf(buf, "%s %s\n", diodes, resistors);
0184 }
0185
0186 static DEVICE_ATTR(trickle_charger, S_IRUGO, ds1343_show_tricklecharger, NULL);
0187
0188 static struct attribute *ds1343_attrs[] = {
0189     &dev_attr_glitch_filter.attr,
0190     &dev_attr_trickle_charger.attr,
0191     NULL
0192 };
0193
0194 static const struct attribute_group ds1343_attr_group = {
0195     .attrs  = ds1343_attrs,
0196 };
0197
0198 static int ds1343_read_time(struct device *dev, struct rtc_time *dt)
0199 {
0200     struct ds1343_priv *priv = dev_get_drvdata(dev);
0201     unsigned char buf[7];
0202     int res;
0203
0204     res = regmap_bulk_read(priv->map, DS1343_SECONDS_REG, buf, 7);
0205     if (res)
0206         return res;
0207
0208     dt->tm_sec  = bcd2bin(buf[0]);
0209     dt->tm_min  = bcd2bin(buf[1]);
0210     dt->tm_hour = bcd2bin(buf[2] & 0x3F);
0211     dt->tm_wday = bcd2bin(buf[3]) - 1;
0212     dt->tm_mday = bcd2bin(buf[4]);
0213     dt->tm_mon  = bcd2bin(buf[5] & 0x1F) - 1;
0214     dt->tm_year = bcd2bin(buf[6]) + 100; /* year offset from 1900 */
0215
0216     return 0;
0217 }
0218
0219 static int ds1343_set_time(struct device *dev, struct rtc_time *dt)
0220 {
0221     struct ds1343_priv *priv = dev_get_drvdata(dev);
0222     u8 buf[7];
0223
0224     buf[0] = bin2bcd(dt->tm_sec);
0225     buf[1] = bin2bcd(dt->tm_min);
0226     buf[2] = bin2bcd(dt->tm_hour) & 0x3F;
0227     buf[3] = bin2bcd(dt->tm_wday + 1);
0228     buf[4] = bin2bcd(dt->tm_mday);
0229     buf[5] = bin2bcd(dt->tm_mon + 1);
0230     buf[6] = bin2bcd(dt->tm_year - 100);
0231
0232     return regmap_bulk_write(priv->map, DS1343_SECONDS_REG,
0233                  buf, sizeof(buf));
0234 }
0235
0236 static int ds1343_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0237 {
0238     struct ds1343_priv *priv = dev_get_drvdata(dev);
0239     unsigned char buf[4];
0240     unsigned int val;
0241     int res;
0242
0243     if (priv->irq <= 0)
0244         return -EINVAL;
0245
0246     res = regmap_read(priv->map, DS1343_STATUS_REG, &val);
0247     if (res)
0248         return res;
0249
0250     alarm->pending = !!(val & DS1343_IRQF0);
0251
0252     res = regmap_read(priv->map, DS1343_CONTROL_REG, &val);
0253     if (res)
0254         return res;
0255     alarm->enabled = !!(val & DS1343_A0IE);
0256
0257     res = regmap_bulk_read(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
0258     if (res)
0259         return res;
0260
0261     alarm->time.tm_sec = bcd2bin(buf[0]) & 0x7f;
0262     alarm->time.tm_min = bcd2bin(buf[1]) & 0x7f;
0263     alarm->time.tm_hour = bcd2bin(buf[2]) & 0x3f;
0264     alarm->time.tm_mday = bcd2bin(buf[3]) & 0x3f;
0265
0266     return 0;
0267 }
0268
0269 static int ds1343_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0270 {
0271     struct ds1343_priv *priv = dev_get_drvdata(dev);
0272     unsigned char buf[4];
0273     int res = 0;
0274
0275     if (priv->irq <= 0)
0276         return -EINVAL;
0277
0278     res = regmap_update_bits(priv->map, DS1343_CONTROL_REG, DS1343_A0IE, 0);
0279     if (res)
0280         return res;
0281
0282     buf[0] = bin2bcd(alarm->time.tm_sec);
0283     buf[1] = bin2bcd(alarm->time.tm_min);
0284     buf[2] = bin2bcd(alarm->time.tm_hour);
0285     buf[3] = bin2bcd(alarm->time.tm_mday);
0286
0287     res = regmap_bulk_write(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
0288     if (res)
0289         return res;
0290
0291     if (alarm->enabled)
0292         res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
0293                      DS1343_A0IE, DS1343_A0IE);
0294
0295     return res;
0296 }
0297
0298 static int ds1343_alarm_irq_enable(struct device *dev, unsigned int enabled)
0299 {
0300     struct ds1343_priv *priv = dev_get_drvdata(dev);
0301
0302     if (priv->irq <= 0)
0303         return -EINVAL;
0304
0305     return regmap_update_bits(priv->map, DS1343_CONTROL_REG,
0306                   DS1343_A0IE, enabled ? DS1343_A0IE : 0);
0307 }
0308
0309 static irqreturn_t ds1343_thread(int irq, void *dev_id)
0310 {
0311     struct ds1343_priv *priv = dev_id;
0312     unsigned int stat;
0313     int res = 0;
0314
0315     rtc_lock(priv->rtc);
0316
0317     res = regmap_read(priv->map, DS1343_STATUS_REG, &stat);
0318     if (res)
0319         goto out;
0320
0321     if (stat & DS1343_IRQF0) {
0322         stat &= ~DS1343_IRQF0;
0323         regmap_write(priv->map, DS1343_STATUS_REG, stat);
0324
0325         rtc_update_irq(priv->rtc, 1, RTC_AF | RTC_IRQF);
0326
0327         regmap_update_bits(priv->map, DS1343_CONTROL_REG,
0328                    DS1343_A0IE, 0);
0329     }
0330
0331 out:
0332     rtc_unlock(priv->rtc);
0333     return IRQ_HANDLED;
0334 }
0335
0336 static const struct rtc_class_ops ds1343_rtc_ops = {
0337     .read_time  = ds1343_read_time,
0338     .set_time   = ds1343_set_time,
0339     .read_alarm = ds1343_read_alarm,
0340     .set_alarm  = ds1343_set_alarm,
0341     .alarm_irq_enable = ds1343_alarm_irq_enable,
0342 };
0343
0344 static int ds1343_probe(struct spi_device *spi)
0345 {
0346     struct ds1343_priv *priv;
0347     struct regmap_config config = { .reg_bits = 8, .val_bits = 8,
0348                     .write_flag_mask = 0x80, };
0349     unsigned int data;
0350     int res;
0351     struct nvmem_config nvmem_cfg = {
0352         .name = "ds1343-",
0353         .word_size = 1,
0354         .stride = 1,
0355         .size = DS1343_NVRAM_LEN,
0356         .reg_read = ds1343_nvram_read,
0357         .reg_write = ds1343_nvram_write,
0358     };
0359
0360     priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL);
0361     if (!priv)
0362         return -ENOMEM;
0363
0364     /* RTC DS1347 works in spi mode 3 and
0365      * its chip select is active high. Active high should be defined as
0366      * "inverse polarity" as GPIO-based chip selects can be logically
0367      * active high but inverted by the GPIO library.
0368      */
0369     spi->mode |= SPI_MODE_3;
0370     spi->mode ^= SPI_CS_HIGH;
0371     spi->bits_per_word = 8;
0372     res = spi_setup(spi);
0373     if (res)
0374         return res;
0375
0376     spi_set_drvdata(spi, priv);
0377
0378     priv->map = devm_regmap_init_spi(spi, &config);
0379
0380     if (IS_ERR(priv->map)) {
0381         dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n");
0382         return PTR_ERR(priv->map);
0383     }
0384
0385     res = regmap_read(priv->map, DS1343_SECONDS_REG, &data);
0386     if (res)
0387         return res;
0388
0389     regmap_read(priv->map, DS1343_CONTROL_REG, &data);
0390     data |= DS1343_INTCN;
0391     data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE);
0392     regmap_write(priv->map, DS1343_CONTROL_REG, data);
0393
0394     regmap_read(priv->map, DS1343_STATUS_REG, &data);
0395     data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0);
0396     regmap_write(priv->map, DS1343_STATUS_REG, data);
0397
0398     priv->rtc = devm_rtc_allocate_device(&spi->dev);
0399     if (IS_ERR(priv->rtc))
0400         return PTR_ERR(priv->rtc);
0401
0402     priv->rtc->ops = &ds1343_rtc_ops;
0403     priv->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0404     priv->rtc->range_max = RTC_TIMESTAMP_END_2099;
0405
0406     res = rtc_add_group(priv->rtc, &ds1343_attr_group);
0407     if (res)
0408         dev_err(&spi->dev,
0409             "unable to create sysfs entries for rtc ds1343\n");
0410
0411     res = devm_rtc_register_device(priv->rtc);
0412     if (res)
0413         return res;
0414
0415     nvmem_cfg.priv = priv;
0416     devm_rtc_nvmem_register(priv->rtc, &nvmem_cfg);
0417
0418     priv->irq = spi->irq;
0419
0420     if (priv->irq >= 0) {
0421         res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
0422                         ds1343_thread, IRQF_ONESHOT,
0423                         "ds1343", priv);
0424         if (res) {
0425             priv->irq = -1;
0426             dev_err(&spi->dev,
0427                 "unable to request irq for rtc ds1343\n");
0428         } else {
0429             device_init_wakeup(&spi->dev, true);
0430             dev_pm_set_wake_irq(&spi->dev, spi->irq);
0431         }
0432     }
0433
0434     return 0;
0435 }
0436
0437 static void ds1343_remove(struct spi_device *spi)
0438 {
0439     dev_pm_clear_wake_irq(&spi->dev);
0440 }
0441
0442 #ifdef CONFIG_PM_SLEEP
0443
0444 static int ds1343_suspend(struct device *dev)
0445 {
0446     struct spi_device *spi = to_spi_device(dev);
0447
0448     if (spi->irq >= 0 && device_may_wakeup(dev))
0449         enable_irq_wake(spi->irq);
0450
0451     return 0;
0452 }
0453
0454 static int ds1343_resume(struct device *dev)
0455 {
0456     struct spi_device *spi = to_spi_device(dev);
0457
0458     if (spi->irq >= 0 && device_may_wakeup(dev))
0459         disable_irq_wake(spi->irq);
0460
0461     return 0;
0462 }
0463
0464 #endif
0465
0466 static SIMPLE_DEV_PM_OPS(ds1343_pm, ds1343_suspend, ds1343_resume);
0467
0468 static struct spi_driver ds1343_driver = {
0469     .driver = {
0470         .name = "ds1343",
0471         .pm = &ds1343_pm,
0472     },
0473     .probe = ds1343_probe,
0474     .remove = ds1343_remove,
0475     .id_table = ds1343_id,
0476 };
0477
0478 module_spi_driver(ds1343_driver);
0479
0480 MODULE_DESCRIPTION("DS1343 RTC SPI Driver");
0481 MODULE_AUTHOR("Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>,"
0482         "Ankur Srivastava <sankurece@gmail.com>");
0483 MODULE_LICENSE("GPL v2");