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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
0004  *
0005  *  Copyright (C) 2005 James Chapman (ds1337 core)
0006  *  Copyright (C) 2006 David Brownell
0007  *  Copyright (C) 2009 Matthias Fuchs (rx8025 support)
0008  *  Copyright (C) 2012 Bertrand Achard (nvram access fixes)
0009  */
0010 
0011 #include <linux/bcd.h>
0012 #include <linux/i2c.h>
0013 #include <linux/init.h>
0014 #include <linux/mod_devicetable.h>
0015 #include <linux/module.h>
0016 #include <linux/property.h>
0017 #include <linux/rtc/ds1307.h>
0018 #include <linux/rtc.h>
0019 #include <linux/slab.h>
0020 #include <linux/string.h>
0021 #include <linux/hwmon.h>
0022 #include <linux/hwmon-sysfs.h>
0023 #include <linux/clk-provider.h>
0024 #include <linux/regmap.h>
0025 #include <linux/watchdog.h>
0026 
0027 /*
0028  * We can't determine type by probing, but if we expect pre-Linux code
0029  * to have set the chip up as a clock (turning on the oscillator and
0030  * setting the date and time), Linux can ignore the non-clock features.
0031  * That's a natural job for a factory or repair bench.
0032  */
0033 enum ds_type {
0034     unknown_ds_type, /* always first and 0 */
0035     ds_1307,
0036     ds_1308,
0037     ds_1337,
0038     ds_1338,
0039     ds_1339,
0040     ds_1340,
0041     ds_1341,
0042     ds_1388,
0043     ds_3231,
0044     m41t0,
0045     m41t00,
0046     m41t11,
0047     mcp794xx,
0048     rx_8025,
0049     rx_8130,
0050     last_ds_type /* always last */
0051     /* rs5c372 too?  different address... */
0052 };
0053 
0054 /* RTC registers don't differ much, except for the century flag */
0055 #define DS1307_REG_SECS     0x00    /* 00-59 */
0056 #   define DS1307_BIT_CH        0x80
0057 #   define DS1340_BIT_nEOSC     0x80
0058 #   define MCP794XX_BIT_ST      0x80
0059 #define DS1307_REG_MIN      0x01    /* 00-59 */
0060 #   define M41T0_BIT_OF     0x80
0061 #define DS1307_REG_HOUR     0x02    /* 00-23, or 1-12{am,pm} */
0062 #   define DS1307_BIT_12HR      0x40    /* in REG_HOUR */
0063 #   define DS1307_BIT_PM        0x20    /* in REG_HOUR */
0064 #   define DS1340_BIT_CENTURY_EN    0x80    /* in REG_HOUR */
0065 #   define DS1340_BIT_CENTURY   0x40    /* in REG_HOUR */
0066 #define DS1307_REG_WDAY     0x03    /* 01-07 */
0067 #   define MCP794XX_BIT_VBATEN  0x08
0068 #define DS1307_REG_MDAY     0x04    /* 01-31 */
0069 #define DS1307_REG_MONTH    0x05    /* 01-12 */
0070 #   define DS1337_BIT_CENTURY   0x80    /* in REG_MONTH */
0071 #define DS1307_REG_YEAR     0x06    /* 00-99 */
0072 
0073 /*
0074  * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
0075  * start at 7, and they differ a LOT. Only control and status matter for
0076  * basic RTC date and time functionality; be careful using them.
0077  */
0078 #define DS1307_REG_CONTROL  0x07        /* or ds1338 */
0079 #   define DS1307_BIT_OUT       0x80
0080 #   define DS1338_BIT_OSF       0x20
0081 #   define DS1307_BIT_SQWE      0x10
0082 #   define DS1307_BIT_RS1       0x02
0083 #   define DS1307_BIT_RS0       0x01
0084 #define DS1337_REG_CONTROL  0x0e
0085 #   define DS1337_BIT_nEOSC     0x80
0086 #   define DS1339_BIT_BBSQI     0x20
0087 #   define DS3231_BIT_BBSQW     0x40 /* same as BBSQI */
0088 #   define DS1337_BIT_RS2       0x10
0089 #   define DS1337_BIT_RS1       0x08
0090 #   define DS1337_BIT_INTCN     0x04
0091 #   define DS1337_BIT_A2IE      0x02
0092 #   define DS1337_BIT_A1IE      0x01
0093 #define DS1340_REG_CONTROL  0x07
0094 #   define DS1340_BIT_OUT       0x80
0095 #   define DS1340_BIT_FT        0x40
0096 #   define DS1340_BIT_CALIB_SIGN    0x20
0097 #   define DS1340_M_CALIBRATION 0x1f
0098 #define DS1340_REG_FLAG     0x09
0099 #   define DS1340_BIT_OSF       0x80
0100 #define DS1337_REG_STATUS   0x0f
0101 #   define DS1337_BIT_OSF       0x80
0102 #   define DS3231_BIT_EN32KHZ   0x08
0103 #   define DS1337_BIT_A2I       0x02
0104 #   define DS1337_BIT_A1I       0x01
0105 #define DS1339_REG_ALARM1_SECS  0x07
0106 
0107 #define DS13XX_TRICKLE_CHARGER_MAGIC    0xa0
0108 
0109 #define RX8025_REG_CTRL1    0x0e
0110 #   define RX8025_BIT_2412      0x20
0111 #define RX8025_REG_CTRL2    0x0f
0112 #   define RX8025_BIT_PON       0x10
0113 #   define RX8025_BIT_VDET      0x40
0114 #   define RX8025_BIT_XST       0x20
0115 
0116 #define RX8130_REG_ALARM_MIN        0x17
0117 #define RX8130_REG_ALARM_HOUR       0x18
0118 #define RX8130_REG_ALARM_WEEK_OR_DAY    0x19
0119 #define RX8130_REG_EXTENSION        0x1c
0120 #define RX8130_REG_EXTENSION_WADA   BIT(3)
0121 #define RX8130_REG_FLAG         0x1d
0122 #define RX8130_REG_FLAG_VLF     BIT(1)
0123 #define RX8130_REG_FLAG_AF      BIT(3)
0124 #define RX8130_REG_CONTROL0     0x1e
0125 #define RX8130_REG_CONTROL0_AIE     BIT(3)
0126 #define RX8130_REG_CONTROL1     0x1f
0127 #define RX8130_REG_CONTROL1_INIEN   BIT(4)
0128 #define RX8130_REG_CONTROL1_CHGEN   BIT(5)
0129 
0130 #define MCP794XX_REG_CONTROL        0x07
0131 #   define MCP794XX_BIT_ALM0_EN 0x10
0132 #   define MCP794XX_BIT_ALM1_EN 0x20
0133 #define MCP794XX_REG_ALARM0_BASE    0x0a
0134 #define MCP794XX_REG_ALARM0_CTRL    0x0d
0135 #define MCP794XX_REG_ALARM1_BASE    0x11
0136 #define MCP794XX_REG_ALARM1_CTRL    0x14
0137 #   define MCP794XX_BIT_ALMX_IF BIT(3)
0138 #   define MCP794XX_BIT_ALMX_C0 BIT(4)
0139 #   define MCP794XX_BIT_ALMX_C1 BIT(5)
0140 #   define MCP794XX_BIT_ALMX_C2 BIT(6)
0141 #   define MCP794XX_BIT_ALMX_POL    BIT(7)
0142 #   define MCP794XX_MSK_ALMX_MATCH  (MCP794XX_BIT_ALMX_C0 | \
0143                      MCP794XX_BIT_ALMX_C1 | \
0144                      MCP794XX_BIT_ALMX_C2)
0145 
0146 #define M41TXX_REG_CONTROL  0x07
0147 #   define M41TXX_BIT_OUT       BIT(7)
0148 #   define M41TXX_BIT_FT        BIT(6)
0149 #   define M41TXX_BIT_CALIB_SIGN    BIT(5)
0150 #   define M41TXX_M_CALIBRATION GENMASK(4, 0)
0151 
0152 #define DS1388_REG_WDOG_HUN_SECS    0x08
0153 #define DS1388_REG_WDOG_SECS        0x09
0154 #define DS1388_REG_FLAG         0x0b
0155 #   define DS1388_BIT_WF        BIT(6)
0156 #   define DS1388_BIT_OSF       BIT(7)
0157 #define DS1388_REG_CONTROL      0x0c
0158 #   define DS1388_BIT_RST       BIT(0)
0159 #   define DS1388_BIT_WDE       BIT(1)
0160 #   define DS1388_BIT_nEOSC     BIT(7)
0161 
0162 /* negative offset step is -2.034ppm */
0163 #define M41TXX_NEG_OFFSET_STEP_PPB  2034
0164 /* positive offset step is +4.068ppm */
0165 #define M41TXX_POS_OFFSET_STEP_PPB  4068
0166 /* Min and max values supported with 'offset' interface by M41TXX */
0167 #define M41TXX_MIN_OFFSET   ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
0168 #define M41TXX_MAX_OFFSET   ((31) * M41TXX_POS_OFFSET_STEP_PPB)
0169 
0170 struct ds1307 {
0171     enum ds_type        type;
0172     struct device       *dev;
0173     struct regmap       *regmap;
0174     const char      *name;
0175     struct rtc_device   *rtc;
0176 #ifdef CONFIG_COMMON_CLK
0177     struct clk_hw       clks[2];
0178 #endif
0179 };
0180 
0181 struct chip_desc {
0182     unsigned        alarm:1;
0183     u16         nvram_offset;
0184     u16         nvram_size;
0185     u8          offset; /* register's offset */
0186     u8          century_reg;
0187     u8          century_enable_bit;
0188     u8          century_bit;
0189     u8          bbsqi_bit;
0190     irq_handler_t       irq_handler;
0191     const struct rtc_class_ops *rtc_ops;
0192     u16         trickle_charger_reg;
0193     u8          (*do_trickle_setup)(struct ds1307 *, u32,
0194                             bool);
0195     /* Does the RTC require trickle-resistor-ohms to select the value of
0196      * the resistor between Vcc and Vbackup?
0197      */
0198     bool            requires_trickle_resistor;
0199     /* Some RTC's batteries and supercaps were charged by default, others
0200      * allow charging but were not configured previously to do so.
0201      * Remember this behavior to stay backwards compatible.
0202      */
0203     bool            charge_default;
0204 };
0205 
0206 static const struct chip_desc chips[last_ds_type];
0207 
0208 static int ds1307_get_time(struct device *dev, struct rtc_time *t)
0209 {
0210     struct ds1307   *ds1307 = dev_get_drvdata(dev);
0211     int     tmp, ret;
0212     const struct chip_desc *chip = &chips[ds1307->type];
0213     u8 regs[7];
0214 
0215     if (ds1307->type == rx_8130) {
0216         unsigned int regflag;
0217         ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, &regflag);
0218         if (ret) {
0219             dev_err(dev, "%s error %d\n", "read", ret);
0220             return ret;
0221         }
0222 
0223         if (regflag & RX8130_REG_FLAG_VLF) {
0224             dev_warn_once(dev, "oscillator failed, set time!\n");
0225             return -EINVAL;
0226         }
0227     }
0228 
0229     /* read the RTC date and time registers all at once */
0230     ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
0231                    sizeof(regs));
0232     if (ret) {
0233         dev_err(dev, "%s error %d\n", "read", ret);
0234         return ret;
0235     }
0236 
0237     dev_dbg(dev, "%s: %7ph\n", "read", regs);
0238 
0239     /* if oscillator fail bit is set, no data can be trusted */
0240     if (ds1307->type == m41t0 &&
0241         regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
0242         dev_warn_once(dev, "oscillator failed, set time!\n");
0243         return -EINVAL;
0244     }
0245 
0246     tmp = regs[DS1307_REG_SECS];
0247     switch (ds1307->type) {
0248     case ds_1307:
0249     case m41t0:
0250     case m41t00:
0251     case m41t11:
0252         if (tmp & DS1307_BIT_CH)
0253             return -EINVAL;
0254         break;
0255     case ds_1308:
0256     case ds_1338:
0257         if (tmp & DS1307_BIT_CH)
0258             return -EINVAL;
0259 
0260         ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
0261         if (ret)
0262             return ret;
0263         if (tmp & DS1338_BIT_OSF)
0264             return -EINVAL;
0265         break;
0266     case ds_1340:
0267         if (tmp & DS1340_BIT_nEOSC)
0268             return -EINVAL;
0269 
0270         ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
0271         if (ret)
0272             return ret;
0273         if (tmp & DS1340_BIT_OSF)
0274             return -EINVAL;
0275         break;
0276     case ds_1388:
0277         ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
0278         if (ret)
0279             return ret;
0280         if (tmp & DS1388_BIT_OSF)
0281             return -EINVAL;
0282         break;
0283     case mcp794xx:
0284         if (!(tmp & MCP794XX_BIT_ST))
0285             return -EINVAL;
0286 
0287         break;
0288     default:
0289         break;
0290     }
0291 
0292     t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
0293     t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
0294     tmp = regs[DS1307_REG_HOUR] & 0x3f;
0295     t->tm_hour = bcd2bin(tmp);
0296     /* rx8130 is bit position, not BCD */
0297     if (ds1307->type == rx_8130)
0298         t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
0299     else
0300         t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
0301     t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
0302     tmp = regs[DS1307_REG_MONTH] & 0x1f;
0303     t->tm_mon = bcd2bin(tmp) - 1;
0304     t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
0305 
0306     if (regs[chip->century_reg] & chip->century_bit &&
0307         IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
0308         t->tm_year += 100;
0309 
0310     dev_dbg(dev, "%s secs=%d, mins=%d, "
0311         "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
0312         "read", t->tm_sec, t->tm_min,
0313         t->tm_hour, t->tm_mday,
0314         t->tm_mon, t->tm_year, t->tm_wday);
0315 
0316     return 0;
0317 }
0318 
0319 static int ds1307_set_time(struct device *dev, struct rtc_time *t)
0320 {
0321     struct ds1307   *ds1307 = dev_get_drvdata(dev);
0322     const struct chip_desc *chip = &chips[ds1307->type];
0323     int     result;
0324     int     tmp;
0325     u8      regs[7];
0326 
0327     dev_dbg(dev, "%s secs=%d, mins=%d, "
0328         "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
0329         "write", t->tm_sec, t->tm_min,
0330         t->tm_hour, t->tm_mday,
0331         t->tm_mon, t->tm_year, t->tm_wday);
0332 
0333     if (t->tm_year < 100)
0334         return -EINVAL;
0335 
0336 #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
0337     if (t->tm_year > (chip->century_bit ? 299 : 199))
0338         return -EINVAL;
0339 #else
0340     if (t->tm_year > 199)
0341         return -EINVAL;
0342 #endif
0343 
0344     regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
0345     regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
0346     regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
0347     /* rx8130 is bit position, not BCD */
0348     if (ds1307->type == rx_8130)
0349         regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
0350     else
0351         regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
0352     regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
0353     regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
0354 
0355     /* assume 20YY not 19YY */
0356     tmp = t->tm_year - 100;
0357     regs[DS1307_REG_YEAR] = bin2bcd(tmp);
0358 
0359     if (chip->century_enable_bit)
0360         regs[chip->century_reg] |= chip->century_enable_bit;
0361     if (t->tm_year > 199 && chip->century_bit)
0362         regs[chip->century_reg] |= chip->century_bit;
0363 
0364     switch (ds1307->type) {
0365     case ds_1308:
0366     case ds_1338:
0367         regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
0368                    DS1338_BIT_OSF, 0);
0369         break;
0370     case ds_1340:
0371         regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
0372                    DS1340_BIT_OSF, 0);
0373         break;
0374     case ds_1388:
0375         regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
0376                    DS1388_BIT_OSF, 0);
0377         break;
0378     case mcp794xx:
0379         /*
0380          * these bits were cleared when preparing the date/time
0381          * values and need to be set again before writing the
0382          * regsfer out to the device.
0383          */
0384         regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
0385         regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
0386         break;
0387     default:
0388         break;
0389     }
0390 
0391     dev_dbg(dev, "%s: %7ph\n", "write", regs);
0392 
0393     result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
0394                    sizeof(regs));
0395     if (result) {
0396         dev_err(dev, "%s error %d\n", "write", result);
0397         return result;
0398     }
0399 
0400     if (ds1307->type == rx_8130) {
0401         /* clear Voltage Loss Flag as data is available now */
0402         result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
0403                       ~(u8)RX8130_REG_FLAG_VLF);
0404         if (result) {
0405             dev_err(dev, "%s error %d\n", "write", result);
0406             return result;
0407         }
0408     }
0409 
0410     return 0;
0411 }
0412 
0413 static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
0414 {
0415     struct ds1307       *ds1307 = dev_get_drvdata(dev);
0416     int         ret;
0417     u8          regs[9];
0418 
0419     /* read all ALARM1, ALARM2, and status registers at once */
0420     ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
0421                    regs, sizeof(regs));
0422     if (ret) {
0423         dev_err(dev, "%s error %d\n", "alarm read", ret);
0424         return ret;
0425     }
0426 
0427     dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
0428         &regs[0], &regs[4], &regs[7]);
0429 
0430     /*
0431      * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
0432      * and that all four fields are checked matches
0433      */
0434     t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
0435     t->time.tm_min = bcd2bin(regs[1] & 0x7f);
0436     t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
0437     t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
0438 
0439     /* ... and status */
0440     t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
0441     t->pending = !!(regs[8] & DS1337_BIT_A1I);
0442 
0443     dev_dbg(dev, "%s secs=%d, mins=%d, "
0444         "hours=%d, mday=%d, enabled=%d, pending=%d\n",
0445         "alarm read", t->time.tm_sec, t->time.tm_min,
0446         t->time.tm_hour, t->time.tm_mday,
0447         t->enabled, t->pending);
0448 
0449     return 0;
0450 }
0451 
0452 static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
0453 {
0454     struct ds1307       *ds1307 = dev_get_drvdata(dev);
0455     unsigned char       regs[9];
0456     u8          control, status;
0457     int         ret;
0458 
0459     dev_dbg(dev, "%s secs=%d, mins=%d, "
0460         "hours=%d, mday=%d, enabled=%d, pending=%d\n",
0461         "alarm set", t->time.tm_sec, t->time.tm_min,
0462         t->time.tm_hour, t->time.tm_mday,
0463         t->enabled, t->pending);
0464 
0465     /* read current status of both alarms and the chip */
0466     ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
0467                    sizeof(regs));
0468     if (ret) {
0469         dev_err(dev, "%s error %d\n", "alarm write", ret);
0470         return ret;
0471     }
0472     control = regs[7];
0473     status = regs[8];
0474 
0475     dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
0476         &regs[0], &regs[4], control, status);
0477 
0478     /* set ALARM1, using 24 hour and day-of-month modes */
0479     regs[0] = bin2bcd(t->time.tm_sec);
0480     regs[1] = bin2bcd(t->time.tm_min);
0481     regs[2] = bin2bcd(t->time.tm_hour);
0482     regs[3] = bin2bcd(t->time.tm_mday);
0483 
0484     /* set ALARM2 to non-garbage */
0485     regs[4] = 0;
0486     regs[5] = 0;
0487     regs[6] = 0;
0488 
0489     /* disable alarms */
0490     regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
0491     regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
0492 
0493     ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
0494                 sizeof(regs));
0495     if (ret) {
0496         dev_err(dev, "can't set alarm time\n");
0497         return ret;
0498     }
0499 
0500     /* optionally enable ALARM1 */
0501     if (t->enabled) {
0502         dev_dbg(dev, "alarm IRQ armed\n");
0503         regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
0504         regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
0505     }
0506 
0507     return 0;
0508 }
0509 
0510 static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
0511 {
0512     struct ds1307       *ds1307 = dev_get_drvdata(dev);
0513 
0514     return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
0515                   DS1337_BIT_A1IE,
0516                   enabled ? DS1337_BIT_A1IE : 0);
0517 }
0518 
0519 static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
0520 {
0521     u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
0522         DS1307_TRICKLE_CHARGER_NO_DIODE;
0523 
0524     setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
0525 
0526     switch (ohms) {
0527     case 250:
0528         setup |= DS1307_TRICKLE_CHARGER_250_OHM;
0529         break;
0530     case 2000:
0531         setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
0532         break;
0533     case 4000:
0534         setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
0535         break;
0536     default:
0537         dev_warn(ds1307->dev,
0538              "Unsupported ohm value %u in dt\n", ohms);
0539         return 0;
0540     }
0541     return setup;
0542 }
0543 
0544 static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
0545 {
0546     /* make sure that the backup battery is enabled */
0547     u8 setup = RX8130_REG_CONTROL1_INIEN;
0548     if (diode)
0549         setup |= RX8130_REG_CONTROL1_CHGEN;
0550 
0551     return setup;
0552 }
0553 
0554 static irqreturn_t rx8130_irq(int irq, void *dev_id)
0555 {
0556     struct ds1307           *ds1307 = dev_id;
0557     u8 ctl[3];
0558     int ret;
0559 
0560     rtc_lock(ds1307->rtc);
0561 
0562     /* Read control registers. */
0563     ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
0564                    sizeof(ctl));
0565     if (ret < 0)
0566         goto out;
0567     if (!(ctl[1] & RX8130_REG_FLAG_AF))
0568         goto out;
0569     ctl[1] &= ~RX8130_REG_FLAG_AF;
0570     ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
0571 
0572     ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
0573                 sizeof(ctl));
0574     if (ret < 0)
0575         goto out;
0576 
0577     rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
0578 
0579 out:
0580     rtc_unlock(ds1307->rtc);
0581 
0582     return IRQ_HANDLED;
0583 }
0584 
0585 static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
0586 {
0587     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0588     u8 ald[3], ctl[3];
0589     int ret;
0590 
0591     /* Read alarm registers. */
0592     ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
0593                    sizeof(ald));
0594     if (ret < 0)
0595         return ret;
0596 
0597     /* Read control registers. */
0598     ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
0599                    sizeof(ctl));
0600     if (ret < 0)
0601         return ret;
0602 
0603     t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
0604     t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
0605 
0606     /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
0607     t->time.tm_sec = -1;
0608     t->time.tm_min = bcd2bin(ald[0] & 0x7f);
0609     t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
0610     t->time.tm_wday = -1;
0611     t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
0612     t->time.tm_mon = -1;
0613     t->time.tm_year = -1;
0614     t->time.tm_yday = -1;
0615     t->time.tm_isdst = -1;
0616 
0617     dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
0618         __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
0619         t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
0620 
0621     return 0;
0622 }
0623 
0624 static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
0625 {
0626     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0627     u8 ald[3], ctl[3];
0628     int ret;
0629 
0630     dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
0631         "enabled=%d pending=%d\n", __func__,
0632         t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
0633         t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
0634         t->enabled, t->pending);
0635 
0636     /* Read control registers. */
0637     ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
0638                    sizeof(ctl));
0639     if (ret < 0)
0640         return ret;
0641 
0642     ctl[0] &= RX8130_REG_EXTENSION_WADA;
0643     ctl[1] &= ~RX8130_REG_FLAG_AF;
0644     ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
0645 
0646     ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
0647                 sizeof(ctl));
0648     if (ret < 0)
0649         return ret;
0650 
0651     /* Hardware alarm precision is 1 minute! */
0652     ald[0] = bin2bcd(t->time.tm_min);
0653     ald[1] = bin2bcd(t->time.tm_hour);
0654     ald[2] = bin2bcd(t->time.tm_mday);
0655 
0656     ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
0657                 sizeof(ald));
0658     if (ret < 0)
0659         return ret;
0660 
0661     if (!t->enabled)
0662         return 0;
0663 
0664     ctl[2] |= RX8130_REG_CONTROL0_AIE;
0665 
0666     return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
0667 }
0668 
0669 static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
0670 {
0671     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0672     int ret, reg;
0673 
0674     ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, &reg);
0675     if (ret < 0)
0676         return ret;
0677 
0678     if (enabled)
0679         reg |= RX8130_REG_CONTROL0_AIE;
0680     else
0681         reg &= ~RX8130_REG_CONTROL0_AIE;
0682 
0683     return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
0684 }
0685 
0686 static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
0687 {
0688     struct ds1307           *ds1307 = dev_id;
0689     struct mutex            *lock = &ds1307->rtc->ops_lock;
0690     int reg, ret;
0691 
0692     mutex_lock(lock);
0693 
0694     /* Check and clear alarm 0 interrupt flag. */
0695     ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, &reg);
0696     if (ret)
0697         goto out;
0698     if (!(reg & MCP794XX_BIT_ALMX_IF))
0699         goto out;
0700     reg &= ~MCP794XX_BIT_ALMX_IF;
0701     ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
0702     if (ret)
0703         goto out;
0704 
0705     /* Disable alarm 0. */
0706     ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
0707                  MCP794XX_BIT_ALM0_EN, 0);
0708     if (ret)
0709         goto out;
0710 
0711     rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
0712 
0713 out:
0714     mutex_unlock(lock);
0715 
0716     return IRQ_HANDLED;
0717 }
0718 
0719 static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
0720 {
0721     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0722     u8 regs[10];
0723     int ret;
0724 
0725     /* Read control and alarm 0 registers. */
0726     ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
0727                    sizeof(regs));
0728     if (ret)
0729         return ret;
0730 
0731     t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
0732 
0733     /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
0734     t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
0735     t->time.tm_min = bcd2bin(regs[4] & 0x7f);
0736     t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
0737     t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
0738     t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
0739     t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
0740     t->time.tm_year = -1;
0741     t->time.tm_yday = -1;
0742     t->time.tm_isdst = -1;
0743 
0744     dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
0745         "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
0746         t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
0747         t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
0748         !!(regs[6] & MCP794XX_BIT_ALMX_POL),
0749         !!(regs[6] & MCP794XX_BIT_ALMX_IF),
0750         (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
0751 
0752     return 0;
0753 }
0754 
0755 /*
0756  * We may have a random RTC weekday, therefore calculate alarm weekday based
0757  * on current weekday we read from the RTC timekeeping regs
0758  */
0759 static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
0760 {
0761     struct rtc_time tm_now;
0762     int days_now, days_alarm, ret;
0763 
0764     ret = ds1307_get_time(dev, &tm_now);
0765     if (ret)
0766         return ret;
0767 
0768     days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
0769     days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
0770 
0771     return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
0772 }
0773 
0774 static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
0775 {
0776     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0777     unsigned char regs[10];
0778     int wday, ret;
0779 
0780     wday = mcp794xx_alm_weekday(dev, &t->time);
0781     if (wday < 0)
0782         return wday;
0783 
0784     dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
0785         "enabled=%d pending=%d\n", __func__,
0786         t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
0787         t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
0788         t->enabled, t->pending);
0789 
0790     /* Read control and alarm 0 registers. */
0791     ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
0792                    sizeof(regs));
0793     if (ret)
0794         return ret;
0795 
0796     /* Set alarm 0, using 24-hour and day-of-month modes. */
0797     regs[3] = bin2bcd(t->time.tm_sec);
0798     regs[4] = bin2bcd(t->time.tm_min);
0799     regs[5] = bin2bcd(t->time.tm_hour);
0800     regs[6] = wday;
0801     regs[7] = bin2bcd(t->time.tm_mday);
0802     regs[8] = bin2bcd(t->time.tm_mon + 1);
0803 
0804     /* Clear the alarm 0 interrupt flag. */
0805     regs[6] &= ~MCP794XX_BIT_ALMX_IF;
0806     /* Set alarm match: second, minute, hour, day, date, month. */
0807     regs[6] |= MCP794XX_MSK_ALMX_MATCH;
0808     /* Disable interrupt. We will not enable until completely programmed */
0809     regs[0] &= ~MCP794XX_BIT_ALM0_EN;
0810 
0811     ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
0812                 sizeof(regs));
0813     if (ret)
0814         return ret;
0815 
0816     if (!t->enabled)
0817         return 0;
0818     regs[0] |= MCP794XX_BIT_ALM0_EN;
0819     return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
0820 }
0821 
0822 static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
0823 {
0824     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0825 
0826     return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
0827                   MCP794XX_BIT_ALM0_EN,
0828                   enabled ? MCP794XX_BIT_ALM0_EN : 0);
0829 }
0830 
0831 static int m41txx_rtc_read_offset(struct device *dev, long *offset)
0832 {
0833     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0834     unsigned int ctrl_reg;
0835     u8 val;
0836 
0837     regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
0838 
0839     val = ctrl_reg & M41TXX_M_CALIBRATION;
0840 
0841     /* check if positive */
0842     if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
0843         *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
0844     else
0845         *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
0846 
0847     return 0;
0848 }
0849 
0850 static int m41txx_rtc_set_offset(struct device *dev, long offset)
0851 {
0852     struct ds1307 *ds1307 = dev_get_drvdata(dev);
0853     unsigned int ctrl_reg;
0854 
0855     if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
0856         return -ERANGE;
0857 
0858     if (offset >= 0) {
0859         ctrl_reg = DIV_ROUND_CLOSEST(offset,
0860                          M41TXX_POS_OFFSET_STEP_PPB);
0861         ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
0862     } else {
0863         ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
0864                          M41TXX_NEG_OFFSET_STEP_PPB);
0865     }
0866 
0867     return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
0868                   M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
0869                   ctrl_reg);
0870 }
0871 
0872 #ifdef CONFIG_WATCHDOG_CORE
0873 static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
0874 {
0875     struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
0876     u8 regs[2];
0877     int ret;
0878 
0879     ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
0880                  DS1388_BIT_WF, 0);
0881     if (ret)
0882         return ret;
0883 
0884     ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
0885                  DS1388_BIT_WDE | DS1388_BIT_RST, 0);
0886     if (ret)
0887         return ret;
0888 
0889     /*
0890      * watchdog timeouts are measured in seconds. So ignore hundredths of
0891      * seconds field.
0892      */
0893     regs[0] = 0;
0894     regs[1] = bin2bcd(wdt_dev->timeout);
0895 
0896     ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
0897                 sizeof(regs));
0898     if (ret)
0899         return ret;
0900 
0901     return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
0902                   DS1388_BIT_WDE | DS1388_BIT_RST,
0903                   DS1388_BIT_WDE | DS1388_BIT_RST);
0904 }
0905 
0906 static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
0907 {
0908     struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
0909 
0910     return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
0911                   DS1388_BIT_WDE | DS1388_BIT_RST, 0);
0912 }
0913 
0914 static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
0915 {
0916     struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
0917     u8 regs[2];
0918 
0919     return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
0920                 sizeof(regs));
0921 }
0922 
0923 static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
0924                   unsigned int val)
0925 {
0926     struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
0927     u8 regs[2];
0928 
0929     wdt_dev->timeout = val;
0930     regs[0] = 0;
0931     regs[1] = bin2bcd(wdt_dev->timeout);
0932 
0933     return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
0934                  sizeof(regs));
0935 }
0936 #endif
0937 
0938 static const struct rtc_class_ops rx8130_rtc_ops = {
0939     .read_time      = ds1307_get_time,
0940     .set_time       = ds1307_set_time,
0941     .read_alarm     = rx8130_read_alarm,
0942     .set_alarm      = rx8130_set_alarm,
0943     .alarm_irq_enable = rx8130_alarm_irq_enable,
0944 };
0945 
0946 static const struct rtc_class_ops mcp794xx_rtc_ops = {
0947     .read_time      = ds1307_get_time,
0948     .set_time       = ds1307_set_time,
0949     .read_alarm     = mcp794xx_read_alarm,
0950     .set_alarm      = mcp794xx_set_alarm,
0951     .alarm_irq_enable = mcp794xx_alarm_irq_enable,
0952 };
0953 
0954 static const struct rtc_class_ops m41txx_rtc_ops = {
0955     .read_time      = ds1307_get_time,
0956     .set_time       = ds1307_set_time,
0957     .read_alarm = ds1337_read_alarm,
0958     .set_alarm  = ds1337_set_alarm,
0959     .alarm_irq_enable = ds1307_alarm_irq_enable,
0960     .read_offset    = m41txx_rtc_read_offset,
0961     .set_offset = m41txx_rtc_set_offset,
0962 };
0963 
0964 static const struct chip_desc chips[last_ds_type] = {
0965     [ds_1307] = {
0966         .nvram_offset   = 8,
0967         .nvram_size = 56,
0968     },
0969     [ds_1308] = {
0970         .nvram_offset   = 8,
0971         .nvram_size = 56,
0972     },
0973     [ds_1337] = {
0974         .alarm      = 1,
0975         .century_reg    = DS1307_REG_MONTH,
0976         .century_bit    = DS1337_BIT_CENTURY,
0977     },
0978     [ds_1338] = {
0979         .nvram_offset   = 8,
0980         .nvram_size = 56,
0981     },
0982     [ds_1339] = {
0983         .alarm      = 1,
0984         .century_reg    = DS1307_REG_MONTH,
0985         .century_bit    = DS1337_BIT_CENTURY,
0986         .bbsqi_bit  = DS1339_BIT_BBSQI,
0987         .trickle_charger_reg = 0x10,
0988         .do_trickle_setup = &do_trickle_setup_ds1339,
0989         .requires_trickle_resistor = true,
0990         .charge_default = true,
0991     },
0992     [ds_1340] = {
0993         .century_reg    = DS1307_REG_HOUR,
0994         .century_enable_bit = DS1340_BIT_CENTURY_EN,
0995         .century_bit    = DS1340_BIT_CENTURY,
0996         .do_trickle_setup = &do_trickle_setup_ds1339,
0997         .trickle_charger_reg = 0x08,
0998         .requires_trickle_resistor = true,
0999         .charge_default = true,
1000     },
1001     [ds_1341] = {
1002         .century_reg    = DS1307_REG_MONTH,
1003         .century_bit    = DS1337_BIT_CENTURY,
1004     },
1005     [ds_1388] = {
1006         .offset     = 1,
1007         .trickle_charger_reg = 0x0a,
1008     },
1009     [ds_3231] = {
1010         .alarm      = 1,
1011         .century_reg    = DS1307_REG_MONTH,
1012         .century_bit    = DS1337_BIT_CENTURY,
1013         .bbsqi_bit  = DS3231_BIT_BBSQW,
1014     },
1015     [rx_8130] = {
1016         .alarm      = 1,
1017         /* this is battery backed SRAM */
1018         .nvram_offset   = 0x20,
1019         .nvram_size = 4,    /* 32bit (4 word x 8 bit) */
1020         .offset     = 0x10,
1021         .irq_handler = rx8130_irq,
1022         .rtc_ops = &rx8130_rtc_ops,
1023         .trickle_charger_reg = RX8130_REG_CONTROL1,
1024         .do_trickle_setup = &do_trickle_setup_rx8130,
1025     },
1026     [m41t0] = {
1027         .rtc_ops    = &m41txx_rtc_ops,
1028     },
1029     [m41t00] = {
1030         .rtc_ops    = &m41txx_rtc_ops,
1031     },
1032     [m41t11] = {
1033         /* this is battery backed SRAM */
1034         .nvram_offset   = 8,
1035         .nvram_size = 56,
1036         .rtc_ops    = &m41txx_rtc_ops,
1037     },
1038     [mcp794xx] = {
1039         .alarm      = 1,
1040         /* this is battery backed SRAM */
1041         .nvram_offset   = 0x20,
1042         .nvram_size = 0x40,
1043         .irq_handler = mcp794xx_irq,
1044         .rtc_ops = &mcp794xx_rtc_ops,
1045     },
1046 };
1047 
1048 static const struct i2c_device_id ds1307_id[] = {
1049     { "ds1307", ds_1307 },
1050     { "ds1308", ds_1308 },
1051     { "ds1337", ds_1337 },
1052     { "ds1338", ds_1338 },
1053     { "ds1339", ds_1339 },
1054     { "ds1388", ds_1388 },
1055     { "ds1340", ds_1340 },
1056     { "ds1341", ds_1341 },
1057     { "ds3231", ds_3231 },
1058     { "m41t0", m41t0 },
1059     { "m41t00", m41t00 },
1060     { "m41t11", m41t11 },
1061     { "mcp7940x", mcp794xx },
1062     { "mcp7941x", mcp794xx },
1063     { "pt7c4338", ds_1307 },
1064     { "rx8025", rx_8025 },
1065     { "isl12057", ds_1337 },
1066     { "rx8130", rx_8130 },
1067     { }
1068 };
1069 MODULE_DEVICE_TABLE(i2c, ds1307_id);
1070 
1071 static const struct of_device_id ds1307_of_match[] = {
1072     {
1073         .compatible = "dallas,ds1307",
1074         .data = (void *)ds_1307
1075     },
1076     {
1077         .compatible = "dallas,ds1308",
1078         .data = (void *)ds_1308
1079     },
1080     {
1081         .compatible = "dallas,ds1337",
1082         .data = (void *)ds_1337
1083     },
1084     {
1085         .compatible = "dallas,ds1338",
1086         .data = (void *)ds_1338
1087     },
1088     {
1089         .compatible = "dallas,ds1339",
1090         .data = (void *)ds_1339
1091     },
1092     {
1093         .compatible = "dallas,ds1388",
1094         .data = (void *)ds_1388
1095     },
1096     {
1097         .compatible = "dallas,ds1340",
1098         .data = (void *)ds_1340
1099     },
1100     {
1101         .compatible = "dallas,ds1341",
1102         .data = (void *)ds_1341
1103     },
1104     {
1105         .compatible = "maxim,ds3231",
1106         .data = (void *)ds_3231
1107     },
1108     {
1109         .compatible = "st,m41t0",
1110         .data = (void *)m41t0
1111     },
1112     {
1113         .compatible = "st,m41t00",
1114         .data = (void *)m41t00
1115     },
1116     {
1117         .compatible = "st,m41t11",
1118         .data = (void *)m41t11
1119     },
1120     {
1121         .compatible = "microchip,mcp7940x",
1122         .data = (void *)mcp794xx
1123     },
1124     {
1125         .compatible = "microchip,mcp7941x",
1126         .data = (void *)mcp794xx
1127     },
1128     {
1129         .compatible = "pericom,pt7c4338",
1130         .data = (void *)ds_1307
1131     },
1132     {
1133         .compatible = "epson,rx8025",
1134         .data = (void *)rx_8025
1135     },
1136     {
1137         .compatible = "isil,isl12057",
1138         .data = (void *)ds_1337
1139     },
1140     {
1141         .compatible = "epson,rx8130",
1142         .data = (void *)rx_8130
1143     },
1144     { }
1145 };
1146 MODULE_DEVICE_TABLE(of, ds1307_of_match);
1147 
1148 /*
1149  * The ds1337 and ds1339 both have two alarms, but we only use the first
1150  * one (with a "seconds" field).  For ds1337 we expect nINTA is our alarm
1151  * signal; ds1339 chips have only one alarm signal.
1152  */
1153 static irqreturn_t ds1307_irq(int irq, void *dev_id)
1154 {
1155     struct ds1307       *ds1307 = dev_id;
1156     struct mutex        *lock = &ds1307->rtc->ops_lock;
1157     int         stat, ret;
1158 
1159     mutex_lock(lock);
1160     ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
1161     if (ret)
1162         goto out;
1163 
1164     if (stat & DS1337_BIT_A1I) {
1165         stat &= ~DS1337_BIT_A1I;
1166         regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
1167 
1168         ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1169                      DS1337_BIT_A1IE, 0);
1170         if (ret)
1171             goto out;
1172 
1173         rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
1174     }
1175 
1176 out:
1177     mutex_unlock(lock);
1178 
1179     return IRQ_HANDLED;
1180 }
1181 
1182 /*----------------------------------------------------------------------*/
1183 
1184 static const struct rtc_class_ops ds13xx_rtc_ops = {
1185     .read_time  = ds1307_get_time,
1186     .set_time   = ds1307_set_time,
1187     .read_alarm = ds1337_read_alarm,
1188     .set_alarm  = ds1337_set_alarm,
1189     .alarm_irq_enable = ds1307_alarm_irq_enable,
1190 };
1191 
1192 static ssize_t frequency_test_store(struct device *dev,
1193                     struct device_attribute *attr,
1194                     const char *buf, size_t count)
1195 {
1196     struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1197     bool freq_test_en;
1198     int ret;
1199 
1200     ret = kstrtobool(buf, &freq_test_en);
1201     if (ret) {
1202         dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
1203         return ret;
1204     }
1205 
1206     regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
1207                freq_test_en ? M41TXX_BIT_FT : 0);
1208 
1209     return count;
1210 }
1211 
1212 static ssize_t frequency_test_show(struct device *dev,
1213                    struct device_attribute *attr,
1214                    char *buf)
1215 {
1216     struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
1217     unsigned int ctrl_reg;
1218 
1219     regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
1220 
1221     return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
1222             "off\n");
1223 }
1224 
1225 static DEVICE_ATTR_RW(frequency_test);
1226 
1227 static struct attribute *rtc_freq_test_attrs[] = {
1228     &dev_attr_frequency_test.attr,
1229     NULL,
1230 };
1231 
1232 static const struct attribute_group rtc_freq_test_attr_group = {
1233     .attrs      = rtc_freq_test_attrs,
1234 };
1235 
1236 static int ds1307_add_frequency_test(struct ds1307 *ds1307)
1237 {
1238     int err;
1239 
1240     switch (ds1307->type) {
1241     case m41t0:
1242     case m41t00:
1243     case m41t11:
1244         err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
1245         if (err)
1246             return err;
1247         break;
1248     default:
1249         break;
1250     }
1251 
1252     return 0;
1253 }
1254 
1255 /*----------------------------------------------------------------------*/
1256 
1257 static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
1258                  size_t bytes)
1259 {
1260     struct ds1307 *ds1307 = priv;
1261     const struct chip_desc *chip = &chips[ds1307->type];
1262 
1263     return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
1264                 val, bytes);
1265 }
1266 
1267 static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
1268                   size_t bytes)
1269 {
1270     struct ds1307 *ds1307 = priv;
1271     const struct chip_desc *chip = &chips[ds1307->type];
1272 
1273     return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
1274                  val, bytes);
1275 }
1276 
1277 /*----------------------------------------------------------------------*/
1278 
1279 static u8 ds1307_trickle_init(struct ds1307 *ds1307,
1280                   const struct chip_desc *chip)
1281 {
1282     u32 ohms, chargeable;
1283     bool diode = chip->charge_default;
1284 
1285     if (!chip->do_trickle_setup)
1286         return 0;
1287 
1288     if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
1289                      &ohms) && chip->requires_trickle_resistor)
1290         return 0;
1291 
1292     /* aux-voltage-chargeable takes precedence over the deprecated
1293      * trickle-diode-disable
1294      */
1295     if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
1296                      &chargeable)) {
1297         switch (chargeable) {
1298         case 0:
1299             diode = false;
1300             break;
1301         case 1:
1302             diode = true;
1303             break;
1304         default:
1305             dev_warn(ds1307->dev,
1306                  "unsupported aux-voltage-chargeable value\n");
1307             break;
1308         }
1309     } else if (device_property_read_bool(ds1307->dev,
1310                          "trickle-diode-disable")) {
1311         diode = false;
1312     }
1313 
1314     return chip->do_trickle_setup(ds1307, ohms, diode);
1315 }
1316 
1317 /*----------------------------------------------------------------------*/
1318 
1319 #if IS_REACHABLE(CONFIG_HWMON)
1320 
1321 /*
1322  * Temperature sensor support for ds3231 devices.
1323  */
1324 
1325 #define DS3231_REG_TEMPERATURE  0x11
1326 
1327 /*
1328  * A user-initiated temperature conversion is not started by this function,
1329  * so the temperature is updated once every 64 seconds.
1330  */
1331 static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
1332 {
1333     struct ds1307 *ds1307 = dev_get_drvdata(dev);
1334     u8 temp_buf[2];
1335     s16 temp;
1336     int ret;
1337 
1338     ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
1339                    temp_buf, sizeof(temp_buf));
1340     if (ret)
1341         return ret;
1342     /*
1343      * Temperature is represented as a 10-bit code with a resolution of
1344      * 0.25 degree celsius and encoded in two's complement format.
1345      */
1346     temp = (temp_buf[0] << 8) | temp_buf[1];
1347     temp >>= 6;
1348     *mC = temp * 250;
1349 
1350     return 0;
1351 }
1352 
1353 static ssize_t ds3231_hwmon_show_temp(struct device *dev,
1354                       struct device_attribute *attr, char *buf)
1355 {
1356     int ret;
1357     s32 temp;
1358 
1359     ret = ds3231_hwmon_read_temp(dev, &temp);
1360     if (ret)
1361         return ret;
1362 
1363     return sprintf(buf, "%d\n", temp);
1364 }
1365 static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
1366               NULL, 0);
1367 
1368 static struct attribute *ds3231_hwmon_attrs[] = {
1369     &sensor_dev_attr_temp1_input.dev_attr.attr,
1370     NULL,
1371 };
1372 ATTRIBUTE_GROUPS(ds3231_hwmon);
1373 
1374 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1375 {
1376     struct device *dev;
1377 
1378     if (ds1307->type != ds_3231)
1379         return;
1380 
1381     dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
1382                              ds1307,
1383                              ds3231_hwmon_groups);
1384     if (IS_ERR(dev)) {
1385         dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
1386              PTR_ERR(dev));
1387     }
1388 }
1389 
1390 #else
1391 
1392 static void ds1307_hwmon_register(struct ds1307 *ds1307)
1393 {
1394 }
1395 
1396 #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
1397 
1398 /*----------------------------------------------------------------------*/
1399 
1400 /*
1401  * Square-wave output support for DS3231
1402  * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
1403  */
1404 #ifdef CONFIG_COMMON_CLK
1405 
1406 enum {
1407     DS3231_CLK_SQW = 0,
1408     DS3231_CLK_32KHZ,
1409 };
1410 
1411 #define clk_sqw_to_ds1307(clk)  \
1412     container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
1413 #define clk_32khz_to_ds1307(clk)    \
1414     container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
1415 
1416 static int ds3231_clk_sqw_rates[] = {
1417     1,
1418     1024,
1419     4096,
1420     8192,
1421 };
1422 
1423 static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
1424 {
1425     struct mutex *lock = &ds1307->rtc->ops_lock;
1426     int ret;
1427 
1428     mutex_lock(lock);
1429     ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
1430                  mask, value);
1431     mutex_unlock(lock);
1432 
1433     return ret;
1434 }
1435 
1436 static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
1437                         unsigned long parent_rate)
1438 {
1439     struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1440     int control, ret;
1441     int rate_sel = 0;
1442 
1443     ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1444     if (ret)
1445         return ret;
1446     if (control & DS1337_BIT_RS1)
1447         rate_sel += 1;
1448     if (control & DS1337_BIT_RS2)
1449         rate_sel += 2;
1450 
1451     return ds3231_clk_sqw_rates[rate_sel];
1452 }
1453 
1454 static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
1455                       unsigned long *prate)
1456 {
1457     int i;
1458 
1459     for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
1460         if (ds3231_clk_sqw_rates[i] <= rate)
1461             return ds3231_clk_sqw_rates[i];
1462     }
1463 
1464     return 0;
1465 }
1466 
1467 static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
1468                    unsigned long parent_rate)
1469 {
1470     struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1471     int control = 0;
1472     int rate_sel;
1473 
1474     for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
1475             rate_sel++) {
1476         if (ds3231_clk_sqw_rates[rate_sel] == rate)
1477             break;
1478     }
1479 
1480     if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
1481         return -EINVAL;
1482 
1483     if (rate_sel & 1)
1484         control |= DS1337_BIT_RS1;
1485     if (rate_sel & 2)
1486         control |= DS1337_BIT_RS2;
1487 
1488     return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
1489                 control);
1490 }
1491 
1492 static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
1493 {
1494     struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1495 
1496     return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
1497 }
1498 
1499 static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
1500 {
1501     struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1502 
1503     ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
1504 }
1505 
1506 static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
1507 {
1508     struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
1509     int control, ret;
1510 
1511     ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
1512     if (ret)
1513         return ret;
1514 
1515     return !(control & DS1337_BIT_INTCN);
1516 }
1517 
1518 static const struct clk_ops ds3231_clk_sqw_ops = {
1519     .prepare = ds3231_clk_sqw_prepare,
1520     .unprepare = ds3231_clk_sqw_unprepare,
1521     .is_prepared = ds3231_clk_sqw_is_prepared,
1522     .recalc_rate = ds3231_clk_sqw_recalc_rate,
1523     .round_rate = ds3231_clk_sqw_round_rate,
1524     .set_rate = ds3231_clk_sqw_set_rate,
1525 };
1526 
1527 static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
1528                           unsigned long parent_rate)
1529 {
1530     return 32768;
1531 }
1532 
1533 static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
1534 {
1535     struct mutex *lock = &ds1307->rtc->ops_lock;
1536     int ret;
1537 
1538     mutex_lock(lock);
1539     ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
1540                  DS3231_BIT_EN32KHZ,
1541                  enable ? DS3231_BIT_EN32KHZ : 0);
1542     mutex_unlock(lock);
1543 
1544     return ret;
1545 }
1546 
1547 static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
1548 {
1549     struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1550 
1551     return ds3231_clk_32khz_control(ds1307, true);
1552 }
1553 
1554 static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
1555 {
1556     struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1557 
1558     ds3231_clk_32khz_control(ds1307, false);
1559 }
1560 
1561 static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
1562 {
1563     struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
1564     int status, ret;
1565 
1566     ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
1567     if (ret)
1568         return ret;
1569 
1570     return !!(status & DS3231_BIT_EN32KHZ);
1571 }
1572 
1573 static const struct clk_ops ds3231_clk_32khz_ops = {
1574     .prepare = ds3231_clk_32khz_prepare,
1575     .unprepare = ds3231_clk_32khz_unprepare,
1576     .is_prepared = ds3231_clk_32khz_is_prepared,
1577     .recalc_rate = ds3231_clk_32khz_recalc_rate,
1578 };
1579 
1580 static const char *ds3231_clks_names[] = {
1581     [DS3231_CLK_SQW] = "ds3231_clk_sqw",
1582     [DS3231_CLK_32KHZ] = "ds3231_clk_32khz",
1583 };
1584 
1585 static struct clk_init_data ds3231_clks_init[] = {
1586     [DS3231_CLK_SQW] = {
1587         .ops = &ds3231_clk_sqw_ops,
1588     },
1589     [DS3231_CLK_32KHZ] = {
1590         .ops = &ds3231_clk_32khz_ops,
1591     },
1592 };
1593 
1594 static int ds3231_clks_register(struct ds1307 *ds1307)
1595 {
1596     struct device_node *node = ds1307->dev->of_node;
1597     struct clk_onecell_data *onecell;
1598     int i;
1599 
1600     onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
1601     if (!onecell)
1602         return -ENOMEM;
1603 
1604     onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
1605     onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
1606                      sizeof(onecell->clks[0]), GFP_KERNEL);
1607     if (!onecell->clks)
1608         return -ENOMEM;
1609 
1610     /* optional override of the clockname */
1611     device_property_read_string_array(ds1307->dev, "clock-output-names",
1612                       ds3231_clks_names,
1613                       ARRAY_SIZE(ds3231_clks_names));
1614 
1615     for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
1616         struct clk_init_data init = ds3231_clks_init[i];
1617 
1618         /*
1619          * Interrupt signal due to alarm conditions and square-wave
1620          * output share same pin, so don't initialize both.
1621          */
1622         if (i == DS3231_CLK_SQW && test_bit(RTC_FEATURE_ALARM, ds1307->rtc->features))
1623             continue;
1624 
1625         init.name = ds3231_clks_names[i];
1626         ds1307->clks[i].init = &init;
1627 
1628         onecell->clks[i] = devm_clk_register(ds1307->dev,
1629                              &ds1307->clks[i]);
1630         if (IS_ERR(onecell->clks[i]))
1631             return PTR_ERR(onecell->clks[i]);
1632     }
1633 
1634     if (node)
1635         of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
1636 
1637     return 0;
1638 }
1639 
1640 static void ds1307_clks_register(struct ds1307 *ds1307)
1641 {
1642     int ret;
1643 
1644     if (ds1307->type != ds_3231)
1645         return;
1646 
1647     ret = ds3231_clks_register(ds1307);
1648     if (ret) {
1649         dev_warn(ds1307->dev, "unable to register clock device %d\n",
1650              ret);
1651     }
1652 }
1653 
1654 #else
1655 
1656 static void ds1307_clks_register(struct ds1307 *ds1307)
1657 {
1658 }
1659 
1660 #endif /* CONFIG_COMMON_CLK */
1661 
1662 #ifdef CONFIG_WATCHDOG_CORE
1663 static const struct watchdog_info ds1388_wdt_info = {
1664     .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
1665     .identity = "DS1388 watchdog",
1666 };
1667 
1668 static const struct watchdog_ops ds1388_wdt_ops = {
1669     .owner = THIS_MODULE,
1670     .start = ds1388_wdt_start,
1671     .stop = ds1388_wdt_stop,
1672     .ping = ds1388_wdt_ping,
1673     .set_timeout = ds1388_wdt_set_timeout,
1674 
1675 };
1676 
1677 static void ds1307_wdt_register(struct ds1307 *ds1307)
1678 {
1679     struct watchdog_device  *wdt;
1680     int err;
1681     int val;
1682 
1683     if (ds1307->type != ds_1388)
1684         return;
1685 
1686     wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
1687     if (!wdt)
1688         return;
1689 
1690     err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
1691     if (!err && val & DS1388_BIT_WF)
1692         wdt->bootstatus = WDIOF_CARDRESET;
1693 
1694     wdt->info = &ds1388_wdt_info;
1695     wdt->ops = &ds1388_wdt_ops;
1696     wdt->timeout = 99;
1697     wdt->max_timeout = 99;
1698     wdt->min_timeout = 1;
1699 
1700     watchdog_init_timeout(wdt, 0, ds1307->dev);
1701     watchdog_set_drvdata(wdt, ds1307);
1702     devm_watchdog_register_device(ds1307->dev, wdt);
1703 }
1704 #else
1705 static void ds1307_wdt_register(struct ds1307 *ds1307)
1706 {
1707 }
1708 #endif /* CONFIG_WATCHDOG_CORE */
1709 
1710 static const struct regmap_config regmap_config = {
1711     .reg_bits = 8,
1712     .val_bits = 8,
1713 };
1714 
1715 static int ds1307_probe(struct i2c_client *client,
1716             const struct i2c_device_id *id)
1717 {
1718     struct ds1307       *ds1307;
1719     const void      *match;
1720     int         err = -ENODEV;
1721     int         tmp;
1722     const struct chip_desc  *chip;
1723     bool            want_irq;
1724     bool            ds1307_can_wakeup_device = false;
1725     unsigned char       regs[8];
1726     struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
1727     u8          trickle_charger_setup = 0;
1728 
1729     ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
1730     if (!ds1307)
1731         return -ENOMEM;
1732 
1733     dev_set_drvdata(&client->dev, ds1307);
1734     ds1307->dev = &client->dev;
1735     ds1307->name = client->name;
1736 
1737     ds1307->regmap = devm_regmap_init_i2c(client, &regmap_config);
1738     if (IS_ERR(ds1307->regmap)) {
1739         dev_err(ds1307->dev, "regmap allocation failed\n");
1740         return PTR_ERR(ds1307->regmap);
1741     }
1742 
1743     i2c_set_clientdata(client, ds1307);
1744 
1745     match = device_get_match_data(&client->dev);
1746     if (match) {
1747         ds1307->type = (enum ds_type)match;
1748         chip = &chips[ds1307->type];
1749     } else if (id) {
1750         chip = &chips[id->driver_data];
1751         ds1307->type = id->driver_data;
1752     } else {
1753         return -ENODEV;
1754     }
1755 
1756     want_irq = client->irq > 0 && chip->alarm;
1757 
1758     if (!pdata)
1759         trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
1760     else if (pdata->trickle_charger_setup)
1761         trickle_charger_setup = pdata->trickle_charger_setup;
1762 
1763     if (trickle_charger_setup && chip->trickle_charger_reg) {
1764         dev_dbg(ds1307->dev,
1765             "writing trickle charger info 0x%x to 0x%x\n",
1766             trickle_charger_setup, chip->trickle_charger_reg);
1767         regmap_write(ds1307->regmap, chip->trickle_charger_reg,
1768                  trickle_charger_setup);
1769     }
1770 
1771 /*
1772  * For devices with no IRQ directly connected to the SoC, the RTC chip
1773  * can be forced as a wakeup source by stating that explicitly in
1774  * the device's .dts file using the "wakeup-source" boolean property.
1775  * If the "wakeup-source" property is set, don't request an IRQ.
1776  * This will guarantee the 'wakealarm' sysfs entry is available on the device,
1777  * if supported by the RTC.
1778  */
1779     if (chip->alarm && device_property_read_bool(&client->dev, "wakeup-source"))
1780         ds1307_can_wakeup_device = true;
1781 
1782     switch (ds1307->type) {
1783     case ds_1337:
1784     case ds_1339:
1785     case ds_1341:
1786     case ds_3231:
1787         /* get registers that the "rtc" read below won't read... */
1788         err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
1789                        regs, 2);
1790         if (err) {
1791             dev_dbg(ds1307->dev, "read error %d\n", err);
1792             goto exit;
1793         }
1794 
1795         /* oscillator off?  turn it on, so clock can tick. */
1796         if (regs[0] & DS1337_BIT_nEOSC)
1797             regs[0] &= ~DS1337_BIT_nEOSC;
1798 
1799         /*
1800          * Using IRQ or defined as wakeup-source?
1801          * Disable the square wave and both alarms.
1802          * For some variants, be sure alarms can trigger when we're
1803          * running on Vbackup (BBSQI/BBSQW)
1804          */
1805         if (want_irq || ds1307_can_wakeup_device) {
1806             regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
1807             regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
1808         }
1809 
1810         regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
1811                  regs[0]);
1812 
1813         /* oscillator fault?  clear flag, and warn */
1814         if (regs[1] & DS1337_BIT_OSF) {
1815             regmap_write(ds1307->regmap, DS1337_REG_STATUS,
1816                      regs[1] & ~DS1337_BIT_OSF);
1817             dev_warn(ds1307->dev, "SET TIME!\n");
1818         }
1819         break;
1820 
1821     case rx_8025:
1822         err = regmap_bulk_read(ds1307->regmap,
1823                        RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
1824         if (err) {
1825             dev_dbg(ds1307->dev, "read error %d\n", err);
1826             goto exit;
1827         }
1828 
1829         /* oscillator off?  turn it on, so clock can tick. */
1830         if (!(regs[1] & RX8025_BIT_XST)) {
1831             regs[1] |= RX8025_BIT_XST;
1832             regmap_write(ds1307->regmap,
1833                      RX8025_REG_CTRL2 << 4 | 0x08,
1834                      regs[1]);
1835             dev_warn(ds1307->dev,
1836                  "oscillator stop detected - SET TIME!\n");
1837         }
1838 
1839         if (regs[1] & RX8025_BIT_PON) {
1840             regs[1] &= ~RX8025_BIT_PON;
1841             regmap_write(ds1307->regmap,
1842                      RX8025_REG_CTRL2 << 4 | 0x08,
1843                      regs[1]);
1844             dev_warn(ds1307->dev, "power-on detected\n");
1845         }
1846 
1847         if (regs[1] & RX8025_BIT_VDET) {
1848             regs[1] &= ~RX8025_BIT_VDET;
1849             regmap_write(ds1307->regmap,
1850                      RX8025_REG_CTRL2 << 4 | 0x08,
1851                      regs[1]);
1852             dev_warn(ds1307->dev, "voltage drop detected\n");
1853         }
1854 
1855         /* make sure we are running in 24hour mode */
1856         if (!(regs[0] & RX8025_BIT_2412)) {
1857             u8 hour;
1858 
1859             /* switch to 24 hour mode */
1860             regmap_write(ds1307->regmap,
1861                      RX8025_REG_CTRL1 << 4 | 0x08,
1862                      regs[0] | RX8025_BIT_2412);
1863 
1864             err = regmap_bulk_read(ds1307->regmap,
1865                            RX8025_REG_CTRL1 << 4 | 0x08,
1866                            regs, 2);
1867             if (err) {
1868                 dev_dbg(ds1307->dev, "read error %d\n", err);
1869                 goto exit;
1870             }
1871 
1872             /* correct hour */
1873             hour = bcd2bin(regs[DS1307_REG_HOUR]);
1874             if (hour == 12)
1875                 hour = 0;
1876             if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1877                 hour += 12;
1878 
1879             regmap_write(ds1307->regmap,
1880                      DS1307_REG_HOUR << 4 | 0x08, hour);
1881         }
1882         break;
1883     case ds_1388:
1884         err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
1885         if (err) {
1886             dev_dbg(ds1307->dev, "read error %d\n", err);
1887             goto exit;
1888         }
1889 
1890         /* oscillator off?  turn it on, so clock can tick. */
1891         if (tmp & DS1388_BIT_nEOSC) {
1892             tmp &= ~DS1388_BIT_nEOSC;
1893             regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
1894         }
1895         break;
1896     default:
1897         break;
1898     }
1899 
1900     /* read RTC registers */
1901     err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
1902                    sizeof(regs));
1903     if (err) {
1904         dev_dbg(ds1307->dev, "read error %d\n", err);
1905         goto exit;
1906     }
1907 
1908     if (ds1307->type == mcp794xx &&
1909         !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
1910         regmap_write(ds1307->regmap, DS1307_REG_WDAY,
1911                  regs[DS1307_REG_WDAY] |
1912                  MCP794XX_BIT_VBATEN);
1913     }
1914 
1915     tmp = regs[DS1307_REG_HOUR];
1916     switch (ds1307->type) {
1917     case ds_1340:
1918     case m41t0:
1919     case m41t00:
1920     case m41t11:
1921         /*
1922          * NOTE: ignores century bits; fix before deploying
1923          * systems that will run through year 2100.
1924          */
1925         break;
1926     case rx_8025:
1927         break;
1928     default:
1929         if (!(tmp & DS1307_BIT_12HR))
1930             break;
1931 
1932         /*
1933          * Be sure we're in 24 hour mode.  Multi-master systems
1934          * take note...
1935          */
1936         tmp = bcd2bin(tmp & 0x1f);
1937         if (tmp == 12)
1938             tmp = 0;
1939         if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
1940             tmp += 12;
1941         regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
1942                  bin2bcd(tmp));
1943     }
1944 
1945     ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
1946     if (IS_ERR(ds1307->rtc))
1947         return PTR_ERR(ds1307->rtc);
1948 
1949     if (want_irq || ds1307_can_wakeup_device)
1950         device_set_wakeup_capable(ds1307->dev, true);
1951     else
1952         clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1953 
1954     if (ds1307_can_wakeup_device && !want_irq) {
1955         dev_info(ds1307->dev,
1956              "'wakeup-source' is set, request for an IRQ is disabled!\n");
1957         /* We cannot support UIE mode if we do not have an IRQ line */
1958         clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, ds1307->rtc->features);
1959     }
1960 
1961     if (want_irq) {
1962         err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
1963                         chip->irq_handler ?: ds1307_irq,
1964                         IRQF_SHARED | IRQF_ONESHOT,
1965                         ds1307->name, ds1307);
1966         if (err) {
1967             client->irq = 0;
1968             device_set_wakeup_capable(ds1307->dev, false);
1969             clear_bit(RTC_FEATURE_ALARM, ds1307->rtc->features);
1970             dev_err(ds1307->dev, "unable to request IRQ!\n");
1971         } else {
1972             dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
1973         }
1974     }
1975 
1976     ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
1977     err = ds1307_add_frequency_test(ds1307);
1978     if (err)
1979         return err;
1980 
1981     err = devm_rtc_register_device(ds1307->rtc);
1982     if (err)
1983         return err;
1984 
1985     if (chip->nvram_size) {
1986         struct nvmem_config nvmem_cfg = {
1987             .name = "ds1307_nvram",
1988             .word_size = 1,
1989             .stride = 1,
1990             .size = chip->nvram_size,
1991             .reg_read = ds1307_nvram_read,
1992             .reg_write = ds1307_nvram_write,
1993             .priv = ds1307,
1994         };
1995 
1996         devm_rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
1997     }
1998 
1999     ds1307_hwmon_register(ds1307);
2000     ds1307_clks_register(ds1307);
2001     ds1307_wdt_register(ds1307);
2002 
2003     return 0;
2004 
2005 exit:
2006     return err;
2007 }
2008 
2009 static struct i2c_driver ds1307_driver = {
2010     .driver = {
2011         .name   = "rtc-ds1307",
2012         .of_match_table = ds1307_of_match,
2013     },
2014     .probe      = ds1307_probe,
2015     .id_table   = ds1307_id,
2016 };
2017 
2018 module_i2c_driver(ds1307_driver);
2019 
2020 MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
2021 MODULE_LICENSE("GPL");
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