drivers/rtc/rtc-ds1302.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Dallas DS1302 RTC Support
0004  *
0005  *  Copyright (C) 2002 David McCullough
0006  *  Copyright (C) 2003 - 2007 Paul Mundt
0007  */
0008
0009 #include <linux/bcd.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/rtc.h>
0016 #include <linux/spi/spi.h>
0017
0018 #define RTC_CMD_READ    0x81        /* Read command */
0019 #define RTC_CMD_WRITE   0x80        /* Write command */
0020
0021 #define RTC_CMD_WRITE_ENABLE    0x00        /* Write enable */
0022 #define RTC_CMD_WRITE_DISABLE   0x80        /* Write disable */
0023
0024 #define RTC_ADDR_RAM0   0x20        /* Address of RAM0 */
0025 #define RTC_ADDR_TCR    0x08        /* Address of trickle charge register */
0026 #define RTC_CLCK_BURST  0x1F        /* Address of clock burst */
0027 #define RTC_CLCK_LEN    0x08        /* Size of clock burst */
0028 #define RTC_ADDR_CTRL   0x07        /* Address of control register */
0029 #define RTC_ADDR_YEAR   0x06        /* Address of year register */
0030 #define RTC_ADDR_DAY    0x05        /* Address of day of week register */
0031 #define RTC_ADDR_MON    0x04        /* Address of month register */
0032 #define RTC_ADDR_DATE   0x03        /* Address of day of month register */
0033 #define RTC_ADDR_HOUR   0x02        /* Address of hour register */
0034 #define RTC_ADDR_MIN    0x01        /* Address of minute register */
0035 #define RTC_ADDR_SEC    0x00        /* Address of second register */
0036
0037 static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
0038 {
0039     struct spi_device   *spi = dev_get_drvdata(dev);
0040     u8      buf[1 + RTC_CLCK_LEN];
0041     u8      *bp;
0042     int     status;
0043
0044     /* Enable writing */
0045     bp = buf;
0046     *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
0047     *bp++ = RTC_CMD_WRITE_ENABLE;
0048
0049     status = spi_write_then_read(spi, buf, 2,
0050             NULL, 0);
0051     if (status)
0052         return status;
0053
0054     /* Write registers starting at the first time/date address. */
0055     bp = buf;
0056     *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
0057
0058     *bp++ = bin2bcd(time->tm_sec);
0059     *bp++ = bin2bcd(time->tm_min);
0060     *bp++ = bin2bcd(time->tm_hour);
0061     *bp++ = bin2bcd(time->tm_mday);
0062     *bp++ = bin2bcd(time->tm_mon + 1);
0063     *bp++ = time->tm_wday + 1;
0064     *bp++ = bin2bcd(time->tm_year % 100);
0065     *bp++ = RTC_CMD_WRITE_DISABLE;
0066
0067     /* use write-then-read since dma from stack is nonportable */
0068     return spi_write_then_read(spi, buf, sizeof(buf),
0069             NULL, 0);
0070 }
0071
0072 static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
0073 {
0074     struct spi_device   *spi = dev_get_drvdata(dev);
0075     u8      addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
0076     u8      buf[RTC_CLCK_LEN - 1];
0077     int     status;
0078
0079     /* Use write-then-read to get all the date/time registers
0080      * since dma from stack is nonportable
0081      */
0082     status = spi_write_then_read(spi, &addr, sizeof(addr),
0083             buf, sizeof(buf));
0084     if (status < 0)
0085         return status;
0086
0087     /* Decode the registers */
0088     time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
0089     time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
0090     time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
0091     time->tm_wday = buf[RTC_ADDR_DAY] - 1;
0092     time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
0093     time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
0094     time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
0095
0096     return 0;
0097 }
0098
0099 static const struct rtc_class_ops ds1302_rtc_ops = {
0100     .read_time  = ds1302_rtc_get_time,
0101     .set_time   = ds1302_rtc_set_time,
0102 };
0103
0104 static int ds1302_probe(struct spi_device *spi)
0105 {
0106     struct rtc_device   *rtc;
0107     u8      addr;
0108     u8      buf[4];
0109     u8      *bp;
0110     int     status;
0111
0112     /* Sanity check board setup data.  This may be hooked up
0113      * in 3wire mode, but we don't care.  Note that unless
0114      * there's an inverter in place, this needs SPI_CS_HIGH!
0115      */
0116     if (spi->bits_per_word && (spi->bits_per_word != 8)) {
0117         dev_err(&spi->dev, "bad word length\n");
0118         return -EINVAL;
0119     } else if (spi->max_speed_hz > 2000000) {
0120         dev_err(&spi->dev, "speed is too high\n");
0121         return -EINVAL;
0122     } else if (spi->mode & SPI_CPHA) {
0123         dev_err(&spi->dev, "bad mode\n");
0124         return -EINVAL;
0125     }
0126
0127     addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
0128     status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
0129     if (status < 0) {
0130         dev_err(&spi->dev, "control register read error %d\n",
0131                 status);
0132         return status;
0133     }
0134
0135     if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
0136         status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
0137         if (status < 0) {
0138             dev_err(&spi->dev, "control register read error %d\n",
0139                     status);
0140             return status;
0141         }
0142
0143         if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
0144             dev_err(&spi->dev, "junk in control register\n");
0145             return -ENODEV;
0146         }
0147     }
0148     if (buf[0] == 0) {
0149         bp = buf;
0150         *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
0151         *bp++ = RTC_CMD_WRITE_DISABLE;
0152
0153         status = spi_write_then_read(spi, buf, 2, NULL, 0);
0154         if (status < 0) {
0155             dev_err(&spi->dev, "control register write error %d\n",
0156                     status);
0157             return status;
0158         }
0159
0160         addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
0161         status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
0162         if (status < 0) {
0163             dev_err(&spi->dev,
0164                     "error %d reading control register\n",
0165                     status);
0166             return status;
0167         }
0168
0169         if (buf[0] != RTC_CMD_WRITE_DISABLE) {
0170             dev_err(&spi->dev, "failed to detect chip\n");
0171             return -ENODEV;
0172         }
0173     }
0174
0175     spi_set_drvdata(spi, spi);
0176
0177     rtc = devm_rtc_device_register(&spi->dev, "ds1302",
0178             &ds1302_rtc_ops, THIS_MODULE);
0179     if (IS_ERR(rtc)) {
0180         status = PTR_ERR(rtc);
0181         dev_err(&spi->dev, "error %d registering rtc\n", status);
0182         return status;
0183     }
0184
0185     return 0;
0186 }
0187
0188 static void ds1302_remove(struct spi_device *spi)
0189 {
0190     spi_set_drvdata(spi, NULL);
0191 }
0192
0193 #ifdef CONFIG_OF
0194 static const struct of_device_id ds1302_dt_ids[] = {
0195     { .compatible = "maxim,ds1302", },
0196     { /* sentinel */ }
0197 };
0198 MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
0199 #endif
0200
0201 static const struct spi_device_id ds1302_spi_ids[] = {
0202     { .name = "ds1302", },
0203     { /* sentinel */ }
0204 };
0205 MODULE_DEVICE_TABLE(spi, ds1302_spi_ids);
0206
0207 static struct spi_driver ds1302_driver = {
0208     .driver.name    = "rtc-ds1302",
0209     .driver.of_match_table = of_match_ptr(ds1302_dt_ids),
0210     .probe      = ds1302_probe,
0211     .remove     = ds1302_remove,
0212     .id_table   = ds1302_spi_ids,
0213 };
0214
0215 module_spi_driver(ds1302_driver);
0216
0217 MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
0218 MODULE_AUTHOR("Paul Mundt, David McCullough");
0219 MODULE_LICENSE("GPL v2");