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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Motorola CPCAP PMIC RTC driver
0004  *
0005  * Based on cpcap-regulator.c from Motorola Linux kernel tree
0006  * Copyright (C) 2009 Motorola, Inc.
0007  *
0008  * Rewritten for mainline kernel
0009  *  - use DT
0010  *  - use regmap
0011  *  - use standard interrupt framework
0012  *  - use managed device resources
0013  *  - remove custom "secure clock daemon" helpers
0014  *
0015  * Copyright (C) 2017 Sebastian Reichel <sre@kernel.org>
0016  */
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/mod_devicetable.h>
0020 #include <linux/init.h>
0021 #include <linux/device.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/rtc.h>
0024 #include <linux/err.h>
0025 #include <linux/regmap.h>
0026 #include <linux/mfd/motorola-cpcap.h>
0027 #include <linux/slab.h>
0028 #include <linux/sched.h>
0029 
0030 #define SECS_PER_DAY 86400
0031 #define DAY_MASK  0x7FFF
0032 #define TOD1_MASK 0x00FF
0033 #define TOD2_MASK 0x01FF
0034 
0035 struct cpcap_time {
0036     int day;
0037     int tod1;
0038     int tod2;
0039 };
0040 
0041 struct cpcap_rtc {
0042     struct regmap *regmap;
0043     struct rtc_device *rtc_dev;
0044     u16 vendor;
0045     int alarm_irq;
0046     bool alarm_enabled;
0047     int update_irq;
0048     bool update_enabled;
0049 };
0050 
0051 static void cpcap2rtc_time(struct rtc_time *rtc, struct cpcap_time *cpcap)
0052 {
0053     unsigned long int tod;
0054     unsigned long int time;
0055 
0056     tod = (cpcap->tod1 & TOD1_MASK) | ((cpcap->tod2 & TOD2_MASK) << 8);
0057     time = tod + ((cpcap->day & DAY_MASK) * SECS_PER_DAY);
0058 
0059     rtc_time64_to_tm(time, rtc);
0060 }
0061 
0062 static void rtc2cpcap_time(struct cpcap_time *cpcap, struct rtc_time *rtc)
0063 {
0064     unsigned long time;
0065 
0066     time = rtc_tm_to_time64(rtc);
0067 
0068     cpcap->day = time / SECS_PER_DAY;
0069     time %= SECS_PER_DAY;
0070     cpcap->tod2 = (time >> 8) & TOD2_MASK;
0071     cpcap->tod1 = time & TOD1_MASK;
0072 }
0073 
0074 static int cpcap_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0075 {
0076     struct cpcap_rtc *rtc = dev_get_drvdata(dev);
0077 
0078     if (rtc->alarm_enabled == enabled)
0079         return 0;
0080 
0081     if (enabled)
0082         enable_irq(rtc->alarm_irq);
0083     else
0084         disable_irq(rtc->alarm_irq);
0085 
0086     rtc->alarm_enabled = !!enabled;
0087 
0088     return 0;
0089 }
0090 
0091 static int cpcap_rtc_read_time(struct device *dev, struct rtc_time *tm)
0092 {
0093     struct cpcap_rtc *rtc;
0094     struct cpcap_time cpcap_tm;
0095     int temp_tod2;
0096     int ret;
0097 
0098     rtc = dev_get_drvdata(dev);
0099 
0100     ret = regmap_read(rtc->regmap, CPCAP_REG_TOD2, &temp_tod2);
0101     ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
0102     ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD1, &cpcap_tm.tod1);
0103     ret |= regmap_read(rtc->regmap, CPCAP_REG_TOD2, &cpcap_tm.tod2);
0104 
0105     if (temp_tod2 > cpcap_tm.tod2)
0106         ret |= regmap_read(rtc->regmap, CPCAP_REG_DAY, &cpcap_tm.day);
0107 
0108     if (ret) {
0109         dev_err(dev, "Failed to read time\n");
0110         return -EIO;
0111     }
0112 
0113     cpcap2rtc_time(tm, &cpcap_tm);
0114 
0115     return 0;
0116 }
0117 
0118 static int cpcap_rtc_set_time(struct device *dev, struct rtc_time *tm)
0119 {
0120     struct cpcap_rtc *rtc;
0121     struct cpcap_time cpcap_tm;
0122     int ret = 0;
0123 
0124     rtc = dev_get_drvdata(dev);
0125 
0126     rtc2cpcap_time(&cpcap_tm, tm);
0127 
0128     if (rtc->alarm_enabled)
0129         disable_irq(rtc->alarm_irq);
0130     if (rtc->update_enabled)
0131         disable_irq(rtc->update_irq);
0132 
0133     if (rtc->vendor == CPCAP_VENDOR_ST) {
0134         /* The TOD1 and TOD2 registers MUST be written in this order
0135          * for the change to properly set.
0136          */
0137         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
0138                       TOD1_MASK, cpcap_tm.tod1);
0139         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
0140                       TOD2_MASK, cpcap_tm.tod2);
0141         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
0142                       DAY_MASK, cpcap_tm.day);
0143     } else {
0144         /* Clearing the upper lower 8 bits of the TOD guarantees that
0145          * the upper half of TOD (TOD2) will not increment for 0xFF RTC
0146          * ticks (255 seconds).  During this time we can safely write
0147          * to DAY, TOD2, then TOD1 (in that order) and expect RTC to be
0148          * synchronized to the exact time requested upon the final write
0149          * to TOD1.
0150          */
0151         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
0152                       TOD1_MASK, 0);
0153         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_DAY,
0154                       DAY_MASK, cpcap_tm.day);
0155         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD2,
0156                       TOD2_MASK, cpcap_tm.tod2);
0157         ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TOD1,
0158                       TOD1_MASK, cpcap_tm.tod1);
0159     }
0160 
0161     if (rtc->update_enabled)
0162         enable_irq(rtc->update_irq);
0163     if (rtc->alarm_enabled)
0164         enable_irq(rtc->alarm_irq);
0165 
0166     return ret;
0167 }
0168 
0169 static int cpcap_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0170 {
0171     struct cpcap_rtc *rtc;
0172     struct cpcap_time cpcap_tm;
0173     int ret;
0174 
0175     rtc = dev_get_drvdata(dev);
0176 
0177     alrm->enabled = rtc->alarm_enabled;
0178 
0179     ret = regmap_read(rtc->regmap, CPCAP_REG_DAYA, &cpcap_tm.day);
0180     ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA2, &cpcap_tm.tod2);
0181     ret |= regmap_read(rtc->regmap, CPCAP_REG_TODA1, &cpcap_tm.tod1);
0182 
0183     if (ret) {
0184         dev_err(dev, "Failed to read time\n");
0185         return -EIO;
0186     }
0187 
0188     cpcap2rtc_time(&alrm->time, &cpcap_tm);
0189     return rtc_valid_tm(&alrm->time);
0190 }
0191 
0192 static int cpcap_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0193 {
0194     struct cpcap_rtc *rtc;
0195     struct cpcap_time cpcap_tm;
0196     int ret;
0197 
0198     rtc = dev_get_drvdata(dev);
0199 
0200     rtc2cpcap_time(&cpcap_tm, &alrm->time);
0201 
0202     if (rtc->alarm_enabled)
0203         disable_irq(rtc->alarm_irq);
0204 
0205     ret = regmap_update_bits(rtc->regmap, CPCAP_REG_DAYA, DAY_MASK,
0206                  cpcap_tm.day);
0207     ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA2, TOD2_MASK,
0208                   cpcap_tm.tod2);
0209     ret |= regmap_update_bits(rtc->regmap, CPCAP_REG_TODA1, TOD1_MASK,
0210                   cpcap_tm.tod1);
0211 
0212     if (!ret) {
0213         enable_irq(rtc->alarm_irq);
0214         rtc->alarm_enabled = true;
0215     }
0216 
0217     return ret;
0218 }
0219 
0220 static const struct rtc_class_ops cpcap_rtc_ops = {
0221     .read_time      = cpcap_rtc_read_time,
0222     .set_time       = cpcap_rtc_set_time,
0223     .read_alarm     = cpcap_rtc_read_alarm,
0224     .set_alarm      = cpcap_rtc_set_alarm,
0225     .alarm_irq_enable   = cpcap_rtc_alarm_irq_enable,
0226 };
0227 
0228 static irqreturn_t cpcap_rtc_alarm_irq(int irq, void *data)
0229 {
0230     struct cpcap_rtc *rtc = data;
0231 
0232     rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
0233     return IRQ_HANDLED;
0234 }
0235 
0236 static irqreturn_t cpcap_rtc_update_irq(int irq, void *data)
0237 {
0238     struct cpcap_rtc *rtc = data;
0239 
0240     rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
0241     return IRQ_HANDLED;
0242 }
0243 
0244 static int cpcap_rtc_probe(struct platform_device *pdev)
0245 {
0246     struct device *dev = &pdev->dev;
0247     struct cpcap_rtc *rtc;
0248     int err;
0249 
0250     rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
0251     if (!rtc)
0252         return -ENOMEM;
0253 
0254     rtc->regmap = dev_get_regmap(dev->parent, NULL);
0255     if (!rtc->regmap)
0256         return -ENODEV;
0257 
0258     platform_set_drvdata(pdev, rtc);
0259     rtc->rtc_dev = devm_rtc_allocate_device(dev);
0260     if (IS_ERR(rtc->rtc_dev))
0261         return PTR_ERR(rtc->rtc_dev);
0262 
0263     rtc->rtc_dev->ops = &cpcap_rtc_ops;
0264     rtc->rtc_dev->range_max = (timeu64_t) (DAY_MASK + 1) * SECS_PER_DAY - 1;
0265 
0266     err = cpcap_get_vendor(dev, rtc->regmap, &rtc->vendor);
0267     if (err)
0268         return err;
0269 
0270     rtc->alarm_irq = platform_get_irq(pdev, 0);
0271     err = devm_request_threaded_irq(dev, rtc->alarm_irq, NULL,
0272                     cpcap_rtc_alarm_irq,
0273                     IRQF_TRIGGER_NONE | IRQF_ONESHOT,
0274                     "rtc_alarm", rtc);
0275     if (err) {
0276         dev_err(dev, "Could not request alarm irq: %d\n", err);
0277         return err;
0278     }
0279     disable_irq(rtc->alarm_irq);
0280 
0281     /* Stock Android uses the 1 Hz interrupt for "secure clock daemon",
0282      * which is not supported by the mainline kernel. The mainline kernel
0283      * does not use the irq at the moment, but we explicitly request and
0284      * disable it, so that its masked and does not wake up the processor
0285      * every second.
0286      */
0287     rtc->update_irq = platform_get_irq(pdev, 1);
0288     err = devm_request_threaded_irq(dev, rtc->update_irq, NULL,
0289                     cpcap_rtc_update_irq,
0290                     IRQF_TRIGGER_NONE | IRQF_ONESHOT,
0291                     "rtc_1hz", rtc);
0292     if (err) {
0293         dev_err(dev, "Could not request update irq: %d\n", err);
0294         return err;
0295     }
0296     disable_irq(rtc->update_irq);
0297 
0298     err = device_init_wakeup(dev, 1);
0299     if (err) {
0300         dev_err(dev, "wakeup initialization failed (%d)\n", err);
0301         /* ignore error and continue without wakeup support */
0302     }
0303 
0304     return devm_rtc_register_device(rtc->rtc_dev);
0305 }
0306 
0307 static const struct of_device_id cpcap_rtc_of_match[] = {
0308     { .compatible = "motorola,cpcap-rtc", },
0309     {},
0310 };
0311 MODULE_DEVICE_TABLE(of, cpcap_rtc_of_match);
0312 
0313 static struct platform_driver cpcap_rtc_driver = {
0314     .probe      = cpcap_rtc_probe,
0315     .driver     = {
0316         .name   = "cpcap-rtc",
0317         .of_match_table = cpcap_rtc_of_match,
0318     },
0319 };
0320 
0321 module_platform_driver(cpcap_rtc_driver);
0322 
0323 MODULE_ALIAS("platform:cpcap-rtc");
0324 MODULE_DESCRIPTION("CPCAP RTC driver");
0325 MODULE_AUTHOR("Sebastian Reichel <sre@kernel.org>");
0326 MODULE_LICENSE("GPL");
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