drivers/rtc/rtc-au1xxx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Au1xxx counter0 (aka Time-Of-Year counter) RTC interface driver.
0004  *
0005  * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
0006  */
0007
0008 /* All current Au1xxx SoCs have 2 counters fed by an external 32.768 kHz
0009  * crystal. Counter 0, which keeps counting during sleep/powerdown, is
0010  * used to count seconds since the beginning of the unix epoch.
0011  *
0012  * The counters must be configured and enabled by bootloader/board code;
0013  * no checks as to whether they really get a proper 32.768kHz clock are
0014  * made as this would take far too long.
0015  */
0016
0017 #include <linux/module.h>
0018 #include <linux/kernel.h>
0019 #include <linux/rtc.h>
0020 #include <linux/init.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/io.h>
0023 #include <asm/mach-au1x00/au1000.h>
0024
0025 /* 32kHz clock enabled and detected */
0026 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
0027
0028 static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm)
0029 {
0030     unsigned long t;
0031
0032     t = alchemy_rdsys(AU1000_SYS_TOYREAD);
0033
0034     rtc_time64_to_tm(t, tm);
0035
0036     return 0;
0037 }
0038
0039 static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm)
0040 {
0041     unsigned long t;
0042
0043     t = rtc_tm_to_time64(tm);
0044
0045     alchemy_wrsys(t, AU1000_SYS_TOYWRITE);
0046
0047     /* wait for the pending register write to succeed.  This can
0048      * take up to 6 seconds...
0049      */
0050     while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
0051         msleep(1);
0052
0053     return 0;
0054 }
0055
0056 static const struct rtc_class_ops au1xtoy_rtc_ops = {
0057     .read_time  = au1xtoy_rtc_read_time,
0058     .set_time   = au1xtoy_rtc_set_time,
0059 };
0060
0061 static int au1xtoy_rtc_probe(struct platform_device *pdev)
0062 {
0063     struct rtc_device *rtcdev;
0064     unsigned long t;
0065
0066     t = alchemy_rdsys(AU1000_SYS_CNTRCTRL);
0067     if (!(t & CNTR_OK)) {
0068         dev_err(&pdev->dev, "counters not working; aborting.\n");
0069         return -ENODEV;
0070     }
0071
0072     /* set counter0 tickrate to 1Hz if necessary */
0073     if (alchemy_rdsys(AU1000_SYS_TOYTRIM) != 32767) {
0074         /* wait until hardware gives access to TRIM register */
0075         t = 0x00100000;
0076         while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T0S) && --t)
0077             msleep(1);
0078
0079         if (!t) {
0080             /* timed out waiting for register access; assume
0081              * counters are unusable.
0082              */
0083             dev_err(&pdev->dev, "timeout waiting for access\n");
0084             return -ETIMEDOUT;
0085         }
0086
0087         /* set 1Hz TOY tick rate */
0088         alchemy_wrsys(32767, AU1000_SYS_TOYTRIM);
0089     }
0090
0091     /* wait until the hardware allows writes to the counter reg */
0092     while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C0S)
0093         msleep(1);
0094
0095     rtcdev = devm_rtc_allocate_device(&pdev->dev);
0096     if (IS_ERR(rtcdev))
0097         return PTR_ERR(rtcdev);
0098
0099     rtcdev->ops = &au1xtoy_rtc_ops;
0100     rtcdev->range_max = U32_MAX;
0101
0102     platform_set_drvdata(pdev, rtcdev);
0103
0104     return devm_rtc_register_device(rtcdev);
0105 }
0106
0107 static struct platform_driver au1xrtc_driver = {
0108     .driver     = {
0109         .name   = "rtc-au1xxx",
0110     },
0111 };
0112
0113 module_platform_driver_probe(au1xrtc_driver, au1xtoy_rtc_probe);
0114
0115 MODULE_DESCRIPTION("Au1xxx TOY-counter-based RTC driver");
0116 MODULE_AUTHOR("Manuel Lauss <manuel.lauss@gmail.com>");
0117 MODULE_LICENSE("GPL");
0118 MODULE_ALIAS("platform:rtc-au1xxx");