drivers/rtc/rtc-at91sam9.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
0004  *
0005  * (C) 2007 Michel Benoit
0006  *
0007  * Based on rtc-at91rm9200.c by Rick Bronson
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/ioctl.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regmap.h>
0020 #include <linux/rtc.h>
0021 #include <linux/slab.h>
0022 #include <linux/suspend.h>
0023 #include <linux/time.h>
0024
0025 /*
0026  * This driver uses two configurable hardware resources that live in the
0027  * AT91SAM9 backup power domain (intended to be powered at all times)
0028  * to implement the Real Time Clock interfaces
0029  *
0030  *  - A "Real-time Timer" (RTT) counts up in seconds from a base time.
0031  *    We can't assign the counter value (CRTV) ... but we can reset it.
0032  *
0033  *  - One of the "General Purpose Backup Registers" (GPBRs) holds the
0034  *    base time, normally an offset from the beginning of the POSIX
0035  *    epoch (1970-Jan-1 00:00:00 UTC).  Some systems also include the
0036  *    local timezone's offset.
0037  *
0038  * The RTC's value is the RTT counter plus that offset.  The RTC's alarm
0039  * is likewise a base (ALMV) plus that offset.
0040  *
0041  * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
0042  * choose from, or a "real" RTC module.  All systems have multiple GPBR
0043  * registers available, likewise usable for more than "RTC" support.
0044  */
0045
0046 #define AT91_RTT_MR     0x00        /* Real-time Mode Register */
0047 #define AT91_RTT_RTPRES     (0xffff << 0)   /* Timer Prescaler Value */
0048 #define AT91_RTT_ALMIEN     BIT(16)     /* Alarm Interrupt Enable */
0049 #define AT91_RTT_RTTINCIEN  BIT(17)     /* Increment Interrupt Enable */
0050 #define AT91_RTT_RTTRST     BIT(18)     /* Timer Restart */
0051
0052 #define AT91_RTT_AR     0x04        /* Real-time Alarm Register */
0053 #define AT91_RTT_ALMV       (0xffffffff)    /* Alarm Value */
0054
0055 #define AT91_RTT_VR     0x08        /* Real-time Value Register */
0056 #define AT91_RTT_CRTV       (0xffffffff)    /* Current Real-time Value */
0057
0058 #define AT91_RTT_SR     0x0c        /* Real-time Status Register */
0059 #define AT91_RTT_ALMS       BIT(0)      /* Alarm Status */
0060 #define AT91_RTT_RTTINC     BIT(1)      /* Timer Increment */
0061
0062 /*
0063  * We store ALARM_DISABLED in ALMV to record that no alarm is set.
0064  * It's also the reset value for that field.
0065  */
0066 #define ALARM_DISABLED  ((u32)~0)
0067
0068 struct sam9_rtc {
0069     void __iomem        *rtt;
0070     struct rtc_device   *rtcdev;
0071     u32         imr;
0072     struct regmap       *gpbr;
0073     unsigned int        gpbr_offset;
0074     int         irq;
0075     struct clk      *sclk;
0076     bool            suspended;
0077     unsigned long       events;
0078     spinlock_t      lock;
0079 };
0080
0081 #define rtt_readl(rtc, field) \
0082     readl((rtc)->rtt + AT91_RTT_ ## field)
0083 #define rtt_writel(rtc, field, val) \
0084     writel((val), (rtc)->rtt + AT91_RTT_ ## field)
0085
0086 static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
0087 {
0088     unsigned int val;
0089
0090     regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
0091
0092     return val;
0093 }
0094
0095 static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
0096 {
0097     regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
0098 }
0099
0100 /*
0101  * Read current time and date in RTC
0102  */
0103 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
0104 {
0105     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0106     u32 secs, secs2;
0107     u32 offset;
0108
0109     /* read current time offset */
0110     offset = gpbr_readl(rtc);
0111     if (offset == 0)
0112         return -EILSEQ;
0113
0114     /* reread the counter to help sync the two clock domains */
0115     secs = rtt_readl(rtc, VR);
0116     secs2 = rtt_readl(rtc, VR);
0117     if (secs != secs2)
0118         secs = rtt_readl(rtc, VR);
0119
0120     rtc_time64_to_tm(offset + secs, tm);
0121
0122     dev_dbg(dev, "%s: %ptR\n", __func__, tm);
0123
0124     return 0;
0125 }
0126
0127 /*
0128  * Set current time and date in RTC
0129  */
0130 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
0131 {
0132     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0133     u32 offset, alarm, mr;
0134     unsigned long secs;
0135
0136     dev_dbg(dev, "%s: %ptR\n", __func__, tm);
0137
0138     secs = rtc_tm_to_time64(tm);
0139
0140     mr = rtt_readl(rtc, MR);
0141
0142     /* disable interrupts */
0143     rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
0144
0145     /* read current time offset */
0146     offset = gpbr_readl(rtc);
0147
0148     /* store the new base time in a battery backup register */
0149     secs += 1;
0150     gpbr_writel(rtc, secs);
0151
0152     /* adjust the alarm time for the new base */
0153     alarm = rtt_readl(rtc, AR);
0154     if (alarm != ALARM_DISABLED) {
0155         if (offset > secs) {
0156             /* time jumped backwards, increase time until alarm */
0157             alarm += (offset - secs);
0158         } else if ((alarm + offset) > secs) {
0159             /* time jumped forwards, decrease time until alarm */
0160             alarm -= (secs - offset);
0161         } else {
0162             /* time jumped past the alarm, disable alarm */
0163             alarm = ALARM_DISABLED;
0164             mr &= ~AT91_RTT_ALMIEN;
0165         }
0166         rtt_writel(rtc, AR, alarm);
0167     }
0168
0169     /* reset the timer, and re-enable interrupts */
0170     rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);
0171
0172     return 0;
0173 }
0174
0175 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
0176 {
0177     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0178     struct rtc_time *tm = &alrm->time;
0179     u32 alarm = rtt_readl(rtc, AR);
0180     u32 offset;
0181
0182     offset = gpbr_readl(rtc);
0183     if (offset == 0)
0184         return -EILSEQ;
0185
0186     memset(alrm, 0, sizeof(*alrm));
0187     if (alarm != ALARM_DISABLED) {
0188         rtc_time64_to_tm(offset + alarm, tm);
0189
0190         dev_dbg(dev, "%s: %ptR\n", __func__, tm);
0191
0192         if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
0193             alrm->enabled = 1;
0194     }
0195
0196     return 0;
0197 }
0198
0199 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
0200 {
0201     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0202     struct rtc_time *tm = &alrm->time;
0203     unsigned long secs;
0204     u32 offset;
0205     u32 mr;
0206
0207     secs = rtc_tm_to_time64(tm);
0208
0209     offset = gpbr_readl(rtc);
0210     if (offset == 0) {
0211         /* time is not set */
0212         return -EILSEQ;
0213     }
0214     mr = rtt_readl(rtc, MR);
0215     rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
0216
0217     /* alarm in the past? finish and leave disabled */
0218     if (secs <= offset) {
0219         rtt_writel(rtc, AR, ALARM_DISABLED);
0220         return 0;
0221     }
0222
0223     /* else set alarm and maybe enable it */
0224     rtt_writel(rtc, AR, secs - offset);
0225     if (alrm->enabled)
0226         rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
0227
0228     dev_dbg(dev, "%s: %ptR\n", __func__, tm);
0229
0230     return 0;
0231 }
0232
0233 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0234 {
0235     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0236     u32 mr = rtt_readl(rtc, MR);
0237
0238     dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
0239     if (enabled)
0240         rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
0241     else
0242         rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
0243     return 0;
0244 }
0245
0246 /*
0247  * Provide additional RTC information in /proc/driver/rtc
0248  */
0249 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
0250 {
0251     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0252     u32 mr = rtt_readl(rtc, MR);
0253
0254     seq_printf(seq, "update_IRQ\t: %s\n",
0255            (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
0256     return 0;
0257 }
0258
0259 static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
0260 {
0261     u32 sr, mr;
0262
0263     /* Shared interrupt may be for another device.  Note: reading
0264      * SR clears it, so we must only read it in this irq handler!
0265      */
0266     mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
0267     sr = rtt_readl(rtc, SR) & (mr >> 16);
0268     if (!sr)
0269         return IRQ_NONE;
0270
0271     /* alarm status */
0272     if (sr & AT91_RTT_ALMS)
0273         rtc->events |= (RTC_AF | RTC_IRQF);
0274
0275     /* timer update/increment */
0276     if (sr & AT91_RTT_RTTINC)
0277         rtc->events |= (RTC_UF | RTC_IRQF);
0278
0279     return IRQ_HANDLED;
0280 }
0281
0282 static void at91_rtc_flush_events(struct sam9_rtc *rtc)
0283 {
0284     if (!rtc->events)
0285         return;
0286
0287     rtc_update_irq(rtc->rtcdev, 1, rtc->events);
0288     rtc->events = 0;
0289
0290     pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
0291          rtc->events >> 8, rtc->events & 0x000000FF);
0292 }
0293
0294 /*
0295  * IRQ handler for the RTC
0296  */
0297 static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
0298 {
0299     struct sam9_rtc *rtc = _rtc;
0300     int ret;
0301
0302     spin_lock(&rtc->lock);
0303
0304     ret = at91_rtc_cache_events(rtc);
0305
0306     /* We're called in suspended state */
0307     if (rtc->suspended) {
0308         /* Mask irqs coming from this peripheral */
0309         rtt_writel(rtc, MR,
0310                rtt_readl(rtc, MR) &
0311                ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
0312         /* Trigger a system wakeup */
0313         pm_system_wakeup();
0314     } else {
0315         at91_rtc_flush_events(rtc);
0316     }
0317
0318     spin_unlock(&rtc->lock);
0319
0320     return ret;
0321 }
0322
0323 static const struct rtc_class_ops at91_rtc_ops = {
0324     .read_time  = at91_rtc_readtime,
0325     .set_time   = at91_rtc_settime,
0326     .read_alarm = at91_rtc_readalarm,
0327     .set_alarm  = at91_rtc_setalarm,
0328     .proc       = at91_rtc_proc,
0329     .alarm_irq_enable = at91_rtc_alarm_irq_enable,
0330 };
0331
0332 /*
0333  * Initialize and install RTC driver
0334  */
0335 static int at91_rtc_probe(struct platform_device *pdev)
0336 {
0337     struct sam9_rtc *rtc;
0338     int     ret, irq;
0339     u32     mr;
0340     unsigned int    sclk_rate;
0341     struct of_phandle_args args;
0342
0343     irq = platform_get_irq(pdev, 0);
0344     if (irq < 0)
0345         return irq;
0346
0347     rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
0348     if (!rtc)
0349         return -ENOMEM;
0350
0351     spin_lock_init(&rtc->lock);
0352     rtc->irq = irq;
0353
0354     /* platform setup code should have handled this; sigh */
0355     if (!device_can_wakeup(&pdev->dev))
0356         device_init_wakeup(&pdev->dev, 1);
0357
0358     platform_set_drvdata(pdev, rtc);
0359
0360     rtc->rtt = devm_platform_ioremap_resource(pdev, 0);
0361     if (IS_ERR(rtc->rtt))
0362         return PTR_ERR(rtc->rtt);
0363
0364     ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
0365                            "atmel,rtt-rtc-time-reg", 1, 0,
0366                            &args);
0367     if (ret)
0368         return ret;
0369
0370     rtc->gpbr = syscon_node_to_regmap(args.np);
0371     rtc->gpbr_offset = args.args[0];
0372     if (IS_ERR(rtc->gpbr)) {
0373         dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
0374         return -ENOMEM;
0375     }
0376
0377     rtc->sclk = devm_clk_get(&pdev->dev, NULL);
0378     if (IS_ERR(rtc->sclk))
0379         return PTR_ERR(rtc->sclk);
0380
0381     ret = clk_prepare_enable(rtc->sclk);
0382     if (ret) {
0383         dev_err(&pdev->dev, "Could not enable slow clock\n");
0384         return ret;
0385     }
0386
0387     sclk_rate = clk_get_rate(rtc->sclk);
0388     if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
0389         dev_err(&pdev->dev, "Invalid slow clock rate\n");
0390         ret = -EINVAL;
0391         goto err_clk;
0392     }
0393
0394     mr = rtt_readl(rtc, MR);
0395
0396     /* unless RTT is counting at 1 Hz, re-initialize it */
0397     if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
0398         mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
0399         gpbr_writel(rtc, 0);
0400     }
0401
0402     /* disable all interrupts (same as on shutdown path) */
0403     mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
0404     rtt_writel(rtc, MR, mr);
0405
0406     rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
0407     if (IS_ERR(rtc->rtcdev)) {
0408         ret = PTR_ERR(rtc->rtcdev);
0409         goto err_clk;
0410     }
0411
0412     rtc->rtcdev->ops = &at91_rtc_ops;
0413     rtc->rtcdev->range_max = U32_MAX;
0414
0415     /* register irq handler after we know what name we'll use */
0416     ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
0417                    IRQF_SHARED | IRQF_COND_SUSPEND,
0418                    dev_name(&rtc->rtcdev->dev), rtc);
0419     if (ret) {
0420         dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
0421         goto err_clk;
0422     }
0423
0424     /* NOTE:  sam9260 rev A silicon has a ROM bug which resets the
0425      * RTT on at least some reboots.  If you have that chip, you must
0426      * initialize the time from some external source like a GPS, wall
0427      * clock, discrete RTC, etc
0428      */
0429
0430     if (gpbr_readl(rtc) == 0)
0431         dev_warn(&pdev->dev, "%s: SET TIME!\n",
0432              dev_name(&rtc->rtcdev->dev));
0433
0434     return devm_rtc_register_device(rtc->rtcdev);
0435
0436 err_clk:
0437     clk_disable_unprepare(rtc->sclk);
0438
0439     return ret;
0440 }
0441
0442 /*
0443  * Disable and remove the RTC driver
0444  */
0445 static int at91_rtc_remove(struct platform_device *pdev)
0446 {
0447     struct sam9_rtc *rtc = platform_get_drvdata(pdev);
0448     u32     mr = rtt_readl(rtc, MR);
0449
0450     /* disable all interrupts */
0451     rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
0452
0453     clk_disable_unprepare(rtc->sclk);
0454
0455     return 0;
0456 }
0457
0458 static void at91_rtc_shutdown(struct platform_device *pdev)
0459 {
0460     struct sam9_rtc *rtc = platform_get_drvdata(pdev);
0461     u32     mr = rtt_readl(rtc, MR);
0462
0463     rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
0464     rtt_writel(rtc, MR, mr & ~rtc->imr);
0465 }
0466
0467 #ifdef CONFIG_PM_SLEEP
0468
0469 /* AT91SAM9 RTC Power management control */
0470
0471 static int at91_rtc_suspend(struct device *dev)
0472 {
0473     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0474     u32     mr = rtt_readl(rtc, MR);
0475
0476     /*
0477      * This IRQ is shared with DBGU and other hardware which isn't
0478      * necessarily a wakeup event source.
0479      */
0480     rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
0481     if (rtc->imr) {
0482         if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
0483             unsigned long flags;
0484
0485             enable_irq_wake(rtc->irq);
0486             spin_lock_irqsave(&rtc->lock, flags);
0487             rtc->suspended = true;
0488             spin_unlock_irqrestore(&rtc->lock, flags);
0489             /* don't let RTTINC cause wakeups */
0490             if (mr & AT91_RTT_RTTINCIEN)
0491                 rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
0492         } else {
0493             rtt_writel(rtc, MR, mr & ~rtc->imr);
0494         }
0495     }
0496
0497     return 0;
0498 }
0499
0500 static int at91_rtc_resume(struct device *dev)
0501 {
0502     struct sam9_rtc *rtc = dev_get_drvdata(dev);
0503     u32     mr;
0504
0505     if (rtc->imr) {
0506         unsigned long flags;
0507
0508         if (device_may_wakeup(dev))
0509             disable_irq_wake(rtc->irq);
0510         mr = rtt_readl(rtc, MR);
0511         rtt_writel(rtc, MR, mr | rtc->imr);
0512
0513         spin_lock_irqsave(&rtc->lock, flags);
0514         rtc->suspended = false;
0515         at91_rtc_cache_events(rtc);
0516         at91_rtc_flush_events(rtc);
0517         spin_unlock_irqrestore(&rtc->lock, flags);
0518     }
0519
0520     return 0;
0521 }
0522 #endif
0523
0524 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
0525
0526 static const struct of_device_id at91_rtc_dt_ids[] = {
0527     { .compatible = "atmel,at91sam9260-rtt" },
0528     { /* sentinel */ }
0529 };
0530 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
0531
0532 static struct platform_driver at91_rtc_driver = {
0533     .probe      = at91_rtc_probe,
0534     .remove     = at91_rtc_remove,
0535     .shutdown   = at91_rtc_shutdown,
0536     .driver     = {
0537         .name   = "rtc-at91sam9",
0538         .pm = &at91_rtc_pm_ops,
0539         .of_match_table = of_match_ptr(at91_rtc_dt_ids),
0540     },
0541 };
0542
0543 module_platform_driver(at91_rtc_driver);
0544
0545 MODULE_AUTHOR("Michel Benoit");
0546 MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
0547 MODULE_LICENSE("GPL");