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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Real Time Clock interface for Linux on Atmel AT91RM9200
0004  *
0005  *  Copyright (C) 2002 Rick Bronson
0006  *
0007  *  Converted to RTC class model by Andrew Victor
0008  *
0009  *  Ported to Linux 2.6 by Steven Scholz
0010  *  Based on s3c2410-rtc.c Simtec Electronics
0011  *
0012  *  Based on sa1100-rtc.c by Nils Faerber
0013  *  Based on rtc.c by Paul Gortmaker
0014  */
0015 
0016 #include <linux/bcd.h>
0017 #include <linux/bitfield.h>
0018 #include <linux/clk.h>
0019 #include <linux/completion.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/ioctl.h>
0022 #include <linux/io.h>
0023 #include <linux/kernel.h>
0024 #include <linux/module.h>
0025 #include <linux/of_device.h>
0026 #include <linux/of.h>
0027 #include <linux/platform_device.h>
0028 #include <linux/rtc.h>
0029 #include <linux/spinlock.h>
0030 #include <linux/suspend.h>
0031 #include <linux/time.h>
0032 #include <linux/uaccess.h>
0033 
0034 #define AT91_RTC_CR     0x00            /* Control Register */
0035 #define     AT91_RTC_UPDTIM     BIT(0)      /* Update Request Time Register */
0036 #define     AT91_RTC_UPDCAL     BIT(1)      /* Update Request Calendar Register */
0037 
0038 #define AT91_RTC_MR     0x04            /* Mode Register */
0039 #define     AT91_RTC_HRMOD      BIT(0)      /* 12/24 hour mode */
0040 #define     AT91_RTC_NEGPPM     BIT(4)      /* Negative PPM correction */
0041 #define     AT91_RTC_CORRECTION GENMASK(14, 8)  /* Slow clock correction */
0042 #define     AT91_RTC_HIGHPPM    BIT(15)     /* High PPM correction */
0043 
0044 #define AT91_RTC_TIMR       0x08            /* Time Register */
0045 #define     AT91_RTC_SEC        GENMASK(6, 0)   /* Current Second */
0046 #define     AT91_RTC_MIN        GENMASK(14, 8)  /* Current Minute */
0047 #define     AT91_RTC_HOUR       GENMASK(21, 16) /* Current Hour */
0048 #define     AT91_RTC_AMPM       BIT(22)     /* Ante Meridiem Post Meridiem Indicator */
0049 
0050 #define AT91_RTC_CALR       0x0c            /* Calendar Register */
0051 #define     AT91_RTC_CENT       GENMASK(6, 0)   /* Current Century */
0052 #define     AT91_RTC_YEAR       GENMASK(15, 8)  /* Current Year */
0053 #define     AT91_RTC_MONTH      GENMASK(20, 16) /* Current Month */
0054 #define     AT91_RTC_DAY        GENMASK(23, 21) /* Current Day */
0055 #define     AT91_RTC_DATE       GENMASK(29, 24) /* Current Date */
0056 
0057 #define AT91_RTC_TIMALR     0x10            /* Time Alarm Register */
0058 #define     AT91_RTC_SECEN      BIT(7)      /* Second Alarm Enable */
0059 #define     AT91_RTC_MINEN      BIT(15)     /* Minute Alarm Enable */
0060 #define     AT91_RTC_HOUREN     BIT(23)     /* Hour Alarm Enable */
0061 
0062 #define AT91_RTC_CALALR     0x14            /* Calendar Alarm Register */
0063 #define     AT91_RTC_MTHEN      BIT(23)     /* Month Alarm Enable */
0064 #define     AT91_RTC_DATEEN     BIT(31)     /* Date Alarm Enable */
0065 
0066 #define AT91_RTC_SR     0x18            /* Status Register */
0067 #define     AT91_RTC_ACKUPD     BIT(0)      /* Acknowledge for Update */
0068 #define     AT91_RTC_ALARM      BIT(1)      /* Alarm Flag */
0069 #define     AT91_RTC_SECEV      BIT(2)      /* Second Event */
0070 #define     AT91_RTC_TIMEV      BIT(3)      /* Time Event */
0071 #define     AT91_RTC_CALEV      BIT(4)      /* Calendar Event */
0072 
0073 #define AT91_RTC_SCCR       0x1c            /* Status Clear Command Register */
0074 #define AT91_RTC_IER        0x20            /* Interrupt Enable Register */
0075 #define AT91_RTC_IDR        0x24            /* Interrupt Disable Register */
0076 #define AT91_RTC_IMR        0x28            /* Interrupt Mask Register */
0077 
0078 #define AT91_RTC_VER        0x2c            /* Valid Entry Register */
0079 #define     AT91_RTC_NVTIM      BIT(0)      /* Non valid Time */
0080 #define     AT91_RTC_NVCAL      BIT(1)      /* Non valid Calendar */
0081 #define     AT91_RTC_NVTIMALR   BIT(2)      /* Non valid Time Alarm */
0082 #define     AT91_RTC_NVCALALR   BIT(3)      /* Non valid Calendar Alarm */
0083 
0084 #define AT91_RTC_CORR_DIVIDEND      3906000
0085 #define AT91_RTC_CORR_LOW_RATIO     20
0086 
0087 #define at91_rtc_read(field) \
0088     readl_relaxed(at91_rtc_regs + field)
0089 #define at91_rtc_write(field, val) \
0090     writel_relaxed((val), at91_rtc_regs + field)
0091 
0092 struct at91_rtc_config {
0093     bool use_shadow_imr;
0094     bool has_correction;
0095 };
0096 
0097 static const struct at91_rtc_config *at91_rtc_config;
0098 static DECLARE_COMPLETION(at91_rtc_updated);
0099 static DECLARE_COMPLETION(at91_rtc_upd_rdy);
0100 static void __iomem *at91_rtc_regs;
0101 static int irq;
0102 static DEFINE_SPINLOCK(at91_rtc_lock);
0103 static u32 at91_rtc_shadow_imr;
0104 static bool suspended;
0105 static DEFINE_SPINLOCK(suspended_lock);
0106 static unsigned long cached_events;
0107 static u32 at91_rtc_imr;
0108 static struct clk *sclk;
0109 
0110 static void at91_rtc_write_ier(u32 mask)
0111 {
0112     unsigned long flags;
0113 
0114     spin_lock_irqsave(&at91_rtc_lock, flags);
0115     at91_rtc_shadow_imr |= mask;
0116     at91_rtc_write(AT91_RTC_IER, mask);
0117     spin_unlock_irqrestore(&at91_rtc_lock, flags);
0118 }
0119 
0120 static void at91_rtc_write_idr(u32 mask)
0121 {
0122     unsigned long flags;
0123 
0124     spin_lock_irqsave(&at91_rtc_lock, flags);
0125     at91_rtc_write(AT91_RTC_IDR, mask);
0126     /*
0127      * Register read back (of any RTC-register) needed to make sure
0128      * IDR-register write has reached the peripheral before updating
0129      * shadow mask.
0130      *
0131      * Note that there is still a possibility that the mask is updated
0132      * before interrupts have actually been disabled in hardware. The only
0133      * way to be certain would be to poll the IMR-register, which is is
0134      * the very register we are trying to emulate. The register read back
0135      * is a reasonable heuristic.
0136      */
0137     at91_rtc_read(AT91_RTC_SR);
0138     at91_rtc_shadow_imr &= ~mask;
0139     spin_unlock_irqrestore(&at91_rtc_lock, flags);
0140 }
0141 
0142 static u32 at91_rtc_read_imr(void)
0143 {
0144     unsigned long flags;
0145     u32 mask;
0146 
0147     if (at91_rtc_config->use_shadow_imr) {
0148         spin_lock_irqsave(&at91_rtc_lock, flags);
0149         mask = at91_rtc_shadow_imr;
0150         spin_unlock_irqrestore(&at91_rtc_lock, flags);
0151     } else {
0152         mask = at91_rtc_read(AT91_RTC_IMR);
0153     }
0154 
0155     return mask;
0156 }
0157 
0158 /*
0159  * Decode time/date into rtc_time structure
0160  */
0161 static void at91_rtc_decodetime(unsigned int timereg, unsigned int calreg,
0162                 struct rtc_time *tm)
0163 {
0164     unsigned int time, date;
0165 
0166     /* must read twice in case it changes */
0167     do {
0168         time = at91_rtc_read(timereg);
0169         date = at91_rtc_read(calreg);
0170     } while ((time != at91_rtc_read(timereg)) ||
0171             (date != at91_rtc_read(calreg)));
0172 
0173     tm->tm_sec  = bcd2bin(FIELD_GET(AT91_RTC_SEC, time));
0174     tm->tm_min  = bcd2bin(FIELD_GET(AT91_RTC_MIN, time));
0175     tm->tm_hour = bcd2bin(FIELD_GET(AT91_RTC_HOUR, time));
0176 
0177     /*
0178      * The Calendar Alarm register does not have a field for
0179      * the year - so these will return an invalid value.
0180      */
0181     tm->tm_year  = bcd2bin(date & AT91_RTC_CENT) * 100; /* century */
0182     tm->tm_year += bcd2bin(FIELD_GET(AT91_RTC_YEAR, date)); /* year */
0183 
0184     tm->tm_wday = bcd2bin(FIELD_GET(AT91_RTC_DAY, date)) - 1;   /* day of the week [0-6], Sunday=0 */
0185     tm->tm_mon  = bcd2bin(FIELD_GET(AT91_RTC_MONTH, date)) - 1;
0186     tm->tm_mday = bcd2bin(FIELD_GET(AT91_RTC_DATE, date));
0187 }
0188 
0189 /*
0190  * Read current time and date in RTC
0191  */
0192 static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
0193 {
0194     at91_rtc_decodetime(AT91_RTC_TIMR, AT91_RTC_CALR, tm);
0195     tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
0196     tm->tm_year = tm->tm_year - 1900;
0197 
0198     dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
0199 
0200     return 0;
0201 }
0202 
0203 /*
0204  * Set current time and date in RTC
0205  */
0206 static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
0207 {
0208     unsigned long cr;
0209 
0210     dev_dbg(dev, "%s(): %ptR\n", __func__, tm);
0211 
0212     wait_for_completion(&at91_rtc_upd_rdy);
0213 
0214     /* Stop Time/Calendar from counting */
0215     cr = at91_rtc_read(AT91_RTC_CR);
0216     at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
0217 
0218     at91_rtc_write_ier(AT91_RTC_ACKUPD);
0219     wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
0220     at91_rtc_write_idr(AT91_RTC_ACKUPD);
0221 
0222     at91_rtc_write(AT91_RTC_TIMR,
0223               FIELD_PREP(AT91_RTC_SEC, bin2bcd(tm->tm_sec))
0224             | FIELD_PREP(AT91_RTC_MIN, bin2bcd(tm->tm_min))
0225             | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(tm->tm_hour)));
0226 
0227     at91_rtc_write(AT91_RTC_CALR,
0228               FIELD_PREP(AT91_RTC_CENT,
0229                      bin2bcd((tm->tm_year + 1900) / 100))
0230             | FIELD_PREP(AT91_RTC_YEAR, bin2bcd(tm->tm_year % 100))
0231             | FIELD_PREP(AT91_RTC_MONTH, bin2bcd(tm->tm_mon + 1))
0232             | FIELD_PREP(AT91_RTC_DAY, bin2bcd(tm->tm_wday + 1))
0233             | FIELD_PREP(AT91_RTC_DATE, bin2bcd(tm->tm_mday)));
0234 
0235     /* Restart Time/Calendar */
0236     cr = at91_rtc_read(AT91_RTC_CR);
0237     at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_SECEV);
0238     at91_rtc_write(AT91_RTC_CR, cr & ~(AT91_RTC_UPDCAL | AT91_RTC_UPDTIM));
0239     at91_rtc_write_ier(AT91_RTC_SECEV);
0240 
0241     return 0;
0242 }
0243 
0244 /*
0245  * Read alarm time and date in RTC
0246  */
0247 static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
0248 {
0249     struct rtc_time *tm = &alrm->time;
0250 
0251     at91_rtc_decodetime(AT91_RTC_TIMALR, AT91_RTC_CALALR, tm);
0252     tm->tm_year = -1;
0253 
0254     alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
0255             ? 1 : 0;
0256 
0257     dev_dbg(dev, "%s(): %ptR %sabled\n", __func__, tm,
0258         alrm->enabled ? "en" : "dis");
0259 
0260     return 0;
0261 }
0262 
0263 /*
0264  * Set alarm time and date in RTC
0265  */
0266 static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
0267 {
0268     struct rtc_time tm = alrm->time;
0269 
0270     at91_rtc_write_idr(AT91_RTC_ALARM);
0271     at91_rtc_write(AT91_RTC_TIMALR,
0272           FIELD_PREP(AT91_RTC_SEC, bin2bcd(alrm->time.tm_sec))
0273         | FIELD_PREP(AT91_RTC_MIN, bin2bcd(alrm->time.tm_min))
0274         | FIELD_PREP(AT91_RTC_HOUR, bin2bcd(alrm->time.tm_hour))
0275         | AT91_RTC_HOUREN | AT91_RTC_MINEN | AT91_RTC_SECEN);
0276     at91_rtc_write(AT91_RTC_CALALR,
0277           FIELD_PREP(AT91_RTC_MONTH, bin2bcd(alrm->time.tm_mon + 1))
0278         | FIELD_PREP(AT91_RTC_DATE, bin2bcd(alrm->time.tm_mday))
0279         | AT91_RTC_DATEEN | AT91_RTC_MTHEN);
0280 
0281     if (alrm->enabled) {
0282         at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
0283         at91_rtc_write_ier(AT91_RTC_ALARM);
0284     }
0285 
0286     dev_dbg(dev, "%s(): %ptR\n", __func__, &tm);
0287 
0288     return 0;
0289 }
0290 
0291 static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
0292 {
0293     dev_dbg(dev, "%s(): cmd=%08x\n", __func__, enabled);
0294 
0295     if (enabled) {
0296         at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
0297         at91_rtc_write_ier(AT91_RTC_ALARM);
0298     } else
0299         at91_rtc_write_idr(AT91_RTC_ALARM);
0300 
0301     return 0;
0302 }
0303 
0304 static int at91_rtc_readoffset(struct device *dev, long *offset)
0305 {
0306     u32 mr = at91_rtc_read(AT91_RTC_MR);
0307     long val = FIELD_GET(AT91_RTC_CORRECTION, mr);
0308 
0309     if (!val) {
0310         *offset = 0;
0311         return 0;
0312     }
0313 
0314     val++;
0315 
0316     if (!(mr & AT91_RTC_NEGPPM))
0317         val = -val;
0318 
0319     if (!(mr & AT91_RTC_HIGHPPM))
0320         val *= AT91_RTC_CORR_LOW_RATIO;
0321 
0322     *offset = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, val);
0323 
0324     return 0;
0325 }
0326 
0327 static int at91_rtc_setoffset(struct device *dev, long offset)
0328 {
0329     long corr;
0330     u32 mr;
0331 
0332     if (offset > AT91_RTC_CORR_DIVIDEND / 2)
0333         return -ERANGE;
0334     if (offset < -AT91_RTC_CORR_DIVIDEND / 2)
0335         return -ERANGE;
0336 
0337     mr = at91_rtc_read(AT91_RTC_MR);
0338     mr &= ~(AT91_RTC_NEGPPM | AT91_RTC_CORRECTION | AT91_RTC_HIGHPPM);
0339 
0340     if (offset > 0)
0341         mr |= AT91_RTC_NEGPPM;
0342     else
0343         offset = -offset;
0344 
0345     /* offset less than 764 ppb, disable correction*/
0346     if (offset < 764) {
0347         at91_rtc_write(AT91_RTC_MR, mr & ~AT91_RTC_NEGPPM);
0348 
0349         return 0;
0350     }
0351 
0352     /*
0353      * 29208 ppb is the perfect cutoff between low range and high range
0354      * low range values are never better than high range value after that.
0355      */
0356     if (offset < 29208) {
0357         corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset * AT91_RTC_CORR_LOW_RATIO);
0358     } else {
0359         corr = DIV_ROUND_CLOSEST(AT91_RTC_CORR_DIVIDEND, offset);
0360         mr |= AT91_RTC_HIGHPPM;
0361     }
0362 
0363     if (corr > 128)
0364         corr = 128;
0365 
0366     mr |= FIELD_PREP(AT91_RTC_CORRECTION, corr - 1);
0367 
0368     at91_rtc_write(AT91_RTC_MR, mr);
0369 
0370     return 0;
0371 }
0372 
0373 /*
0374  * IRQ handler for the RTC
0375  */
0376 static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
0377 {
0378     struct platform_device *pdev = dev_id;
0379     struct rtc_device *rtc = platform_get_drvdata(pdev);
0380     unsigned int rtsr;
0381     unsigned long events = 0;
0382     int ret = IRQ_NONE;
0383 
0384     spin_lock(&suspended_lock);
0385     rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
0386     if (rtsr) {     /* this interrupt is shared!  Is it ours? */
0387         if (rtsr & AT91_RTC_ALARM)
0388             events |= (RTC_AF | RTC_IRQF);
0389         if (rtsr & AT91_RTC_SECEV) {
0390             complete(&at91_rtc_upd_rdy);
0391             at91_rtc_write_idr(AT91_RTC_SECEV);
0392         }
0393         if (rtsr & AT91_RTC_ACKUPD)
0394             complete(&at91_rtc_updated);
0395 
0396         at91_rtc_write(AT91_RTC_SCCR, rtsr);    /* clear status reg */
0397 
0398         if (!suspended) {
0399             rtc_update_irq(rtc, 1, events);
0400 
0401             dev_dbg(&pdev->dev, "%s(): num=%ld, events=0x%02lx\n",
0402                 __func__, events >> 8, events & 0x000000FF);
0403         } else {
0404             cached_events |= events;
0405             at91_rtc_write_idr(at91_rtc_imr);
0406             pm_system_wakeup();
0407         }
0408 
0409         ret = IRQ_HANDLED;
0410     }
0411     spin_unlock(&suspended_lock);
0412 
0413     return ret;
0414 }
0415 
0416 static const struct at91_rtc_config at91rm9200_config = {
0417 };
0418 
0419 static const struct at91_rtc_config at91sam9x5_config = {
0420     .use_shadow_imr = true,
0421 };
0422 
0423 static const struct at91_rtc_config sama5d4_config = {
0424     .has_correction = true,
0425 };
0426 
0427 static const struct of_device_id at91_rtc_dt_ids[] = {
0428     {
0429         .compatible = "atmel,at91rm9200-rtc",
0430         .data = &at91rm9200_config,
0431     }, {
0432         .compatible = "atmel,at91sam9x5-rtc",
0433         .data = &at91sam9x5_config,
0434     }, {
0435         .compatible = "atmel,sama5d4-rtc",
0436         .data = &sama5d4_config,
0437     }, {
0438         .compatible = "atmel,sama5d2-rtc",
0439         .data = &sama5d4_config,
0440     }, {
0441         .compatible = "microchip,sam9x60-rtc",
0442         .data = &sama5d4_config,
0443     }, {
0444         /* sentinel */
0445     }
0446 };
0447 MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
0448 
0449 static const struct rtc_class_ops at91_rtc_ops = {
0450     .read_time  = at91_rtc_readtime,
0451     .set_time   = at91_rtc_settime,
0452     .read_alarm = at91_rtc_readalarm,
0453     .set_alarm  = at91_rtc_setalarm,
0454     .alarm_irq_enable = at91_rtc_alarm_irq_enable,
0455 };
0456 
0457 static const struct rtc_class_ops sama5d4_rtc_ops = {
0458     .read_time  = at91_rtc_readtime,
0459     .set_time   = at91_rtc_settime,
0460     .read_alarm = at91_rtc_readalarm,
0461     .set_alarm  = at91_rtc_setalarm,
0462     .alarm_irq_enable = at91_rtc_alarm_irq_enable,
0463     .set_offset = at91_rtc_setoffset,
0464     .read_offset    = at91_rtc_readoffset,
0465 };
0466 
0467 /*
0468  * Initialize and install RTC driver
0469  */
0470 static int __init at91_rtc_probe(struct platform_device *pdev)
0471 {
0472     struct rtc_device *rtc;
0473     struct resource *regs;
0474     int ret = 0;
0475 
0476     at91_rtc_config = of_device_get_match_data(&pdev->dev);
0477     if (!at91_rtc_config)
0478         return -ENODEV;
0479 
0480     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0481     if (!regs) {
0482         dev_err(&pdev->dev, "no mmio resource defined\n");
0483         return -ENXIO;
0484     }
0485 
0486     irq = platform_get_irq(pdev, 0);
0487     if (irq < 0)
0488         return -ENXIO;
0489 
0490     at91_rtc_regs = devm_ioremap(&pdev->dev, regs->start,
0491                      resource_size(regs));
0492     if (!at91_rtc_regs) {
0493         dev_err(&pdev->dev, "failed to map registers, aborting.\n");
0494         return -ENOMEM;
0495     }
0496 
0497     rtc = devm_rtc_allocate_device(&pdev->dev);
0498     if (IS_ERR(rtc))
0499         return PTR_ERR(rtc);
0500     platform_set_drvdata(pdev, rtc);
0501 
0502     sclk = devm_clk_get(&pdev->dev, NULL);
0503     if (IS_ERR(sclk))
0504         return PTR_ERR(sclk);
0505 
0506     ret = clk_prepare_enable(sclk);
0507     if (ret) {
0508         dev_err(&pdev->dev, "Could not enable slow clock\n");
0509         return ret;
0510     }
0511 
0512     at91_rtc_write(AT91_RTC_CR, 0);
0513     at91_rtc_write(AT91_RTC_MR, at91_rtc_read(AT91_RTC_MR) & ~AT91_RTC_HRMOD);
0514 
0515     /* Disable all interrupts */
0516     at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
0517                     AT91_RTC_SECEV | AT91_RTC_TIMEV |
0518                     AT91_RTC_CALEV);
0519 
0520     ret = devm_request_irq(&pdev->dev, irq, at91_rtc_interrupt,
0521                    IRQF_SHARED | IRQF_COND_SUSPEND,
0522                    "at91_rtc", pdev);
0523     if (ret) {
0524         dev_err(&pdev->dev, "IRQ %d already in use.\n", irq);
0525         goto err_clk;
0526     }
0527 
0528     /* cpu init code should really have flagged this device as
0529      * being wake-capable; if it didn't, do that here.
0530      */
0531     if (!device_can_wakeup(&pdev->dev))
0532         device_init_wakeup(&pdev->dev, 1);
0533 
0534     if (at91_rtc_config->has_correction)
0535         rtc->ops = &sama5d4_rtc_ops;
0536     else
0537         rtc->ops = &at91_rtc_ops;
0538 
0539     rtc->range_min = RTC_TIMESTAMP_BEGIN_1900;
0540     rtc->range_max = RTC_TIMESTAMP_END_2099;
0541     ret = devm_rtc_register_device(rtc);
0542     if (ret)
0543         goto err_clk;
0544 
0545     /* enable SECEV interrupt in order to initialize at91_rtc_upd_rdy
0546      * completion.
0547      */
0548     at91_rtc_write_ier(AT91_RTC_SECEV);
0549 
0550     dev_info(&pdev->dev, "AT91 Real Time Clock driver.\n");
0551     return 0;
0552 
0553 err_clk:
0554     clk_disable_unprepare(sclk);
0555 
0556     return ret;
0557 }
0558 
0559 /*
0560  * Disable and remove the RTC driver
0561  */
0562 static int __exit at91_rtc_remove(struct platform_device *pdev)
0563 {
0564     /* Disable all interrupts */
0565     at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
0566                     AT91_RTC_SECEV | AT91_RTC_TIMEV |
0567                     AT91_RTC_CALEV);
0568 
0569     clk_disable_unprepare(sclk);
0570 
0571     return 0;
0572 }
0573 
0574 static void at91_rtc_shutdown(struct platform_device *pdev)
0575 {
0576     /* Disable all interrupts */
0577     at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
0578                     AT91_RTC_SECEV | AT91_RTC_TIMEV |
0579                     AT91_RTC_CALEV);
0580 }
0581 
0582 #ifdef CONFIG_PM_SLEEP
0583 
0584 /* AT91RM9200 RTC Power management control */
0585 
0586 static int at91_rtc_suspend(struct device *dev)
0587 {
0588     /* this IRQ is shared with DBGU and other hardware which isn't
0589      * necessarily doing PM like we are...
0590      */
0591     at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
0592 
0593     at91_rtc_imr = at91_rtc_read_imr()
0594             & (AT91_RTC_ALARM|AT91_RTC_SECEV);
0595     if (at91_rtc_imr) {
0596         if (device_may_wakeup(dev)) {
0597             unsigned long flags;
0598 
0599             enable_irq_wake(irq);
0600 
0601             spin_lock_irqsave(&suspended_lock, flags);
0602             suspended = true;
0603             spin_unlock_irqrestore(&suspended_lock, flags);
0604         } else {
0605             at91_rtc_write_idr(at91_rtc_imr);
0606         }
0607     }
0608     return 0;
0609 }
0610 
0611 static int at91_rtc_resume(struct device *dev)
0612 {
0613     struct rtc_device *rtc = dev_get_drvdata(dev);
0614 
0615     if (at91_rtc_imr) {
0616         if (device_may_wakeup(dev)) {
0617             unsigned long flags;
0618 
0619             spin_lock_irqsave(&suspended_lock, flags);
0620 
0621             if (cached_events) {
0622                 rtc_update_irq(rtc, 1, cached_events);
0623                 cached_events = 0;
0624             }
0625 
0626             suspended = false;
0627             spin_unlock_irqrestore(&suspended_lock, flags);
0628 
0629             disable_irq_wake(irq);
0630         }
0631         at91_rtc_write_ier(at91_rtc_imr);
0632     }
0633     return 0;
0634 }
0635 #endif
0636 
0637 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
0638 
0639 static struct platform_driver at91_rtc_driver = {
0640     .remove     = __exit_p(at91_rtc_remove),
0641     .shutdown   = at91_rtc_shutdown,
0642     .driver     = {
0643         .name   = "at91_rtc",
0644         .pm = &at91_rtc_pm_ops,
0645         .of_match_table = of_match_ptr(at91_rtc_dt_ids),
0646     },
0647 };
0648 
0649 module_platform_driver_probe(at91_rtc_driver, at91_rtc_probe);
0650 
0651 MODULE_AUTHOR("Rick Bronson");
0652 MODULE_DESCRIPTION("RTC driver for Atmel AT91RM9200");
0653 MODULE_LICENSE("GPL");
0654 MODULE_ALIAS("platform:at91_rtc");
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