Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * RTC driver for the Armada 38x Marvell SoCs
0004  *
0005  * Copyright (C) 2015 Marvell
0006  *
0007  * Gregory Clement <gregory.clement@free-electrons.com>
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/rtc.h>
0017 
0018 #define RTC_STATUS      0x0
0019 #define RTC_STATUS_ALARM1       BIT(0)
0020 #define RTC_STATUS_ALARM2       BIT(1)
0021 #define RTC_IRQ1_CONF       0x4
0022 #define RTC_IRQ2_CONF       0x8
0023 #define RTC_IRQ_AL_EN           BIT(0)
0024 #define RTC_IRQ_FREQ_EN         BIT(1)
0025 #define RTC_IRQ_FREQ_1HZ        BIT(2)
0026 #define RTC_CCR         0x18
0027 #define RTC_CCR_MODE            BIT(15)
0028 #define RTC_CONF_TEST       0x1C
0029 #define RTC_NOMINAL_TIMING      BIT(13)
0030 
0031 #define RTC_TIME        0xC
0032 #define RTC_ALARM1      0x10
0033 #define RTC_ALARM2      0x14
0034 
0035 /* Armada38x SoC registers  */
0036 #define RTC_38X_BRIDGE_TIMING_CTL   0x0
0037 #define RTC_38X_PERIOD_OFFS     0
0038 #define RTC_38X_PERIOD_MASK     (0x3FF << RTC_38X_PERIOD_OFFS)
0039 #define RTC_38X_READ_DELAY_OFFS     26
0040 #define RTC_38X_READ_DELAY_MASK     (0x1F << RTC_38X_READ_DELAY_OFFS)
0041 
0042 /* Armada 7K/8K registers  */
0043 #define RTC_8K_BRIDGE_TIMING_CTL0    0x0
0044 #define RTC_8K_WRCLK_PERIOD_OFFS    0
0045 #define RTC_8K_WRCLK_PERIOD_MASK    (0xFFFF << RTC_8K_WRCLK_PERIOD_OFFS)
0046 #define RTC_8K_WRCLK_SETUP_OFFS     16
0047 #define RTC_8K_WRCLK_SETUP_MASK     (0xFFFF << RTC_8K_WRCLK_SETUP_OFFS)
0048 #define RTC_8K_BRIDGE_TIMING_CTL1   0x4
0049 #define RTC_8K_READ_DELAY_OFFS      0
0050 #define RTC_8K_READ_DELAY_MASK      (0xFFFF << RTC_8K_READ_DELAY_OFFS)
0051 
0052 #define RTC_8K_ISR          0x10
0053 #define RTC_8K_IMR          0x14
0054 #define RTC_8K_ALARM2           BIT(0)
0055 
0056 #define SOC_RTC_INTERRUPT       0x8
0057 #define SOC_RTC_ALARM1          BIT(0)
0058 #define SOC_RTC_ALARM2          BIT(1)
0059 #define SOC_RTC_ALARM1_MASK     BIT(2)
0060 #define SOC_RTC_ALARM2_MASK     BIT(3)
0061 
0062 #define SAMPLE_NR 100
0063 
0064 struct value_to_freq {
0065     u32 value;
0066     u8 freq;
0067 };
0068 
0069 struct armada38x_rtc {
0070     struct rtc_device   *rtc_dev;
0071     void __iomem        *regs;
0072     void __iomem        *regs_soc;
0073     spinlock_t      lock;
0074     int         irq;
0075     bool            initialized;
0076     struct value_to_freq *val_to_freq;
0077     const struct armada38x_rtc_data *data;
0078 };
0079 
0080 #define ALARM1  0
0081 #define ALARM2  1
0082 
0083 #define ALARM_REG(base, alarm)   ((base) + (alarm) * sizeof(u32))
0084 
0085 struct armada38x_rtc_data {
0086     /* Initialize the RTC-MBUS bridge timing */
0087     void (*update_mbus_timing)(struct armada38x_rtc *rtc);
0088     u32 (*read_rtc_reg)(struct armada38x_rtc *rtc, u8 rtc_reg);
0089     void (*clear_isr)(struct armada38x_rtc *rtc);
0090     void (*unmask_interrupt)(struct armada38x_rtc *rtc);
0091     u32 alarm;
0092 };
0093 
0094 /*
0095  * According to the datasheet, the OS should wait 5us after every
0096  * register write to the RTC hard macro so that the required update
0097  * can occur without holding off the system bus
0098  * According to errata RES-3124064, Write to any RTC register
0099  * may fail. As a workaround, before writing to RTC
0100  * register, issue a dummy write of 0x0 twice to RTC Status
0101  * register.
0102  */
0103 
0104 static void rtc_delayed_write(u32 val, struct armada38x_rtc *rtc, int offset)
0105 {
0106     writel(0, rtc->regs + RTC_STATUS);
0107     writel(0, rtc->regs + RTC_STATUS);
0108     writel(val, rtc->regs + offset);
0109     udelay(5);
0110 }
0111 
0112 /* Update RTC-MBUS bridge timing parameters */
0113 static void rtc_update_38x_mbus_timing_params(struct armada38x_rtc *rtc)
0114 {
0115     u32 reg;
0116 
0117     reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
0118     reg &= ~RTC_38X_PERIOD_MASK;
0119     reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */
0120     reg &= ~RTC_38X_READ_DELAY_MASK;
0121     reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */
0122     writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL);
0123 }
0124 
0125 static void rtc_update_8k_mbus_timing_params(struct armada38x_rtc *rtc)
0126 {
0127     u32 reg;
0128 
0129     reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
0130     reg &= ~RTC_8K_WRCLK_PERIOD_MASK;
0131     reg |= 0x3FF << RTC_8K_WRCLK_PERIOD_OFFS;
0132     reg &= ~RTC_8K_WRCLK_SETUP_MASK;
0133     reg |= 0x29 << RTC_8K_WRCLK_SETUP_OFFS;
0134     writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL0);
0135 
0136     reg = readl(rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
0137     reg &= ~RTC_8K_READ_DELAY_MASK;
0138     reg |= 0x3F << RTC_8K_READ_DELAY_OFFS;
0139     writel(reg, rtc->regs_soc + RTC_8K_BRIDGE_TIMING_CTL1);
0140 }
0141 
0142 static u32 read_rtc_register(struct armada38x_rtc *rtc, u8 rtc_reg)
0143 {
0144     return readl(rtc->regs + rtc_reg);
0145 }
0146 
0147 static u32 read_rtc_register_38x_wa(struct armada38x_rtc *rtc, u8 rtc_reg)
0148 {
0149     int i, index_max = 0, max = 0;
0150 
0151     for (i = 0; i < SAMPLE_NR; i++) {
0152         rtc->val_to_freq[i].value = readl(rtc->regs + rtc_reg);
0153         rtc->val_to_freq[i].freq = 0;
0154     }
0155 
0156     for (i = 0; i < SAMPLE_NR; i++) {
0157         int j = 0;
0158         u32 value = rtc->val_to_freq[i].value;
0159 
0160         while (rtc->val_to_freq[j].freq) {
0161             if (rtc->val_to_freq[j].value == value) {
0162                 rtc->val_to_freq[j].freq++;
0163                 break;
0164             }
0165             j++;
0166         }
0167 
0168         if (!rtc->val_to_freq[j].freq) {
0169             rtc->val_to_freq[j].value = value;
0170             rtc->val_to_freq[j].freq = 1;
0171         }
0172 
0173         if (rtc->val_to_freq[j].freq > max) {
0174             index_max = j;
0175             max = rtc->val_to_freq[j].freq;
0176         }
0177 
0178         /*
0179          * If a value already has half of the sample this is the most
0180          * frequent one and we can stop the research right now
0181          */
0182         if (max > SAMPLE_NR / 2)
0183             break;
0184     }
0185 
0186     return rtc->val_to_freq[index_max].value;
0187 }
0188 
0189 static void armada38x_clear_isr(struct armada38x_rtc *rtc)
0190 {
0191     u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
0192 
0193     writel(val & ~SOC_RTC_ALARM1, rtc->regs_soc + SOC_RTC_INTERRUPT);
0194 }
0195 
0196 static void armada38x_unmask_interrupt(struct armada38x_rtc *rtc)
0197 {
0198     u32 val = readl(rtc->regs_soc + SOC_RTC_INTERRUPT);
0199 
0200     writel(val | SOC_RTC_ALARM1_MASK, rtc->regs_soc + SOC_RTC_INTERRUPT);
0201 }
0202 
0203 static void armada8k_clear_isr(struct armada38x_rtc *rtc)
0204 {
0205     writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_ISR);
0206 }
0207 
0208 static void armada8k_unmask_interrupt(struct armada38x_rtc *rtc)
0209 {
0210     writel(RTC_8K_ALARM2, rtc->regs_soc + RTC_8K_IMR);
0211 }
0212 
0213 static int armada38x_rtc_read_time(struct device *dev, struct rtc_time *tm)
0214 {
0215     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0216     unsigned long time, flags;
0217 
0218     spin_lock_irqsave(&rtc->lock, flags);
0219     time = rtc->data->read_rtc_reg(rtc, RTC_TIME);
0220     spin_unlock_irqrestore(&rtc->lock, flags);
0221 
0222     rtc_time64_to_tm(time, tm);
0223 
0224     return 0;
0225 }
0226 
0227 static void armada38x_rtc_reset(struct armada38x_rtc *rtc)
0228 {
0229     u32 reg;
0230 
0231     reg = rtc->data->read_rtc_reg(rtc, RTC_CONF_TEST);
0232     /* If bits [7:0] are non-zero, assume RTC was uninitialized */
0233     if (reg & 0xff) {
0234         rtc_delayed_write(0, rtc, RTC_CONF_TEST);
0235         msleep(500); /* Oscillator startup time */
0236         rtc_delayed_write(0, rtc, RTC_TIME);
0237         rtc_delayed_write(SOC_RTC_ALARM1 | SOC_RTC_ALARM2, rtc,
0238                   RTC_STATUS);
0239         rtc_delayed_write(RTC_NOMINAL_TIMING, rtc, RTC_CCR);
0240     }
0241     rtc->initialized = true;
0242 }
0243 
0244 static int armada38x_rtc_set_time(struct device *dev, struct rtc_time *tm)
0245 {
0246     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0247     unsigned long time, flags;
0248 
0249     time = rtc_tm_to_time64(tm);
0250 
0251     if (!rtc->initialized)
0252         armada38x_rtc_reset(rtc);
0253 
0254     spin_lock_irqsave(&rtc->lock, flags);
0255     rtc_delayed_write(time, rtc, RTC_TIME);
0256     spin_unlock_irqrestore(&rtc->lock, flags);
0257 
0258     return 0;
0259 }
0260 
0261 static int armada38x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0262 {
0263     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0264     unsigned long time, flags;
0265     u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
0266     u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
0267     u32 val;
0268 
0269     spin_lock_irqsave(&rtc->lock, flags);
0270 
0271     time = rtc->data->read_rtc_reg(rtc, reg);
0272     val = rtc->data->read_rtc_reg(rtc, reg_irq) & RTC_IRQ_AL_EN;
0273 
0274     spin_unlock_irqrestore(&rtc->lock, flags);
0275 
0276     alrm->enabled = val ? 1 : 0;
0277     rtc_time64_to_tm(time,  &alrm->time);
0278 
0279     return 0;
0280 }
0281 
0282 static int armada38x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
0283 {
0284     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0285     u32 reg = ALARM_REG(RTC_ALARM1, rtc->data->alarm);
0286     u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
0287     unsigned long time, flags;
0288 
0289     time = rtc_tm_to_time64(&alrm->time);
0290 
0291     spin_lock_irqsave(&rtc->lock, flags);
0292 
0293     rtc_delayed_write(time, rtc, reg);
0294 
0295     if (alrm->enabled) {
0296         rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
0297         rtc->data->unmask_interrupt(rtc);
0298     }
0299 
0300     spin_unlock_irqrestore(&rtc->lock, flags);
0301 
0302     return 0;
0303 }
0304 
0305 static int armada38x_rtc_alarm_irq_enable(struct device *dev,
0306                      unsigned int enabled)
0307 {
0308     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0309     u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
0310     unsigned long flags;
0311 
0312     spin_lock_irqsave(&rtc->lock, flags);
0313 
0314     if (enabled)
0315         rtc_delayed_write(RTC_IRQ_AL_EN, rtc, reg_irq);
0316     else
0317         rtc_delayed_write(0, rtc, reg_irq);
0318 
0319     spin_unlock_irqrestore(&rtc->lock, flags);
0320 
0321     return 0;
0322 }
0323 
0324 static irqreturn_t armada38x_rtc_alarm_irq(int irq, void *data)
0325 {
0326     struct armada38x_rtc *rtc = data;
0327     u32 val;
0328     int event = RTC_IRQF | RTC_AF;
0329     u32 reg_irq = ALARM_REG(RTC_IRQ1_CONF, rtc->data->alarm);
0330 
0331     dev_dbg(&rtc->rtc_dev->dev, "%s:irq(%d)\n", __func__, irq);
0332 
0333     spin_lock(&rtc->lock);
0334 
0335     rtc->data->clear_isr(rtc);
0336     val = rtc->data->read_rtc_reg(rtc, reg_irq);
0337     /* disable all the interrupts for alarm*/
0338     rtc_delayed_write(0, rtc, reg_irq);
0339     /* Ack the event */
0340     rtc_delayed_write(1 << rtc->data->alarm, rtc, RTC_STATUS);
0341 
0342     spin_unlock(&rtc->lock);
0343 
0344     if (val & RTC_IRQ_FREQ_EN) {
0345         if (val & RTC_IRQ_FREQ_1HZ)
0346             event |= RTC_UF;
0347         else
0348             event |= RTC_PF;
0349     }
0350 
0351     rtc_update_irq(rtc->rtc_dev, 1, event);
0352 
0353     return IRQ_HANDLED;
0354 }
0355 
0356 /*
0357  * The information given in the Armada 388 functional spec is complex.
0358  * They give two different formulas for calculating the offset value,
0359  * but when considering "Offset" as an 8-bit signed integer, they both
0360  * reduce down to (we shall rename "Offset" as "val" here):
0361  *
0362  *   val = (f_ideal / f_measured - 1) / resolution   where f_ideal = 32768
0363  *
0364  * Converting to time, f = 1/t:
0365  *   val = (t_measured / t_ideal - 1) / resolution   where t_ideal = 1/32768
0366  *
0367  *   =>  t_measured / t_ideal = val * resolution + 1
0368  *
0369  * "offset" in the RTC interface is defined as:
0370  *   t = t0 * (1 + offset * 1e-9)
0371  * where t is the desired period, t0 is the measured period with a zero
0372  * offset, which is t_measured above. With t0 = t_measured and t = t_ideal,
0373  *   offset = (t_ideal / t_measured - 1) / 1e-9
0374  *
0375  *   => t_ideal / t_measured = offset * 1e-9 + 1
0376  *
0377  * so:
0378  *
0379  *   offset * 1e-9 + 1 = 1 / (val * resolution + 1)
0380  *
0381  * We want "resolution" to be an integer, so resolution = R * 1e-9, giving
0382  *   offset = 1e18 / (val * R + 1e9) - 1e9
0383  *   val = (1e18 / (offset + 1e9) - 1e9) / R
0384  * with a common transformation:
0385  *   f(x) = 1e18 / (x + 1e9) - 1e9
0386  *   offset = f(val * R)
0387  *   val = f(offset) / R
0388  *
0389  * Armada 38x supports two modes, fine mode (954ppb) and coarse mode (3815ppb).
0390  */
0391 static long armada38x_ppb_convert(long ppb)
0392 {
0393     long div = ppb + 1000000000L;
0394 
0395     return div_s64(1000000000000000000LL + div / 2, div) - 1000000000L;
0396 }
0397 
0398 static int armada38x_rtc_read_offset(struct device *dev, long *offset)
0399 {
0400     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0401     unsigned long ccr, flags;
0402     long ppb_cor;
0403 
0404     spin_lock_irqsave(&rtc->lock, flags);
0405     ccr = rtc->data->read_rtc_reg(rtc, RTC_CCR);
0406     spin_unlock_irqrestore(&rtc->lock, flags);
0407 
0408     ppb_cor = (ccr & RTC_CCR_MODE ? 3815 : 954) * (s8)ccr;
0409     /* ppb_cor + 1000000000L can never be zero */
0410     *offset = armada38x_ppb_convert(ppb_cor);
0411 
0412     return 0;
0413 }
0414 
0415 static int armada38x_rtc_set_offset(struct device *dev, long offset)
0416 {
0417     struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0418     unsigned long ccr = 0;
0419     long ppb_cor, off;
0420 
0421     /*
0422      * The maximum ppb_cor is -128 * 3815 .. 127 * 3815, but we
0423      * need to clamp the input.  This equates to -484270 .. 488558.
0424      * Not only is this to stop out of range "off" but also to
0425      * avoid the division by zero in armada38x_ppb_convert().
0426      */
0427     offset = clamp(offset, -484270L, 488558L);
0428 
0429     ppb_cor = armada38x_ppb_convert(offset);
0430 
0431     /*
0432      * Use low update mode where possible, which gives a better
0433      * resolution of correction.
0434      */
0435     off = DIV_ROUND_CLOSEST(ppb_cor, 954);
0436     if (off > 127 || off < -128) {
0437         ccr = RTC_CCR_MODE;
0438         off = DIV_ROUND_CLOSEST(ppb_cor, 3815);
0439     }
0440 
0441     /*
0442      * Armada 388 requires a bit pattern in bits 14..8 depending on
0443      * the sign bit: { 0, ~S, S, S, S, S, S }
0444      */
0445     ccr |= (off & 0x3fff) ^ 0x2000;
0446     rtc_delayed_write(ccr, rtc, RTC_CCR);
0447 
0448     return 0;
0449 }
0450 
0451 static const struct rtc_class_ops armada38x_rtc_ops = {
0452     .read_time = armada38x_rtc_read_time,
0453     .set_time = armada38x_rtc_set_time,
0454     .read_alarm = armada38x_rtc_read_alarm,
0455     .set_alarm = armada38x_rtc_set_alarm,
0456     .alarm_irq_enable = armada38x_rtc_alarm_irq_enable,
0457     .read_offset = armada38x_rtc_read_offset,
0458     .set_offset = armada38x_rtc_set_offset,
0459 };
0460 
0461 static const struct armada38x_rtc_data armada38x_data = {
0462     .update_mbus_timing = rtc_update_38x_mbus_timing_params,
0463     .read_rtc_reg = read_rtc_register_38x_wa,
0464     .clear_isr = armada38x_clear_isr,
0465     .unmask_interrupt = armada38x_unmask_interrupt,
0466     .alarm = ALARM1,
0467 };
0468 
0469 static const struct armada38x_rtc_data armada8k_data = {
0470     .update_mbus_timing = rtc_update_8k_mbus_timing_params,
0471     .read_rtc_reg = read_rtc_register,
0472     .clear_isr = armada8k_clear_isr,
0473     .unmask_interrupt = armada8k_unmask_interrupt,
0474     .alarm = ALARM2,
0475 };
0476 
0477 #ifdef CONFIG_OF
0478 static const struct of_device_id armada38x_rtc_of_match_table[] = {
0479     {
0480         .compatible = "marvell,armada-380-rtc",
0481         .data = &armada38x_data,
0482     },
0483     {
0484         .compatible = "marvell,armada-8k-rtc",
0485         .data = &armada8k_data,
0486     },
0487     {}
0488 };
0489 MODULE_DEVICE_TABLE(of, armada38x_rtc_of_match_table);
0490 #endif
0491 
0492 static __init int armada38x_rtc_probe(struct platform_device *pdev)
0493 {
0494     struct resource *res;
0495     struct armada38x_rtc *rtc;
0496 
0497     rtc = devm_kzalloc(&pdev->dev, sizeof(struct armada38x_rtc),
0498                 GFP_KERNEL);
0499     if (!rtc)
0500         return -ENOMEM;
0501 
0502     rtc->data = of_device_get_match_data(&pdev->dev);
0503 
0504     rtc->val_to_freq = devm_kcalloc(&pdev->dev, SAMPLE_NR,
0505                 sizeof(struct value_to_freq), GFP_KERNEL);
0506     if (!rtc->val_to_freq)
0507         return -ENOMEM;
0508 
0509     spin_lock_init(&rtc->lock);
0510 
0511     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc");
0512     rtc->regs = devm_ioremap_resource(&pdev->dev, res);
0513     if (IS_ERR(rtc->regs))
0514         return PTR_ERR(rtc->regs);
0515     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rtc-soc");
0516     rtc->regs_soc = devm_ioremap_resource(&pdev->dev, res);
0517     if (IS_ERR(rtc->regs_soc))
0518         return PTR_ERR(rtc->regs_soc);
0519 
0520     rtc->irq = platform_get_irq(pdev, 0);
0521     if (rtc->irq < 0)
0522         return rtc->irq;
0523 
0524     rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
0525     if (IS_ERR(rtc->rtc_dev))
0526         return PTR_ERR(rtc->rtc_dev);
0527 
0528     if (devm_request_irq(&pdev->dev, rtc->irq, armada38x_rtc_alarm_irq,
0529                 0, pdev->name, rtc) < 0) {
0530         dev_warn(&pdev->dev, "Interrupt not available.\n");
0531         rtc->irq = -1;
0532     }
0533     platform_set_drvdata(pdev, rtc);
0534 
0535     if (rtc->irq != -1)
0536         device_init_wakeup(&pdev->dev, 1);
0537     else
0538         clear_bit(RTC_FEATURE_ALARM, rtc->rtc_dev->features);
0539 
0540     /* Update RTC-MBUS bridge timing parameters */
0541     rtc->data->update_mbus_timing(rtc);
0542 
0543     rtc->rtc_dev->ops = &armada38x_rtc_ops;
0544     rtc->rtc_dev->range_max = U32_MAX;
0545 
0546     return devm_rtc_register_device(rtc->rtc_dev);
0547 }
0548 
0549 #ifdef CONFIG_PM_SLEEP
0550 static int armada38x_rtc_suspend(struct device *dev)
0551 {
0552     if (device_may_wakeup(dev)) {
0553         struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0554 
0555         return enable_irq_wake(rtc->irq);
0556     }
0557 
0558     return 0;
0559 }
0560 
0561 static int armada38x_rtc_resume(struct device *dev)
0562 {
0563     if (device_may_wakeup(dev)) {
0564         struct armada38x_rtc *rtc = dev_get_drvdata(dev);
0565 
0566         /* Update RTC-MBUS bridge timing parameters */
0567         rtc->data->update_mbus_timing(rtc);
0568 
0569         return disable_irq_wake(rtc->irq);
0570     }
0571 
0572     return 0;
0573 }
0574 #endif
0575 
0576 static SIMPLE_DEV_PM_OPS(armada38x_rtc_pm_ops,
0577              armada38x_rtc_suspend, armada38x_rtc_resume);
0578 
0579 static struct platform_driver armada38x_rtc_driver = {
0580     .driver     = {
0581         .name   = "armada38x-rtc",
0582         .pm = &armada38x_rtc_pm_ops,
0583         .of_match_table = of_match_ptr(armada38x_rtc_of_match_table),
0584     },
0585 };
0586 
0587 module_platform_driver_probe(armada38x_rtc_driver, armada38x_rtc_probe);
0588 
0589 MODULE_DESCRIPTION("Marvell Armada 38x RTC driver");
0590 MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
0591 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!