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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Real Time Clock driver for AB-RTCMC-32.768kHz-EOZ9 chip.
0004  * Copyright (C) 2019 Orolia
0005  *
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/rtc.h>
0010 #include <linux/i2c.h>
0011 #include <linux/bcd.h>
0012 #include <linux/of.h>
0013 #include <linux/regmap.h>
0014 #include <linux/bitfield.h>
0015 #include <linux/hwmon.h>
0016 #include <linux/hwmon-sysfs.h>
0017 
0018 #define ABEOZ9_REG_CTRL1        0x00
0019 #define ABEOZ9_REG_CTRL1_MASK       GENMASK(7, 0)
0020 #define ABEOZ9_REG_CTRL1_WE     BIT(0)
0021 #define ABEOZ9_REG_CTRL1_TE     BIT(1)
0022 #define ABEOZ9_REG_CTRL1_TAR        BIT(2)
0023 #define ABEOZ9_REG_CTRL1_EERE       BIT(3)
0024 #define ABEOZ9_REG_CTRL1_SRON       BIT(4)
0025 #define ABEOZ9_REG_CTRL1_TD0        BIT(5)
0026 #define ABEOZ9_REG_CTRL1_TD1        BIT(6)
0027 #define ABEOZ9_REG_CTRL1_CLKINT     BIT(7)
0028 
0029 #define ABEOZ9_REG_CTRL_INT     0x01
0030 #define ABEOZ9_REG_CTRL_INT_AIE     BIT(0)
0031 #define ABEOZ9_REG_CTRL_INT_TIE     BIT(1)
0032 #define ABEOZ9_REG_CTRL_INT_V1IE    BIT(2)
0033 #define ABEOZ9_REG_CTRL_INT_V2IE    BIT(3)
0034 #define ABEOZ9_REG_CTRL_INT_SRIE    BIT(4)
0035 
0036 #define ABEOZ9_REG_CTRL_INT_FLAG    0x02
0037 #define ABEOZ9_REG_CTRL_INT_FLAG_AF BIT(0)
0038 #define ABEOZ9_REG_CTRL_INT_FLAG_TF BIT(1)
0039 #define ABEOZ9_REG_CTRL_INT_FLAG_V1IF   BIT(2)
0040 #define ABEOZ9_REG_CTRL_INT_FLAG_V2IF   BIT(3)
0041 #define ABEOZ9_REG_CTRL_INT_FLAG_SRF    BIT(4)
0042 
0043 #define ABEOZ9_REG_CTRL_STATUS      0x03
0044 #define ABEOZ9_REG_CTRL_STATUS_V1F  BIT(2)
0045 #define ABEOZ9_REG_CTRL_STATUS_V2F  BIT(3)
0046 #define ABEOZ9_REG_CTRL_STATUS_SR   BIT(4)
0047 #define ABEOZ9_REG_CTRL_STATUS_PON  BIT(5)
0048 #define ABEOZ9_REG_CTRL_STATUS_EEBUSY   BIT(7)
0049 
0050 #define ABEOZ9_REG_SEC          0x08
0051 #define ABEOZ9_REG_MIN          0x09
0052 #define ABEOZ9_REG_HOURS        0x0A
0053 #define ABEOZ9_HOURS_PM         BIT(6)
0054 #define ABEOZ9_REG_DAYS         0x0B
0055 #define ABEOZ9_REG_WEEKDAYS     0x0C
0056 #define ABEOZ9_REG_MONTHS       0x0D
0057 #define ABEOZ9_REG_YEARS        0x0E
0058 
0059 #define ABEOZ9_SEC_LEN          7
0060 
0061 #define ABEOZ9_REG_ALARM_SEC        0x10
0062 #define ABEOZ9_BIT_ALARM_SEC        GENMASK(6, 0)
0063 #define ABEOZ9_REG_ALARM_MIN        0x11
0064 #define ABEOZ9_BIT_ALARM_MIN        GENMASK(6, 0)
0065 #define ABEOZ9_REG_ALARM_HOURS      0x12
0066 #define ABEOZ9_BIT_ALARM_HOURS_PM   BIT(5)
0067 #define ABEOZ9_BIT_ALARM_HOURS      GENMASK(4, 0)
0068 #define ABEOZ9_REG_ALARM_DAYS       0x13
0069 #define ABEOZ9_BIT_ALARM_DAYS       GENMASK(5, 0)
0070 #define ABEOZ9_REG_ALARM_WEEKDAYS   0x14
0071 #define ABEOZ9_BIT_ALARM_WEEKDAYS   GENMASK(2, 0)
0072 #define ABEOZ9_REG_ALARM_MONTHS     0x15
0073 #define ABEOZ9_BIT_ALARM_MONTHS     GENMASK(4, 0)
0074 #define ABEOZ9_REG_ALARM_YEARS      0x16
0075 
0076 #define ABEOZ9_ALARM_LEN        7
0077 #define ABEOZ9_BIT_ALARM_AE     BIT(7)
0078 
0079 #define ABEOZ9_REG_REG_TEMP     0x20
0080 #define ABEOZ953_TEMP_MAX       120
0081 #define ABEOZ953_TEMP_MIN       -60
0082 
0083 #define ABEOZ9_REG_EEPROM       0x30
0084 #define ABEOZ9_REG_EEPROM_MASK      GENMASK(8, 0)
0085 #define ABEOZ9_REG_EEPROM_THP       BIT(0)
0086 #define ABEOZ9_REG_EEPROM_THE       BIT(1)
0087 #define ABEOZ9_REG_EEPROM_FD0       BIT(2)
0088 #define ABEOZ9_REG_EEPROM_FD1       BIT(3)
0089 #define ABEOZ9_REG_EEPROM_R1K       BIT(4)
0090 #define ABEOZ9_REG_EEPROM_R5K       BIT(5)
0091 #define ABEOZ9_REG_EEPROM_R20K      BIT(6)
0092 #define ABEOZ9_REG_EEPROM_R80K      BIT(7)
0093 
0094 struct abeoz9_rtc_data {
0095     struct rtc_device *rtc;
0096     struct regmap *regmap;
0097     struct device *hwmon_dev;
0098 };
0099 
0100 static int abeoz9_check_validity(struct device *dev)
0101 {
0102     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0103     struct regmap *regmap = data->regmap;
0104     int ret;
0105     int val;
0106 
0107     ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
0108     if (ret < 0) {
0109         dev_err(dev,
0110             "unable to get CTRL_STATUS register (%d)\n", ret);
0111         return ret;
0112     }
0113 
0114     if (val & ABEOZ9_REG_CTRL_STATUS_PON) {
0115         dev_warn(dev, "power-on reset detected, date is invalid\n");
0116         return -EINVAL;
0117     }
0118 
0119     if (val & ABEOZ9_REG_CTRL_STATUS_V1F) {
0120         dev_warn(dev,
0121              "voltage drops below VLOW1 threshold, date is invalid\n");
0122         return -EINVAL;
0123     }
0124 
0125     if ((val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
0126         dev_warn(dev,
0127              "voltage drops below VLOW2 threshold, date is invalid\n");
0128         return -EINVAL;
0129     }
0130 
0131     return 0;
0132 }
0133 
0134 static int abeoz9_reset_validity(struct regmap *regmap)
0135 {
0136     return regmap_update_bits(regmap, ABEOZ9_REG_CTRL_STATUS,
0137                   ABEOZ9_REG_CTRL_STATUS_V1F |
0138                   ABEOZ9_REG_CTRL_STATUS_V2F |
0139                   ABEOZ9_REG_CTRL_STATUS_PON,
0140                   0);
0141 }
0142 
0143 static int abeoz9_rtc_get_time(struct device *dev, struct rtc_time *tm)
0144 {
0145     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0146     u8 regs[ABEOZ9_SEC_LEN];
0147     int ret;
0148 
0149     ret = abeoz9_check_validity(dev);
0150     if (ret)
0151         return ret;
0152 
0153     ret = regmap_bulk_read(data->regmap, ABEOZ9_REG_SEC,
0154                    regs,
0155                    sizeof(regs));
0156     if (ret) {
0157         dev_err(dev, "reading RTC time failed (%d)\n", ret);
0158         return ret;
0159     }
0160 
0161     tm->tm_sec = bcd2bin(regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] & 0x7F);
0162     tm->tm_min = bcd2bin(regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] & 0x7F);
0163 
0164     if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM) {
0165         tm->tm_hour =
0166             bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & 0x1f);
0167         if (regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] & ABEOZ9_HOURS_PM)
0168             tm->tm_hour += 12;
0169     } else {
0170         tm->tm_hour = bcd2bin(regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC]);
0171     }
0172 
0173     tm->tm_mday = bcd2bin(regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC]);
0174     tm->tm_wday = bcd2bin(regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC]);
0175     tm->tm_mon  = bcd2bin(regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC]) - 1;
0176     tm->tm_year = bcd2bin(regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC]) + 100;
0177 
0178     return ret;
0179 }
0180 
0181 static int abeoz9_rtc_set_time(struct device *dev, struct rtc_time *tm)
0182 {
0183     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0184     struct regmap *regmap = data->regmap;
0185     u8 regs[ABEOZ9_SEC_LEN];
0186     int ret;
0187 
0188     regs[ABEOZ9_REG_SEC - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_sec);
0189     regs[ABEOZ9_REG_MIN - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_min);
0190     regs[ABEOZ9_REG_HOURS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_hour);
0191     regs[ABEOZ9_REG_DAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mday);
0192     regs[ABEOZ9_REG_WEEKDAYS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_wday);
0193     regs[ABEOZ9_REG_MONTHS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_mon + 1);
0194     regs[ABEOZ9_REG_YEARS - ABEOZ9_REG_SEC] = bin2bcd(tm->tm_year - 100);
0195 
0196     ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_SEC,
0197                 regs,
0198                 sizeof(regs));
0199 
0200     if (ret) {
0201         dev_err(dev, "set RTC time failed (%d)\n", ret);
0202         return ret;
0203     }
0204 
0205     return abeoz9_reset_validity(regmap);
0206 }
0207 
0208 static int abeoz9_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0209 {
0210     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0211     struct regmap *regmap = data->regmap;
0212     u8 regs[ABEOZ9_ALARM_LEN];
0213     u8 val[2];
0214     int ret;
0215 
0216     ret = abeoz9_check_validity(dev);
0217     if (ret)
0218         return ret;
0219 
0220     ret = regmap_bulk_read(regmap, ABEOZ9_REG_CTRL_INT, val, sizeof(val));
0221     if (ret)
0222         return ret;
0223 
0224     alarm->enabled = val[0] & ABEOZ9_REG_CTRL_INT_AIE;
0225     alarm->pending = val[1] & ABEOZ9_REG_CTRL_INT_FLAG_AF;
0226 
0227     ret = regmap_bulk_read(regmap, ABEOZ9_REG_ALARM_SEC, regs, sizeof(regs));
0228     if (ret)
0229         return ret;
0230 
0231     alarm->time.tm_sec = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_SEC, regs[0]));
0232     alarm->time.tm_min = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_MIN, regs[1]));
0233     alarm->time.tm_hour = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_HOURS, regs[2]));
0234     if (FIELD_GET(ABEOZ9_BIT_ALARM_HOURS_PM, regs[2]))
0235         alarm->time.tm_hour += 12;
0236 
0237     alarm->time.tm_mday = bcd2bin(FIELD_GET(ABEOZ9_BIT_ALARM_DAYS, regs[3]));
0238 
0239     return 0;
0240 }
0241 
0242 static int abeoz9_rtc_alarm_irq_enable(struct device *dev, u32 enable)
0243 {
0244     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0245 
0246     return regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT,
0247                   ABEOZ9_REG_CTRL_INT_AIE,
0248                   FIELD_PREP(ABEOZ9_REG_CTRL_INT_AIE, enable));
0249 }
0250 
0251 static int abeoz9_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0252 {
0253     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0254     u8 regs[ABEOZ9_ALARM_LEN] = {0};
0255     int ret;
0256 
0257     ret = regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
0258                  ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
0259     if (ret)
0260         return ret;
0261 
0262     regs[0] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_SEC,
0263                            bin2bcd(alarm->time.tm_sec));
0264     regs[1] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_MIN,
0265                            bin2bcd(alarm->time.tm_min));
0266     regs[2] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_HOURS,
0267                            bin2bcd(alarm->time.tm_hour));
0268     regs[3] = ABEOZ9_BIT_ALARM_AE | FIELD_PREP(ABEOZ9_BIT_ALARM_DAYS,
0269                            bin2bcd(alarm->time.tm_mday));
0270 
0271     ret = regmap_bulk_write(data->regmap, ABEOZ9_REG_ALARM_SEC, regs,
0272                 sizeof(regs));
0273     if (ret)
0274         return ret;
0275 
0276     return abeoz9_rtc_alarm_irq_enable(dev, alarm->enabled);
0277 }
0278 
0279 static irqreturn_t abeoz9_rtc_irq(int irq, void *dev)
0280 {
0281     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0282     unsigned int val;
0283     int ret;
0284 
0285     ret = regmap_read(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG, &val);
0286     if (ret)
0287         return IRQ_NONE;
0288 
0289     if (!FIELD_GET(ABEOZ9_REG_CTRL_INT_FLAG_AF, val))
0290         return IRQ_NONE;
0291 
0292     regmap_update_bits(data->regmap, ABEOZ9_REG_CTRL_INT_FLAG,
0293                ABEOZ9_REG_CTRL_INT_FLAG_AF, 0);
0294 
0295     rtc_update_irq(data->rtc, 1, RTC_IRQF | RTC_AF);
0296 
0297     return IRQ_HANDLED;
0298 }
0299 
0300 static int abeoz9_trickle_parse_dt(struct device_node *node)
0301 {
0302     u32 ohms = 0;
0303 
0304     if (of_property_read_u32(node, "trickle-resistor-ohms", &ohms))
0305         return 0;
0306 
0307     switch (ohms) {
0308     case 1000:
0309         return ABEOZ9_REG_EEPROM_R1K;
0310     case 5000:
0311         return ABEOZ9_REG_EEPROM_R5K;
0312     case 20000:
0313         return ABEOZ9_REG_EEPROM_R20K;
0314     case 80000:
0315         return ABEOZ9_REG_EEPROM_R80K;
0316     default:
0317         return 0;
0318     }
0319 }
0320 
0321 static int abeoz9_rtc_setup(struct device *dev, struct device_node *node)
0322 {
0323     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0324     struct regmap *regmap = data->regmap;
0325     int ret;
0326 
0327     /* Enable Self Recovery, Clock for Watch and EEPROM refresh functions */
0328     ret = regmap_update_bits(regmap, ABEOZ9_REG_CTRL1,
0329                  ABEOZ9_REG_CTRL1_MASK,
0330                  ABEOZ9_REG_CTRL1_WE |
0331                  ABEOZ9_REG_CTRL1_EERE |
0332                  ABEOZ9_REG_CTRL1_SRON);
0333     if (ret < 0) {
0334         dev_err(dev, "unable to set CTRL_1 register (%d)\n", ret);
0335         return ret;
0336     }
0337 
0338     ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT, 0);
0339     if (ret < 0) {
0340         dev_err(dev,
0341             "unable to set control CTRL_INT register (%d)\n",
0342             ret);
0343         return ret;
0344     }
0345 
0346     ret = regmap_write(regmap, ABEOZ9_REG_CTRL_INT_FLAG, 0);
0347     if (ret < 0) {
0348         dev_err(dev,
0349             "unable to set control CTRL_INT_FLAG register (%d)\n",
0350             ret);
0351         return ret;
0352     }
0353 
0354     ret = abeoz9_trickle_parse_dt(node);
0355 
0356     /* Enable built-in termometer */
0357     ret |= ABEOZ9_REG_EEPROM_THE;
0358 
0359     ret = regmap_update_bits(regmap, ABEOZ9_REG_EEPROM,
0360                  ABEOZ9_REG_EEPROM_MASK,
0361                  ret);
0362     if (ret < 0) {
0363         dev_err(dev, "unable to set EEPROM register (%d)\n", ret);
0364         return ret;
0365     }
0366 
0367     return ret;
0368 }
0369 
0370 static const struct rtc_class_ops rtc_ops = {
0371     .read_time = abeoz9_rtc_get_time,
0372     .set_time = abeoz9_rtc_set_time,
0373     .read_alarm = abeoz9_rtc_read_alarm,
0374     .set_alarm = abeoz9_rtc_set_alarm,
0375     .alarm_irq_enable = abeoz9_rtc_alarm_irq_enable,
0376 };
0377 
0378 static const struct regmap_config abeoz9_rtc_regmap_config = {
0379     .reg_bits = 8,
0380     .val_bits = 8,
0381     .max_register = 0x3f,
0382 };
0383 
0384 #if IS_REACHABLE(CONFIG_HWMON)
0385 
0386 static int abeoz9z3_temp_read(struct device *dev,
0387                   enum hwmon_sensor_types type,
0388                   u32 attr, int channel, long *temp)
0389 {
0390     struct abeoz9_rtc_data *data = dev_get_drvdata(dev);
0391     struct regmap *regmap = data->regmap;
0392     int ret;
0393     unsigned int val;
0394 
0395     ret = regmap_read(regmap, ABEOZ9_REG_CTRL_STATUS, &val);
0396     if (ret < 0)
0397         return ret;
0398 
0399     if ((val & ABEOZ9_REG_CTRL_STATUS_V1F) ||
0400         (val & ABEOZ9_REG_CTRL_STATUS_V2F)) {
0401         dev_err(dev,
0402             "thermometer might be disabled due to low voltage\n");
0403         return -EINVAL;
0404     }
0405 
0406     switch (attr) {
0407     case hwmon_temp_input:
0408         ret = regmap_read(regmap, ABEOZ9_REG_REG_TEMP, &val);
0409         if (ret < 0)
0410             return ret;
0411         *temp = 1000 * (val + ABEOZ953_TEMP_MIN);
0412         return 0;
0413     case hwmon_temp_max:
0414         *temp = 1000 * ABEOZ953_TEMP_MAX;
0415         return 0;
0416     case hwmon_temp_min:
0417         *temp = 1000 * ABEOZ953_TEMP_MIN;
0418         return 0;
0419     default:
0420         return -EOPNOTSUPP;
0421     }
0422 }
0423 
0424 static umode_t abeoz9_is_visible(const void *data,
0425                  enum hwmon_sensor_types type,
0426                  u32 attr, int channel)
0427 {
0428     switch (attr) {
0429     case hwmon_temp_input:
0430     case hwmon_temp_max:
0431     case hwmon_temp_min:
0432         return 0444;
0433     default:
0434         return 0;
0435     }
0436 }
0437 
0438 static const u32 abeoz9_chip_config[] = {
0439     HWMON_C_REGISTER_TZ,
0440     0
0441 };
0442 
0443 static const struct hwmon_channel_info abeoz9_chip = {
0444     .type = hwmon_chip,
0445     .config = abeoz9_chip_config,
0446 };
0447 
0448 static const u32 abeoz9_temp_config[] = {
0449     HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MIN,
0450     0
0451 };
0452 
0453 static const struct hwmon_channel_info abeoz9_temp = {
0454     .type = hwmon_temp,
0455     .config = abeoz9_temp_config,
0456 };
0457 
0458 static const struct hwmon_channel_info *abeoz9_info[] = {
0459     &abeoz9_chip,
0460     &abeoz9_temp,
0461     NULL
0462 };
0463 
0464 static const struct hwmon_ops abeoz9_hwmon_ops = {
0465     .is_visible = abeoz9_is_visible,
0466     .read = abeoz9z3_temp_read,
0467 };
0468 
0469 static const struct hwmon_chip_info abeoz9_chip_info = {
0470     .ops = &abeoz9_hwmon_ops,
0471     .info = abeoz9_info,
0472 };
0473 
0474 static void abeoz9_hwmon_register(struct device *dev,
0475                   struct abeoz9_rtc_data *data)
0476 {
0477     data->hwmon_dev =
0478         devm_hwmon_device_register_with_info(dev,
0479                              "abeoz9",
0480                              data,
0481                              &abeoz9_chip_info,
0482                              NULL);
0483     if (IS_ERR(data->hwmon_dev)) {
0484         dev_warn(dev, "unable to register hwmon device %ld\n",
0485              PTR_ERR(data->hwmon_dev));
0486     }
0487 }
0488 
0489 #else
0490 
0491 static void abeoz9_hwmon_register(struct device *dev,
0492                   struct abeoz9_rtc_data *data)
0493 {
0494 }
0495 
0496 #endif
0497 
0498 static int abeoz9_probe(struct i2c_client *client)
0499 {
0500     struct abeoz9_rtc_data *data = NULL;
0501     struct device *dev = &client->dev;
0502     struct regmap *regmap;
0503     int ret;
0504 
0505     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
0506                      I2C_FUNC_SMBUS_BYTE_DATA |
0507                      I2C_FUNC_SMBUS_I2C_BLOCK))
0508         return -ENODEV;
0509 
0510     regmap = devm_regmap_init_i2c(client, &abeoz9_rtc_regmap_config);
0511     if (IS_ERR(regmap)) {
0512         ret = PTR_ERR(regmap);
0513         dev_err(dev, "regmap allocation failed: %d\n", ret);
0514         return ret;
0515     }
0516 
0517     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0518     if (!data)
0519         return -ENOMEM;
0520 
0521     data->regmap = regmap;
0522     dev_set_drvdata(dev, data);
0523 
0524     ret = abeoz9_rtc_setup(dev, client->dev.of_node);
0525     if (ret)
0526         return ret;
0527 
0528     data->rtc = devm_rtc_allocate_device(dev);
0529     ret = PTR_ERR_OR_ZERO(data->rtc);
0530     if (ret)
0531         return ret;
0532 
0533     data->rtc->ops = &rtc_ops;
0534     data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0535     data->rtc->range_max = RTC_TIMESTAMP_END_2099;
0536     clear_bit(RTC_FEATURE_ALARM, data->rtc->features);
0537 
0538     if (client->irq > 0) {
0539         ret = devm_request_threaded_irq(dev, client->irq, NULL,
0540                         abeoz9_rtc_irq,
0541                         IRQF_TRIGGER_LOW | IRQF_ONESHOT,
0542                         dev_name(dev), dev);
0543         if (ret) {
0544             dev_err(dev, "failed to request alarm irq\n");
0545             return ret;
0546         }
0547     } else {
0548         clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, data->rtc->features);
0549     }
0550 
0551     if (client->irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
0552         ret = device_init_wakeup(dev, true);
0553         set_bit(RTC_FEATURE_ALARM, data->rtc->features);
0554     }
0555 
0556     ret = devm_rtc_register_device(data->rtc);
0557     if (ret)
0558         return ret;
0559 
0560     abeoz9_hwmon_register(dev, data);
0561     return 0;
0562 }
0563 
0564 #ifdef CONFIG_OF
0565 static const struct of_device_id abeoz9_dt_match[] = {
0566     { .compatible = "abracon,abeoz9" },
0567     { },
0568 };
0569 MODULE_DEVICE_TABLE(of, abeoz9_dt_match);
0570 #endif
0571 
0572 static const struct i2c_device_id abeoz9_id[] = {
0573     { "abeoz9", 0 },
0574     { }
0575 };
0576 
0577 static struct i2c_driver abeoz9_driver = {
0578     .driver = {
0579         .name = "rtc-ab-eoz9",
0580         .of_match_table = of_match_ptr(abeoz9_dt_match),
0581     },
0582     .probe_new = abeoz9_probe,
0583     .id_table = abeoz9_id,
0584 };
0585 
0586 module_i2c_driver(abeoz9_driver);
0587 
0588 MODULE_AUTHOR("Artem Panfilov <panfilov.artyom@gmail.com>");
0589 MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-EOZ9 RTC driver");
0590 MODULE_LICENSE("GPL");
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