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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * rtc-ab-b5ze-s3 - Driver for Abracon AB-RTCMC-32.768Khz-B5ZE-S3
0004  *                  I2C RTC / Alarm chip
0005  *
0006  * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
0007  *
0008  * Detailed datasheet of the chip is available here:
0009  *
0010  *  https://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-B5ZE-S3-Application-Manual.pdf
0011  *
0012  * This work is based on ISL12057 driver (drivers/rtc/rtc-isl12057.c).
0013  *
0014  */
0015 
0016 #include <linux/module.h>
0017 #include <linux/rtc.h>
0018 #include <linux/i2c.h>
0019 #include <linux/bcd.h>
0020 #include <linux/of.h>
0021 #include <linux/regmap.h>
0022 #include <linux/interrupt.h>
0023 
0024 #define DRV_NAME "rtc-ab-b5ze-s3"
0025 
0026 /* Control section */
0027 #define ABB5ZES3_REG_CTRL1     0x00    /* Control 1 register */
0028 #define ABB5ZES3_REG_CTRL1_CIE     BIT(0)  /* Pulse interrupt enable */
0029 #define ABB5ZES3_REG_CTRL1_AIE     BIT(1)  /* Alarm interrupt enable */
0030 #define ABB5ZES3_REG_CTRL1_SIE     BIT(2)  /* Second interrupt enable */
0031 #define ABB5ZES3_REG_CTRL1_PM      BIT(3)  /* 24h/12h mode */
0032 #define ABB5ZES3_REG_CTRL1_SR      BIT(4)  /* Software reset */
0033 #define ABB5ZES3_REG_CTRL1_STOP    BIT(5)  /* RTC circuit enable */
0034 #define ABB5ZES3_REG_CTRL1_CAP     BIT(7)
0035 
0036 #define ABB5ZES3_REG_CTRL2     0x01    /* Control 2 register */
0037 #define ABB5ZES3_REG_CTRL2_CTBIE   BIT(0)  /* Countdown timer B int. enable */
0038 #define ABB5ZES3_REG_CTRL2_CTAIE   BIT(1)  /* Countdown timer A int. enable */
0039 #define ABB5ZES3_REG_CTRL2_WTAIE   BIT(2)  /* Watchdog timer A int. enable */
0040 #define ABB5ZES3_REG_CTRL2_AF      BIT(3)  /* Alarm interrupt status */
0041 #define ABB5ZES3_REG_CTRL2_SF      BIT(4)  /* Second interrupt status */
0042 #define ABB5ZES3_REG_CTRL2_CTBF    BIT(5)  /* Countdown timer B int. status */
0043 #define ABB5ZES3_REG_CTRL2_CTAF    BIT(6)  /* Countdown timer A int. status */
0044 #define ABB5ZES3_REG_CTRL2_WTAF    BIT(7)  /* Watchdog timer A int. status */
0045 
0046 #define ABB5ZES3_REG_CTRL3     0x02    /* Control 3 register */
0047 #define ABB5ZES3_REG_CTRL3_PM2     BIT(7)  /* Power Management bit 2 */
0048 #define ABB5ZES3_REG_CTRL3_PM1     BIT(6)  /* Power Management bit 1 */
0049 #define ABB5ZES3_REG_CTRL3_PM0     BIT(5)  /* Power Management bit 0 */
0050 #define ABB5ZES3_REG_CTRL3_BSF     BIT(3)  /* Battery switchover int. status */
0051 #define ABB5ZES3_REG_CTRL3_BLF     BIT(2)  /* Battery low int. status */
0052 #define ABB5ZES3_REG_CTRL3_BSIE    BIT(1)  /* Battery switchover int. enable */
0053 #define ABB5ZES3_REG_CTRL3_BLIE    BIT(0)  /* Battery low int. enable */
0054 
0055 #define ABB5ZES3_CTRL_SEC_LEN      3
0056 
0057 /* RTC section */
0058 #define ABB5ZES3_REG_RTC_SC    0x03    /* RTC Seconds register */
0059 #define ABB5ZES3_REG_RTC_SC_OSC    BIT(7)  /* Clock integrity status */
0060 #define ABB5ZES3_REG_RTC_MN    0x04    /* RTC Minutes register */
0061 #define ABB5ZES3_REG_RTC_HR    0x05    /* RTC Hours register */
0062 #define ABB5ZES3_REG_RTC_HR_PM     BIT(5)  /* RTC Hours PM bit */
0063 #define ABB5ZES3_REG_RTC_DT    0x06    /* RTC Date register */
0064 #define ABB5ZES3_REG_RTC_DW    0x07    /* RTC Day of the week register */
0065 #define ABB5ZES3_REG_RTC_MO    0x08    /* RTC Month register */
0066 #define ABB5ZES3_REG_RTC_YR    0x09    /* RTC Year register */
0067 
0068 #define ABB5ZES3_RTC_SEC_LEN       7
0069 
0070 /* Alarm section (enable bits are all active low) */
0071 #define ABB5ZES3_REG_ALRM_MN       0x0A    /* Alarm - minute register */
0072 #define ABB5ZES3_REG_ALRM_MN_AE    BIT(7)  /* Minute enable */
0073 #define ABB5ZES3_REG_ALRM_HR       0x0B    /* Alarm - hours register */
0074 #define ABB5ZES3_REG_ALRM_HR_AE    BIT(7)  /* Hour enable */
0075 #define ABB5ZES3_REG_ALRM_DT       0x0C    /* Alarm - date register */
0076 #define ABB5ZES3_REG_ALRM_DT_AE    BIT(7)  /* Date (day of the month) enable */
0077 #define ABB5ZES3_REG_ALRM_DW       0x0D    /* Alarm - day of the week reg. */
0078 #define ABB5ZES3_REG_ALRM_DW_AE    BIT(7)  /* Day of the week enable */
0079 
0080 #define ABB5ZES3_ALRM_SEC_LEN      4
0081 
0082 /* Frequency offset section */
0083 #define ABB5ZES3_REG_FREQ_OF       0x0E    /* Frequency offset register */
0084 #define ABB5ZES3_REG_FREQ_OF_MODE  0x0E    /* Offset mode: 2 hours / minute */
0085 
0086 /* CLOCKOUT section */
0087 #define ABB5ZES3_REG_TIM_CLK       0x0F    /* Timer & Clockout register */
0088 #define ABB5ZES3_REG_TIM_CLK_TAM   BIT(7)  /* Permanent/pulsed timer A/int. 2 */
0089 #define ABB5ZES3_REG_TIM_CLK_TBM   BIT(6)  /* Permanent/pulsed timer B */
0090 #define ABB5ZES3_REG_TIM_CLK_COF2  BIT(5)  /* Clkout Freq bit 2 */
0091 #define ABB5ZES3_REG_TIM_CLK_COF1  BIT(4)  /* Clkout Freq bit 1 */
0092 #define ABB5ZES3_REG_TIM_CLK_COF0  BIT(3)  /* Clkout Freq bit 0 */
0093 #define ABB5ZES3_REG_TIM_CLK_TAC1  BIT(2)  /* Timer A: - 01 : countdown */
0094 #define ABB5ZES3_REG_TIM_CLK_TAC0  BIT(1)  /*          - 10 : timer */
0095 #define ABB5ZES3_REG_TIM_CLK_TBC   BIT(0)  /* Timer B enable */
0096 
0097 /* Timer A Section */
0098 #define ABB5ZES3_REG_TIMA_CLK      0x10    /* Timer A clock register */
0099 #define ABB5ZES3_REG_TIMA_CLK_TAQ2 BIT(2)  /* Freq bit 2 */
0100 #define ABB5ZES3_REG_TIMA_CLK_TAQ1 BIT(1)  /* Freq bit 1 */
0101 #define ABB5ZES3_REG_TIMA_CLK_TAQ0 BIT(0)  /* Freq bit 0 */
0102 #define ABB5ZES3_REG_TIMA      0x11    /* Timer A register */
0103 
0104 #define ABB5ZES3_TIMA_SEC_LEN      2
0105 
0106 /* Timer B Section */
0107 #define ABB5ZES3_REG_TIMB_CLK      0x12    /* Timer B clock register */
0108 #define ABB5ZES3_REG_TIMB_CLK_TBW2 BIT(6)
0109 #define ABB5ZES3_REG_TIMB_CLK_TBW1 BIT(5)
0110 #define ABB5ZES3_REG_TIMB_CLK_TBW0 BIT(4)
0111 #define ABB5ZES3_REG_TIMB_CLK_TAQ2 BIT(2)
0112 #define ABB5ZES3_REG_TIMB_CLK_TAQ1 BIT(1)
0113 #define ABB5ZES3_REG_TIMB_CLK_TAQ0 BIT(0)
0114 #define ABB5ZES3_REG_TIMB      0x13    /* Timer B register */
0115 #define ABB5ZES3_TIMB_SEC_LEN      2
0116 
0117 #define ABB5ZES3_MEM_MAP_LEN       0x14
0118 
0119 struct abb5zes3_rtc_data {
0120     struct rtc_device *rtc;
0121     struct regmap *regmap;
0122 
0123     int irq;
0124 
0125     bool battery_low;
0126     bool timer_alarm; /* current alarm is via timer A */
0127 };
0128 
0129 /*
0130  * Try and match register bits w/ fixed null values to see whether we
0131  * are dealing with an ABB5ZES3.
0132  */
0133 static int abb5zes3_i2c_validate_chip(struct regmap *regmap)
0134 {
0135     u8 regs[ABB5ZES3_MEM_MAP_LEN];
0136     static const u8 mask[ABB5ZES3_MEM_MAP_LEN] = { 0x00, 0x00, 0x10, 0x00,
0137                                0x80, 0xc0, 0xc0, 0xf8,
0138                                0xe0, 0x00, 0x00, 0x40,
0139                                0x40, 0x78, 0x00, 0x00,
0140                                0xf8, 0x00, 0x88, 0x00 };
0141     int ret, i;
0142 
0143     ret = regmap_bulk_read(regmap, 0, regs, ABB5ZES3_MEM_MAP_LEN);
0144     if (ret)
0145         return ret;
0146 
0147     for (i = 0; i < ABB5ZES3_MEM_MAP_LEN; ++i) {
0148         if (regs[i] & mask[i]) /* check if bits are cleared */
0149             return -ENODEV;
0150     }
0151 
0152     return 0;
0153 }
0154 
0155 /* Clear alarm status bit. */
0156 static int _abb5zes3_rtc_clear_alarm(struct device *dev)
0157 {
0158     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0159     int ret;
0160 
0161     ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
0162                  ABB5ZES3_REG_CTRL2_AF, 0);
0163     if (ret)
0164         dev_err(dev, "%s: clearing alarm failed (%d)\n", __func__, ret);
0165 
0166     return ret;
0167 }
0168 
0169 /* Enable or disable alarm (i.e. alarm interrupt generation) */
0170 static int _abb5zes3_rtc_update_alarm(struct device *dev, bool enable)
0171 {
0172     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0173     int ret;
0174 
0175     ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL1,
0176                  ABB5ZES3_REG_CTRL1_AIE,
0177                  enable ? ABB5ZES3_REG_CTRL1_AIE : 0);
0178     if (ret)
0179         dev_err(dev, "%s: writing alarm INT failed (%d)\n",
0180             __func__, ret);
0181 
0182     return ret;
0183 }
0184 
0185 /* Enable or disable timer (watchdog timer A interrupt generation) */
0186 static int _abb5zes3_rtc_update_timer(struct device *dev, bool enable)
0187 {
0188     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0189     int ret;
0190 
0191     ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_CTRL2,
0192                  ABB5ZES3_REG_CTRL2_WTAIE,
0193                  enable ? ABB5ZES3_REG_CTRL2_WTAIE : 0);
0194     if (ret)
0195         dev_err(dev, "%s: writing timer INT failed (%d)\n",
0196             __func__, ret);
0197 
0198     return ret;
0199 }
0200 
0201 /*
0202  * Note: we only read, so regmap inner lock protection is sufficient, i.e.
0203  * we do not need driver's main lock protection.
0204  */
0205 static int _abb5zes3_rtc_read_time(struct device *dev, struct rtc_time *tm)
0206 {
0207     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0208     u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
0209     int ret = 0;
0210 
0211     /*
0212      * As we need to read CTRL1 register anyway to access 24/12h
0213      * mode bit, we do a single bulk read of both control and RTC
0214      * sections (they are consecutive). This also ease indexing
0215      * of register values after bulk read.
0216      */
0217     ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_CTRL1, regs,
0218                    sizeof(regs));
0219     if (ret) {
0220         dev_err(dev, "%s: reading RTC time failed (%d)\n",
0221             __func__, ret);
0222         return ret;
0223     }
0224 
0225     /* If clock integrity is not guaranteed, do not return a time value */
0226     if (regs[ABB5ZES3_REG_RTC_SC] & ABB5ZES3_REG_RTC_SC_OSC)
0227         return -ENODATA;
0228 
0229     tm->tm_sec = bcd2bin(regs[ABB5ZES3_REG_RTC_SC] & 0x7F);
0230     tm->tm_min = bcd2bin(regs[ABB5ZES3_REG_RTC_MN]);
0231 
0232     if (regs[ABB5ZES3_REG_CTRL1] & ABB5ZES3_REG_CTRL1_PM) { /* 12hr mode */
0233         tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR] & 0x1f);
0234         if (regs[ABB5ZES3_REG_RTC_HR] & ABB5ZES3_REG_RTC_HR_PM) /* PM */
0235             tm->tm_hour += 12;
0236     } else {                        /* 24hr mode */
0237         tm->tm_hour = bcd2bin(regs[ABB5ZES3_REG_RTC_HR]);
0238     }
0239 
0240     tm->tm_mday = bcd2bin(regs[ABB5ZES3_REG_RTC_DT]);
0241     tm->tm_wday = bcd2bin(regs[ABB5ZES3_REG_RTC_DW]);
0242     tm->tm_mon  = bcd2bin(regs[ABB5ZES3_REG_RTC_MO]) - 1; /* starts at 1 */
0243     tm->tm_year = bcd2bin(regs[ABB5ZES3_REG_RTC_YR]) + 100;
0244 
0245     return ret;
0246 }
0247 
0248 static int abb5zes3_rtc_set_time(struct device *dev, struct rtc_time *tm)
0249 {
0250     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0251     u8 regs[ABB5ZES3_REG_RTC_SC + ABB5ZES3_RTC_SEC_LEN];
0252     int ret;
0253 
0254     regs[ABB5ZES3_REG_RTC_SC] = bin2bcd(tm->tm_sec); /* MSB=0 clears OSC */
0255     regs[ABB5ZES3_REG_RTC_MN] = bin2bcd(tm->tm_min);
0256     regs[ABB5ZES3_REG_RTC_HR] = bin2bcd(tm->tm_hour); /* 24-hour format */
0257     regs[ABB5ZES3_REG_RTC_DT] = bin2bcd(tm->tm_mday);
0258     regs[ABB5ZES3_REG_RTC_DW] = bin2bcd(tm->tm_wday);
0259     regs[ABB5ZES3_REG_RTC_MO] = bin2bcd(tm->tm_mon + 1);
0260     regs[ABB5ZES3_REG_RTC_YR] = bin2bcd(tm->tm_year - 100);
0261 
0262     ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_RTC_SC,
0263                 regs + ABB5ZES3_REG_RTC_SC,
0264                 ABB5ZES3_RTC_SEC_LEN);
0265 
0266     return ret;
0267 }
0268 
0269 /*
0270  * Set provided TAQ and Timer A registers (TIMA_CLK and TIMA) based on
0271  * given number of seconds.
0272  */
0273 static inline void sec_to_timer_a(u8 secs, u8 *taq, u8 *timer_a)
0274 {
0275     *taq = ABB5ZES3_REG_TIMA_CLK_TAQ1; /* 1Hz */
0276     *timer_a = secs;
0277 }
0278 
0279 /*
0280  * Return current number of seconds in Timer A. As we only use
0281  * timer A with a 1Hz freq, this is what we expect to have.
0282  */
0283 static inline int sec_from_timer_a(u8 *secs, u8 taq, u8 timer_a)
0284 {
0285     if (taq != ABB5ZES3_REG_TIMA_CLK_TAQ1) /* 1Hz */
0286         return -EINVAL;
0287 
0288     *secs = timer_a;
0289 
0290     return 0;
0291 }
0292 
0293 /*
0294  * Read alarm currently configured via a watchdog timer using timer A. This
0295  * is done by reading current RTC time and adding remaining timer time.
0296  */
0297 static int _abb5zes3_rtc_read_timer(struct device *dev,
0298                     struct rtc_wkalrm *alarm)
0299 {
0300     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0301     struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
0302     u8 regs[ABB5ZES3_TIMA_SEC_LEN + 1];
0303     unsigned long rtc_secs;
0304     unsigned int reg;
0305     u8 timer_secs;
0306     int ret;
0307 
0308     /*
0309      * Instead of doing two separate calls, because they are consecutive,
0310      * we grab both clockout register and Timer A section. The latter is
0311      * used to decide if timer A is enabled (as a watchdog timer).
0312      */
0313     ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_TIM_CLK, regs,
0314                    ABB5ZES3_TIMA_SEC_LEN + 1);
0315     if (ret) {
0316         dev_err(dev, "%s: reading Timer A section failed (%d)\n",
0317             __func__, ret);
0318         return ret;
0319     }
0320 
0321     /* get current time ... */
0322     ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
0323     if (ret)
0324         return ret;
0325 
0326     /* ... convert to seconds ... */
0327     rtc_secs = rtc_tm_to_time64(&rtc_tm);
0328 
0329     /* ... add remaining timer A time ... */
0330     ret = sec_from_timer_a(&timer_secs, regs[1], regs[2]);
0331     if (ret)
0332         return ret;
0333 
0334     /* ... and convert back. */
0335     rtc_time64_to_tm(rtc_secs + timer_secs, alarm_tm);
0336 
0337     ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL2, &reg);
0338     if (ret) {
0339         dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
0340             __func__, ret);
0341         return ret;
0342     }
0343 
0344     alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL2_WTAIE);
0345 
0346     return 0;
0347 }
0348 
0349 /* Read alarm currently configured via a RTC alarm registers. */
0350 static int _abb5zes3_rtc_read_alarm(struct device *dev,
0351                     struct rtc_wkalrm *alarm)
0352 {
0353     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0354     struct rtc_time rtc_tm, *alarm_tm = &alarm->time;
0355     unsigned long rtc_secs, alarm_secs;
0356     u8 regs[ABB5ZES3_ALRM_SEC_LEN];
0357     unsigned int reg;
0358     int ret;
0359 
0360     ret = regmap_bulk_read(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
0361                    ABB5ZES3_ALRM_SEC_LEN);
0362     if (ret) {
0363         dev_err(dev, "%s: reading alarm section failed (%d)\n",
0364             __func__, ret);
0365         return ret;
0366     }
0367 
0368     alarm_tm->tm_sec  = 0;
0369     alarm_tm->tm_min  = bcd2bin(regs[0] & 0x7f);
0370     alarm_tm->tm_hour = bcd2bin(regs[1] & 0x3f);
0371     alarm_tm->tm_mday = bcd2bin(regs[2] & 0x3f);
0372     alarm_tm->tm_wday = -1;
0373 
0374     /*
0375      * The alarm section does not store year/month. We use the ones in rtc
0376      * section as a basis and increment month and then year if needed to get
0377      * alarm after current time.
0378      */
0379     ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
0380     if (ret)
0381         return ret;
0382 
0383     alarm_tm->tm_year = rtc_tm.tm_year;
0384     alarm_tm->tm_mon = rtc_tm.tm_mon;
0385 
0386     rtc_secs = rtc_tm_to_time64(&rtc_tm);
0387     alarm_secs = rtc_tm_to_time64(alarm_tm);
0388 
0389     if (alarm_secs < rtc_secs) {
0390         if (alarm_tm->tm_mon == 11) {
0391             alarm_tm->tm_mon = 0;
0392             alarm_tm->tm_year += 1;
0393         } else {
0394             alarm_tm->tm_mon += 1;
0395         }
0396     }
0397 
0398     ret = regmap_read(data->regmap, ABB5ZES3_REG_CTRL1, &reg);
0399     if (ret) {
0400         dev_err(dev, "%s: reading ctrl reg failed (%d)\n",
0401             __func__, ret);
0402         return ret;
0403     }
0404 
0405     alarm->enabled = !!(reg & ABB5ZES3_REG_CTRL1_AIE);
0406 
0407     return 0;
0408 }
0409 
0410 /*
0411  * As the Alarm mechanism supported by the chip is only accurate to the
0412  * minute, we use the watchdog timer mechanism provided by timer A
0413  * (up to 256 seconds w/ a second accuracy) for low alarm values (below
0414  * 4 minutes). Otherwise, we use the common alarm mechanism provided
0415  * by the chip. In order for that to work, we keep track of currently
0416  * configured timer type via 'timer_alarm' flag in our private data
0417  * structure.
0418  */
0419 static int abb5zes3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0420 {
0421     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0422     int ret;
0423 
0424     if (data->timer_alarm)
0425         ret = _abb5zes3_rtc_read_timer(dev, alarm);
0426     else
0427         ret = _abb5zes3_rtc_read_alarm(dev, alarm);
0428 
0429     return ret;
0430 }
0431 
0432 /*
0433  * Set alarm using chip alarm mechanism. It is only accurate to the
0434  * minute (not the second). The function expects alarm interrupt to
0435  * be disabled.
0436  */
0437 static int _abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0438 {
0439     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0440     struct rtc_time *alarm_tm = &alarm->time;
0441     u8 regs[ABB5ZES3_ALRM_SEC_LEN];
0442     struct rtc_time rtc_tm;
0443     int ret, enable = 1;
0444 
0445     if (!alarm->enabled) {
0446         enable = 0;
0447     } else {
0448         unsigned long rtc_secs, alarm_secs;
0449 
0450         /*
0451          * Chip only support alarms up to one month in the future. Let's
0452          * return an error if we get something after that limit.
0453          * Comparison is done by incrementing rtc_tm month field by one
0454          * and checking alarm value is still below.
0455          */
0456         ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
0457         if (ret)
0458             return ret;
0459 
0460         if (rtc_tm.tm_mon == 11) { /* handle year wrapping */
0461             rtc_tm.tm_mon = 0;
0462             rtc_tm.tm_year += 1;
0463         } else {
0464             rtc_tm.tm_mon += 1;
0465         }
0466 
0467         rtc_secs = rtc_tm_to_time64(&rtc_tm);
0468         alarm_secs = rtc_tm_to_time64(alarm_tm);
0469 
0470         if (alarm_secs > rtc_secs) {
0471             dev_err(dev, "%s: alarm maximum is one month in the future (%d)\n",
0472                 __func__, ret);
0473             return -EINVAL;
0474         }
0475     }
0476 
0477     /*
0478      * Program all alarm registers but DW one. For each register, setting
0479      * MSB to 0 enables associated alarm.
0480      */
0481     regs[0] = bin2bcd(alarm_tm->tm_min) & 0x7f;
0482     regs[1] = bin2bcd(alarm_tm->tm_hour) & 0x3f;
0483     regs[2] = bin2bcd(alarm_tm->tm_mday) & 0x3f;
0484     regs[3] = ABB5ZES3_REG_ALRM_DW_AE; /* do not match day of the week */
0485 
0486     ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_ALRM_MN, regs,
0487                 ABB5ZES3_ALRM_SEC_LEN);
0488     if (ret < 0) {
0489         dev_err(dev, "%s: writing ALARM section failed (%d)\n",
0490             __func__, ret);
0491         return ret;
0492     }
0493 
0494     /* Record currently configured alarm is not a timer */
0495     data->timer_alarm = 0;
0496 
0497     /* Enable or disable alarm interrupt generation */
0498     return _abb5zes3_rtc_update_alarm(dev, enable);
0499 }
0500 
0501 /*
0502  * Set alarm using timer watchdog (via timer A) mechanism. The function expects
0503  * timer A interrupt to be disabled.
0504  */
0505 static int _abb5zes3_rtc_set_timer(struct device *dev, struct rtc_wkalrm *alarm,
0506                    u8 secs)
0507 {
0508     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0509     u8 regs[ABB5ZES3_TIMA_SEC_LEN];
0510     u8 mask = ABB5ZES3_REG_TIM_CLK_TAC0 | ABB5ZES3_REG_TIM_CLK_TAC1;
0511     int ret = 0;
0512 
0513     /* Program given number of seconds to Timer A registers */
0514     sec_to_timer_a(secs, &regs[0], &regs[1]);
0515     ret = regmap_bulk_write(data->regmap, ABB5ZES3_REG_TIMA_CLK, regs,
0516                 ABB5ZES3_TIMA_SEC_LEN);
0517     if (ret < 0) {
0518         dev_err(dev, "%s: writing timer section failed\n", __func__);
0519         return ret;
0520     }
0521 
0522     /* Configure Timer A as a watchdog timer */
0523     ret = regmap_update_bits(data->regmap, ABB5ZES3_REG_TIM_CLK,
0524                  mask, ABB5ZES3_REG_TIM_CLK_TAC1);
0525     if (ret)
0526         dev_err(dev, "%s: failed to update timer\n", __func__);
0527 
0528     /* Record currently configured alarm is a timer */
0529     data->timer_alarm = 1;
0530 
0531     /* Enable or disable timer interrupt generation */
0532     return _abb5zes3_rtc_update_timer(dev, alarm->enabled);
0533 }
0534 
0535 /*
0536  * The chip has an alarm which is only accurate to the minute. In order to
0537  * handle alarms below that limit, we use the watchdog timer function of
0538  * timer A. More precisely, the timer method is used for alarms below 240
0539  * seconds.
0540  */
0541 static int abb5zes3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
0542 {
0543     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0544     struct rtc_time *alarm_tm = &alarm->time;
0545     unsigned long rtc_secs, alarm_secs;
0546     struct rtc_time rtc_tm;
0547     int ret;
0548 
0549     ret = _abb5zes3_rtc_read_time(dev, &rtc_tm);
0550     if (ret)
0551         return ret;
0552 
0553     rtc_secs = rtc_tm_to_time64(&rtc_tm);
0554     alarm_secs = rtc_tm_to_time64(alarm_tm);
0555 
0556     /* Let's first disable both the alarm and the timer interrupts */
0557     ret = _abb5zes3_rtc_update_alarm(dev, false);
0558     if (ret < 0) {
0559         dev_err(dev, "%s: unable to disable alarm (%d)\n", __func__,
0560             ret);
0561         return ret;
0562     }
0563     ret = _abb5zes3_rtc_update_timer(dev, false);
0564     if (ret < 0) {
0565         dev_err(dev, "%s: unable to disable timer (%d)\n", __func__,
0566             ret);
0567         return ret;
0568     }
0569 
0570     data->timer_alarm = 0;
0571 
0572     /*
0573      * Let's now configure the alarm; if we are expected to ring in
0574      * more than 240s, then we setup an alarm. Otherwise, a timer.
0575      */
0576     if ((alarm_secs > rtc_secs) && ((alarm_secs - rtc_secs) <= 240))
0577         ret = _abb5zes3_rtc_set_timer(dev, alarm,
0578                           alarm_secs - rtc_secs);
0579     else
0580         ret = _abb5zes3_rtc_set_alarm(dev, alarm);
0581 
0582     if (ret)
0583         dev_err(dev, "%s: unable to configure alarm (%d)\n", __func__,
0584             ret);
0585 
0586     return ret;
0587 }
0588 
0589 /* Enable or disable battery low irq generation */
0590 static inline int _abb5zes3_rtc_battery_low_irq_enable(struct regmap *regmap,
0591                                bool enable)
0592 {
0593     return regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3,
0594                   ABB5ZES3_REG_CTRL3_BLIE,
0595                   enable ? ABB5ZES3_REG_CTRL3_BLIE : 0);
0596 }
0597 
0598 /*
0599  * Check current RTC status and enable/disable what needs to be. Return 0 if
0600  * everything went ok and a negative value upon error.
0601  */
0602 static int abb5zes3_rtc_check_setup(struct device *dev)
0603 {
0604     struct abb5zes3_rtc_data *data = dev_get_drvdata(dev);
0605     struct regmap *regmap = data->regmap;
0606     unsigned int reg;
0607     int ret;
0608     u8 mask;
0609 
0610     /*
0611      * By default, the devices generates a 32.768KHz signal on IRQ#1 pin. It
0612      * is disabled here to prevent polluting the interrupt line and
0613      * uselessly triggering the IRQ handler we install for alarm and battery
0614      * low events. Note: this is done before clearing int. status below
0615      * in this function.
0616      * We also disable all timers and set timer interrupt to permanent (not
0617      * pulsed).
0618      */
0619     mask = (ABB5ZES3_REG_TIM_CLK_TBC | ABB5ZES3_REG_TIM_CLK_TAC0 |
0620         ABB5ZES3_REG_TIM_CLK_TAC1 | ABB5ZES3_REG_TIM_CLK_COF0 |
0621         ABB5ZES3_REG_TIM_CLK_COF1 | ABB5ZES3_REG_TIM_CLK_COF2 |
0622         ABB5ZES3_REG_TIM_CLK_TBM | ABB5ZES3_REG_TIM_CLK_TAM);
0623     ret = regmap_update_bits(regmap, ABB5ZES3_REG_TIM_CLK, mask,
0624                  ABB5ZES3_REG_TIM_CLK_COF0 |
0625                  ABB5ZES3_REG_TIM_CLK_COF1 |
0626                  ABB5ZES3_REG_TIM_CLK_COF2);
0627     if (ret < 0) {
0628         dev_err(dev, "%s: unable to initialize clkout register (%d)\n",
0629             __func__, ret);
0630         return ret;
0631     }
0632 
0633     /*
0634      * Each component of the alarm (MN, HR, DT, DW) can be enabled/disabled
0635      * individually by clearing/setting MSB of each associated register. So,
0636      * we set all alarm enable bits to disable current alarm setting.
0637      */
0638     mask = (ABB5ZES3_REG_ALRM_MN_AE | ABB5ZES3_REG_ALRM_HR_AE |
0639         ABB5ZES3_REG_ALRM_DT_AE | ABB5ZES3_REG_ALRM_DW_AE);
0640     ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, mask);
0641     if (ret < 0) {
0642         dev_err(dev, "%s: unable to disable alarm setting (%d)\n",
0643             __func__, ret);
0644         return ret;
0645     }
0646 
0647     /* Set Control 1 register (RTC enabled, 24hr mode, all int. disabled) */
0648     mask = (ABB5ZES3_REG_CTRL1_CIE | ABB5ZES3_REG_CTRL1_AIE |
0649         ABB5ZES3_REG_CTRL1_SIE | ABB5ZES3_REG_CTRL1_PM |
0650         ABB5ZES3_REG_CTRL1_CAP | ABB5ZES3_REG_CTRL1_STOP);
0651     ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL1, mask, 0);
0652     if (ret < 0) {
0653         dev_err(dev, "%s: unable to initialize CTRL1 register (%d)\n",
0654             __func__, ret);
0655         return ret;
0656     }
0657 
0658     /*
0659      * Set Control 2 register (timer int. disabled, alarm status cleared).
0660      * WTAF is read-only and cleared automatically by reading the register.
0661      */
0662     mask = (ABB5ZES3_REG_CTRL2_CTBIE | ABB5ZES3_REG_CTRL2_CTAIE |
0663         ABB5ZES3_REG_CTRL2_WTAIE | ABB5ZES3_REG_CTRL2_AF |
0664         ABB5ZES3_REG_CTRL2_SF | ABB5ZES3_REG_CTRL2_CTBF |
0665         ABB5ZES3_REG_CTRL2_CTAF);
0666     ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL2, mask, 0);
0667     if (ret < 0) {
0668         dev_err(dev, "%s: unable to initialize CTRL2 register (%d)\n",
0669             __func__, ret);
0670         return ret;
0671     }
0672 
0673     /*
0674      * Enable battery low detection function and battery switchover function
0675      * (standard mode). Disable associated interrupts. Clear battery
0676      * switchover flag but not battery low flag. The latter is checked
0677      * later below.
0678      */
0679     mask = (ABB5ZES3_REG_CTRL3_PM0  | ABB5ZES3_REG_CTRL3_PM1 |
0680         ABB5ZES3_REG_CTRL3_PM2  | ABB5ZES3_REG_CTRL3_BLIE |
0681         ABB5ZES3_REG_CTRL3_BSIE | ABB5ZES3_REG_CTRL3_BSF);
0682     ret = regmap_update_bits(regmap, ABB5ZES3_REG_CTRL3, mask, 0);
0683     if (ret < 0) {
0684         dev_err(dev, "%s: unable to initialize CTRL3 register (%d)\n",
0685             __func__, ret);
0686         return ret;
0687     }
0688 
0689     /* Check oscillator integrity flag */
0690     ret = regmap_read(regmap, ABB5ZES3_REG_RTC_SC, &reg);
0691     if (ret < 0) {
0692         dev_err(dev, "%s: unable to read osc. integrity flag (%d)\n",
0693             __func__, ret);
0694         return ret;
0695     }
0696 
0697     if (reg & ABB5ZES3_REG_RTC_SC_OSC) {
0698         dev_err(dev, "clock integrity not guaranteed. Osc. has stopped or has been interrupted.\n");
0699         dev_err(dev, "change battery (if not already done) and then set time to reset osc. failure flag.\n");
0700     }
0701 
0702     /*
0703      * Check battery low flag at startup: this allows reporting battery
0704      * is low at startup when IRQ line is not connected. Note: we record
0705      * current status to avoid reenabling this interrupt later in probe
0706      * function if battery is low.
0707      */
0708     ret = regmap_read(regmap, ABB5ZES3_REG_CTRL3, &reg);
0709     if (ret < 0) {
0710         dev_err(dev, "%s: unable to read battery low flag (%d)\n",
0711             __func__, ret);
0712         return ret;
0713     }
0714 
0715     data->battery_low = reg & ABB5ZES3_REG_CTRL3_BLF;
0716     if (data->battery_low) {
0717         dev_err(dev, "RTC battery is low; please, consider changing it!\n");
0718 
0719         ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, false);
0720         if (ret)
0721             dev_err(dev, "%s: disabling battery low interrupt generation failed (%d)\n",
0722                 __func__, ret);
0723     }
0724 
0725     return ret;
0726 }
0727 
0728 static int abb5zes3_rtc_alarm_irq_enable(struct device *dev,
0729                      unsigned int enable)
0730 {
0731     struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
0732     int ret = 0;
0733 
0734     if (rtc_data->irq) {
0735         if (rtc_data->timer_alarm)
0736             ret = _abb5zes3_rtc_update_timer(dev, enable);
0737         else
0738             ret = _abb5zes3_rtc_update_alarm(dev, enable);
0739     }
0740 
0741     return ret;
0742 }
0743 
0744 static irqreturn_t _abb5zes3_rtc_interrupt(int irq, void *data)
0745 {
0746     struct i2c_client *client = data;
0747     struct device *dev = &client->dev;
0748     struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
0749     struct rtc_device *rtc = rtc_data->rtc;
0750     u8 regs[ABB5ZES3_CTRL_SEC_LEN];
0751     int ret, handled = IRQ_NONE;
0752 
0753     ret = regmap_bulk_read(rtc_data->regmap, 0, regs,
0754                    ABB5ZES3_CTRL_SEC_LEN);
0755     if (ret) {
0756         dev_err(dev, "%s: unable to read control section (%d)!\n",
0757             __func__, ret);
0758         return handled;
0759     }
0760 
0761     /*
0762      * Check battery low detection flag and disable battery low interrupt
0763      * generation if flag is set (interrupt can only be cleared when
0764      * battery is replaced).
0765      */
0766     if (regs[ABB5ZES3_REG_CTRL3] & ABB5ZES3_REG_CTRL3_BLF) {
0767         dev_err(dev, "RTC battery is low; please change it!\n");
0768 
0769         _abb5zes3_rtc_battery_low_irq_enable(rtc_data->regmap, false);
0770 
0771         handled = IRQ_HANDLED;
0772     }
0773 
0774     /* Check alarm flag */
0775     if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_AF) {
0776         dev_dbg(dev, "RTC alarm!\n");
0777 
0778         rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
0779 
0780         /* Acknowledge and disable the alarm */
0781         _abb5zes3_rtc_clear_alarm(dev);
0782         _abb5zes3_rtc_update_alarm(dev, 0);
0783 
0784         handled = IRQ_HANDLED;
0785     }
0786 
0787     /* Check watchdog Timer A flag */
0788     if (regs[ABB5ZES3_REG_CTRL2] & ABB5ZES3_REG_CTRL2_WTAF) {
0789         dev_dbg(dev, "RTC timer!\n");
0790 
0791         rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
0792 
0793         /*
0794          * Acknowledge and disable the alarm. Note: WTAF
0795          * flag had been cleared when reading CTRL2
0796          */
0797         _abb5zes3_rtc_update_timer(dev, 0);
0798 
0799         rtc_data->timer_alarm = 0;
0800 
0801         handled = IRQ_HANDLED;
0802     }
0803 
0804     return handled;
0805 }
0806 
0807 static const struct rtc_class_ops rtc_ops = {
0808     .read_time = _abb5zes3_rtc_read_time,
0809     .set_time = abb5zes3_rtc_set_time,
0810     .read_alarm = abb5zes3_rtc_read_alarm,
0811     .set_alarm = abb5zes3_rtc_set_alarm,
0812     .alarm_irq_enable = abb5zes3_rtc_alarm_irq_enable,
0813 };
0814 
0815 static const struct regmap_config abb5zes3_rtc_regmap_config = {
0816     .reg_bits = 8,
0817     .val_bits = 8,
0818 };
0819 
0820 static int abb5zes3_probe(struct i2c_client *client)
0821 {
0822     struct abb5zes3_rtc_data *data = NULL;
0823     struct device *dev = &client->dev;
0824     struct regmap *regmap;
0825     int ret;
0826 
0827     if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
0828                      I2C_FUNC_SMBUS_BYTE_DATA |
0829                      I2C_FUNC_SMBUS_I2C_BLOCK))
0830         return -ENODEV;
0831 
0832     regmap = devm_regmap_init_i2c(client, &abb5zes3_rtc_regmap_config);
0833     if (IS_ERR(regmap)) {
0834         ret = PTR_ERR(regmap);
0835         dev_err(dev, "%s: regmap allocation failed: %d\n",
0836             __func__, ret);
0837         return ret;
0838     }
0839 
0840     ret = abb5zes3_i2c_validate_chip(regmap);
0841     if (ret)
0842         return ret;
0843 
0844     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0845     if (!data)
0846         return -ENOMEM;
0847 
0848     data->regmap = regmap;
0849     dev_set_drvdata(dev, data);
0850 
0851     ret = abb5zes3_rtc_check_setup(dev);
0852     if (ret)
0853         return ret;
0854 
0855     data->rtc = devm_rtc_allocate_device(dev);
0856     ret = PTR_ERR_OR_ZERO(data->rtc);
0857     if (ret) {
0858         dev_err(dev, "%s: unable to allocate RTC device (%d)\n",
0859             __func__, ret);
0860         return ret;
0861     }
0862 
0863     if (client->irq > 0) {
0864         ret = devm_request_threaded_irq(dev, client->irq, NULL,
0865                         _abb5zes3_rtc_interrupt,
0866                         IRQF_SHARED | IRQF_ONESHOT,
0867                         DRV_NAME, client);
0868         if (!ret) {
0869             device_init_wakeup(dev, true);
0870             data->irq = client->irq;
0871             dev_dbg(dev, "%s: irq %d used by RTC\n", __func__,
0872                 client->irq);
0873         } else {
0874             dev_err(dev, "%s: irq %d unavailable (%d)\n",
0875                 __func__, client->irq, ret);
0876             goto err;
0877         }
0878     }
0879 
0880     data->rtc->ops = &rtc_ops;
0881     data->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
0882     data->rtc->range_max = RTC_TIMESTAMP_END_2099;
0883 
0884     /* Enable battery low detection interrupt if battery not already low */
0885     if (!data->battery_low && data->irq) {
0886         ret = _abb5zes3_rtc_battery_low_irq_enable(regmap, true);
0887         if (ret) {
0888             dev_err(dev, "%s: enabling battery low interrupt generation failed (%d)\n",
0889                 __func__, ret);
0890             goto err;
0891         }
0892     }
0893 
0894     ret = devm_rtc_register_device(data->rtc);
0895 
0896 err:
0897     if (ret && data->irq)
0898         device_init_wakeup(dev, false);
0899     return ret;
0900 }
0901 
0902 #ifdef CONFIG_PM_SLEEP
0903 static int abb5zes3_rtc_suspend(struct device *dev)
0904 {
0905     struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
0906 
0907     if (device_may_wakeup(dev))
0908         return enable_irq_wake(rtc_data->irq);
0909 
0910     return 0;
0911 }
0912 
0913 static int abb5zes3_rtc_resume(struct device *dev)
0914 {
0915     struct abb5zes3_rtc_data *rtc_data = dev_get_drvdata(dev);
0916 
0917     if (device_may_wakeup(dev))
0918         return disable_irq_wake(rtc_data->irq);
0919 
0920     return 0;
0921 }
0922 #endif
0923 
0924 static SIMPLE_DEV_PM_OPS(abb5zes3_rtc_pm_ops, abb5zes3_rtc_suspend,
0925              abb5zes3_rtc_resume);
0926 
0927 #ifdef CONFIG_OF
0928 static const struct of_device_id abb5zes3_dt_match[] = {
0929     { .compatible = "abracon,abb5zes3" },
0930     { },
0931 };
0932 MODULE_DEVICE_TABLE(of, abb5zes3_dt_match);
0933 #endif
0934 
0935 static const struct i2c_device_id abb5zes3_id[] = {
0936     { "abb5zes3", 0 },
0937     { }
0938 };
0939 MODULE_DEVICE_TABLE(i2c, abb5zes3_id);
0940 
0941 static struct i2c_driver abb5zes3_driver = {
0942     .driver = {
0943         .name = DRV_NAME,
0944         .pm = &abb5zes3_rtc_pm_ops,
0945         .of_match_table = of_match_ptr(abb5zes3_dt_match),
0946     },
0947     .probe_new = abb5zes3_probe,
0948     .id_table = abb5zes3_id,
0949 };
0950 module_i2c_driver(abb5zes3_driver);
0951 
0952 MODULE_AUTHOR("Arnaud EBALARD <arno@natisbad.org>");
0953 MODULE_DESCRIPTION("Abracon AB-RTCMC-32.768kHz-B5ZE-S3 RTC/Alarm driver");
0954 MODULE_LICENSE("GPL");
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