drivers/rpmsg/qcom_glink_smem.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2016, Linaro Ltd
0004  */
0005
0006 #include <linux/io.h>
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/mfd/syscon.h>
0013 #include <linux/slab.h>
0014 #include <linux/rpmsg.h>
0015 #include <linux/idr.h>
0016 #include <linux/circ_buf.h>
0017 #include <linux/soc/qcom/smem.h>
0018 #include <linux/sizes.h>
0019 #include <linux/delay.h>
0020 #include <linux/regmap.h>
0021 #include <linux/workqueue.h>
0022 #include <linux/list.h>
0023
0024 #include <linux/rpmsg/qcom_glink.h>
0025
0026 #include "qcom_glink_native.h"
0027
0028 #define FIFO_FULL_RESERVE 8
0029 #define FIFO_ALIGNMENT 8
0030 #define TX_BLOCKED_CMD_RESERVE 8 /* size of struct read_notif_request */
0031
0032 #define SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR   478
0033 #define SMEM_GLINK_NATIVE_XPRT_FIFO_0       479
0034 #define SMEM_GLINK_NATIVE_XPRT_FIFO_1       480
0035
0036 struct glink_smem_pipe {
0037     struct qcom_glink_pipe native;
0038
0039     __le32 *tail;
0040     __le32 *head;
0041
0042     void *fifo;
0043
0044     int remote_pid;
0045 };
0046
0047 #define to_smem_pipe(p) container_of(p, struct glink_smem_pipe, native)
0048
0049 static size_t glink_smem_rx_avail(struct qcom_glink_pipe *np)
0050 {
0051     struct glink_smem_pipe *pipe = to_smem_pipe(np);
0052     size_t len;
0053     void *fifo;
0054     u32 head;
0055     u32 tail;
0056
0057     if (!pipe->fifo) {
0058         fifo = qcom_smem_get(pipe->remote_pid,
0059                      SMEM_GLINK_NATIVE_XPRT_FIFO_1, &len);
0060         if (IS_ERR(fifo)) {
0061             pr_err("failed to acquire RX fifo handle: %ld\n",
0062                    PTR_ERR(fifo));
0063             return 0;
0064         }
0065
0066         pipe->fifo = fifo;
0067         pipe->native.length = len;
0068     }
0069
0070     head = le32_to_cpu(*pipe->head);
0071     tail = le32_to_cpu(*pipe->tail);
0072
0073     if (head < tail)
0074         return pipe->native.length - tail + head;
0075     else
0076         return head - tail;
0077 }
0078
0079 static void glink_smem_rx_peak(struct qcom_glink_pipe *np,
0080                    void *data, unsigned int offset, size_t count)
0081 {
0082     struct glink_smem_pipe *pipe = to_smem_pipe(np);
0083     size_t len;
0084     u32 tail;
0085
0086     tail = le32_to_cpu(*pipe->tail);
0087     tail += offset;
0088     if (tail >= pipe->native.length)
0089         tail -= pipe->native.length;
0090
0091     len = min_t(size_t, count, pipe->native.length - tail);
0092     if (len)
0093         memcpy_fromio(data, pipe->fifo + tail, len);
0094
0095     if (len != count)
0096         memcpy_fromio(data + len, pipe->fifo, (count - len));
0097 }
0098
0099 static void glink_smem_rx_advance(struct qcom_glink_pipe *np,
0100                   size_t count)
0101 {
0102     struct glink_smem_pipe *pipe = to_smem_pipe(np);
0103     u32 tail;
0104
0105     tail = le32_to_cpu(*pipe->tail);
0106
0107     tail += count;
0108     if (tail >= pipe->native.length)
0109         tail -= pipe->native.length;
0110
0111     *pipe->tail = cpu_to_le32(tail);
0112 }
0113
0114 static size_t glink_smem_tx_avail(struct qcom_glink_pipe *np)
0115 {
0116     struct glink_smem_pipe *pipe = to_smem_pipe(np);
0117     u32 head;
0118     u32 tail;
0119     u32 avail;
0120
0121     head = le32_to_cpu(*pipe->head);
0122     tail = le32_to_cpu(*pipe->tail);
0123
0124     if (tail <= head)
0125         avail = pipe->native.length - head + tail;
0126     else
0127         avail = tail - head;
0128
0129     if (avail < (FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE))
0130         avail = 0;
0131     else
0132         avail -= FIFO_FULL_RESERVE + TX_BLOCKED_CMD_RESERVE;
0133
0134     return avail;
0135 }
0136
0137 static unsigned int glink_smem_tx_write_one(struct glink_smem_pipe *pipe,
0138                         unsigned int head,
0139                         const void *data, size_t count)
0140 {
0141     size_t len;
0142
0143     len = min_t(size_t, count, pipe->native.length - head);
0144     if (len)
0145         memcpy(pipe->fifo + head, data, len);
0146
0147     if (len != count)
0148         memcpy(pipe->fifo, data + len, count - len);
0149
0150     head += count;
0151     if (head >= pipe->native.length)
0152         head -= pipe->native.length;
0153
0154     return head;
0155 }
0156
0157 static void glink_smem_tx_write(struct qcom_glink_pipe *glink_pipe,
0158                 const void *hdr, size_t hlen,
0159                 const void *data, size_t dlen)
0160 {
0161     struct glink_smem_pipe *pipe = to_smem_pipe(glink_pipe);
0162     unsigned int head;
0163
0164     head = le32_to_cpu(*pipe->head);
0165
0166     head = glink_smem_tx_write_one(pipe, head, hdr, hlen);
0167     head = glink_smem_tx_write_one(pipe, head, data, dlen);
0168
0169     /* Ensure head is always aligned to 8 bytes */
0170     head = ALIGN(head, 8);
0171     if (head >= pipe->native.length)
0172         head -= pipe->native.length;
0173
0174     /* Ensure ordering of fifo and head update */
0175     wmb();
0176
0177     *pipe->head = cpu_to_le32(head);
0178 }
0179
0180 static void qcom_glink_smem_release(struct device *dev)
0181 {
0182     kfree(dev);
0183 }
0184
0185 struct qcom_glink *qcom_glink_smem_register(struct device *parent,
0186                         struct device_node *node)
0187 {
0188     struct glink_smem_pipe *rx_pipe;
0189     struct glink_smem_pipe *tx_pipe;
0190     struct qcom_glink *glink;
0191     struct device *dev;
0192     u32 remote_pid;
0193     __le32 *descs;
0194     size_t size;
0195     int ret;
0196
0197     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0198     if (!dev)
0199         return ERR_PTR(-ENOMEM);
0200
0201     dev->parent = parent;
0202     dev->of_node = node;
0203     dev->release = qcom_glink_smem_release;
0204     dev_set_name(dev, "%s:%pOFn", dev_name(parent->parent), node);
0205     ret = device_register(dev);
0206     if (ret) {
0207         pr_err("failed to register glink edge\n");
0208         put_device(dev);
0209         return ERR_PTR(ret);
0210     }
0211
0212     ret = of_property_read_u32(dev->of_node, "qcom,remote-pid",
0213                    &remote_pid);
0214     if (ret) {
0215         dev_err(dev, "failed to parse qcom,remote-pid\n");
0216         goto err_put_dev;
0217     }
0218
0219     rx_pipe = devm_kzalloc(dev, sizeof(*rx_pipe), GFP_KERNEL);
0220     tx_pipe = devm_kzalloc(dev, sizeof(*tx_pipe), GFP_KERNEL);
0221     if (!rx_pipe || !tx_pipe) {
0222         ret = -ENOMEM;
0223         goto err_put_dev;
0224     }
0225
0226     ret = qcom_smem_alloc(remote_pid,
0227                   SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, 32);
0228     if (ret && ret != -EEXIST) {
0229         dev_err(dev, "failed to allocate glink descriptors\n");
0230         goto err_put_dev;
0231     }
0232
0233     descs = qcom_smem_get(remote_pid,
0234                   SMEM_GLINK_NATIVE_XPRT_DESCRIPTOR, &size);
0235     if (IS_ERR(descs)) {
0236         dev_err(dev, "failed to acquire xprt descriptor\n");
0237         ret = PTR_ERR(descs);
0238         goto err_put_dev;
0239     }
0240
0241     if (size != 32) {
0242         dev_err(dev, "glink descriptor of invalid size\n");
0243         ret = -EINVAL;
0244         goto err_put_dev;
0245     }
0246
0247     tx_pipe->tail = &descs[0];
0248     tx_pipe->head = &descs[1];
0249     rx_pipe->tail = &descs[2];
0250     rx_pipe->head = &descs[3];
0251
0252     ret = qcom_smem_alloc(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
0253                   SZ_16K);
0254     if (ret && ret != -EEXIST) {
0255         dev_err(dev, "failed to allocate TX fifo\n");
0256         goto err_put_dev;
0257     }
0258
0259     tx_pipe->fifo = qcom_smem_get(remote_pid, SMEM_GLINK_NATIVE_XPRT_FIFO_0,
0260                       &tx_pipe->native.length);
0261     if (IS_ERR(tx_pipe->fifo)) {
0262         dev_err(dev, "failed to acquire TX fifo\n");
0263         ret = PTR_ERR(tx_pipe->fifo);
0264         goto err_put_dev;
0265     }
0266
0267     rx_pipe->native.avail = glink_smem_rx_avail;
0268     rx_pipe->native.peak = glink_smem_rx_peak;
0269     rx_pipe->native.advance = glink_smem_rx_advance;
0270     rx_pipe->remote_pid = remote_pid;
0271
0272     tx_pipe->native.avail = glink_smem_tx_avail;
0273     tx_pipe->native.write = glink_smem_tx_write;
0274     tx_pipe->remote_pid = remote_pid;
0275
0276     *rx_pipe->tail = 0;
0277     *tx_pipe->head = 0;
0278
0279     glink = qcom_glink_native_probe(dev,
0280                     GLINK_FEATURE_INTENT_REUSE,
0281                     &rx_pipe->native, &tx_pipe->native,
0282                     false);
0283     if (IS_ERR(glink)) {
0284         ret = PTR_ERR(glink);
0285         goto err_put_dev;
0286     }
0287
0288     return glink;
0289
0290 err_put_dev:
0291     device_unregister(dev);
0292
0293     return ERR_PTR(ret);
0294 }
0295 EXPORT_SYMBOL_GPL(qcom_glink_smem_register);
0296
0297 void qcom_glink_smem_unregister(struct qcom_glink *glink)
0298 {
0299     qcom_glink_native_remove(glink);
0300     qcom_glink_native_unregister(glink);
0301 }
0302 EXPORT_SYMBOL_GPL(qcom_glink_smem_unregister);
0303
0304 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@linaro.org>");
0305 MODULE_DESCRIPTION("Qualcomm GLINK SMEM driver");
0306 MODULE_LICENSE("GPL v2");