reset/sti/reset-stih407.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2014 STMicroelectronics (R&D) Limited
0004  * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0005  */
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/of_platform.h>
0009 #include <linux/platform_device.h>
0010 #include <dt-bindings/reset/stih407-resets.h>
0011 #include "reset-syscfg.h"
0012
0013 /* STiH407 Peripheral powerdown definitions. */
0014 static const char stih407_core[] = "st,stih407-core-syscfg";
0015 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
0016 static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
0017
0018 #define STIH407_PDN_0(_bit) \
0019     _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
0020 #define STIH407_PDN_1(_bit) \
0021     _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
0022 #define STIH407_PDN_ETH(_bit, _stat) \
0023     _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
0024
0025 /* Powerdown requests control 0 */
0026 #define SYSCFG_5000 0x0
0027 #define SYSSTAT_5500    0x7d0
0028 /* Powerdown requests control 1 (High Speed Links) */
0029 #define SYSCFG_5001 0x4
0030 #define SYSSTAT_5501    0x7d4
0031
0032 /* Ethernet powerdown/status/reset */
0033 #define SYSCFG_4032 0x80
0034 #define SYSSTAT_4520    0x820
0035 #define SYSCFG_4002 0x8
0036
0037 static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
0038     [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
0039     [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
0040     [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
0041     [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
0042     [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
0043     [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
0044     [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
0045     [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
0046     [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
0047     [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
0048 };
0049
0050 /* Reset Generator control 0/1 */
0051 #define SYSCFG_5128 0x200
0052 #define SYSCFG_5131 0x20c
0053 #define SYSCFG_5132 0x210
0054
0055 #define LPM_SYSCFG_1    0x4 /* Softreset IRB & SBC UART */
0056
0057 #define STIH407_SRST_CORE(_reg, _bit) \
0058     _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
0059
0060 #define STIH407_SRST_SBC(_reg, _bit) \
0061     _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
0062
0063 #define STIH407_SRST_LPM(_reg, _bit) \
0064     _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
0065
0066 static const struct syscfg_reset_channel_data stih407_softresets[] = {
0067     [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
0068     [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
0069     [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
0070     [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
0071     [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
0072     [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
0073     [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
0074     [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
0075     [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
0076     [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
0077     [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
0078     [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
0079     [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
0080     [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
0081     [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
0082     [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
0083     [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
0084     [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
0085     [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
0086     [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
0087     [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
0088     [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
0089     [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
0090     [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
0091     [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
0092     [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
0093     [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
0094     [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
0095     [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
0096     [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
0097     [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
0098     [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
0099     [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
0100 };
0101
0102 /* PicoPHY reset/control */
0103 #define SYSCFG_5061 0x0f4
0104
0105 static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
0106     [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
0107     [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
0108     [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
0109 };
0110
0111 static const struct syscfg_reset_controller_data stih407_powerdown_controller = {
0112     .wait_for_ack = true,
0113     .nr_channels = ARRAY_SIZE(stih407_powerdowns),
0114     .channels = stih407_powerdowns,
0115 };
0116
0117 static const struct syscfg_reset_controller_data stih407_softreset_controller = {
0118     .wait_for_ack = false,
0119     .active_low = true,
0120     .nr_channels = ARRAY_SIZE(stih407_softresets),
0121     .channels = stih407_softresets,
0122 };
0123
0124 static const struct syscfg_reset_controller_data stih407_picophyreset_controller = {
0125     .wait_for_ack = false,
0126     .nr_channels = ARRAY_SIZE(stih407_picophyresets),
0127     .channels = stih407_picophyresets,
0128 };
0129
0130 static const struct of_device_id stih407_reset_match[] = {
0131     {
0132         .compatible = "st,stih407-powerdown",
0133         .data = &stih407_powerdown_controller,
0134     },
0135     {
0136         .compatible = "st,stih407-softreset",
0137         .data = &stih407_softreset_controller,
0138     },
0139     {
0140         .compatible = "st,stih407-picophyreset",
0141         .data = &stih407_picophyreset_controller,
0142     },
0143     { /* sentinel */ },
0144 };
0145
0146 static struct platform_driver stih407_reset_driver = {
0147     .probe = syscfg_reset_probe,
0148     .driver = {
0149         .name = "reset-stih407",
0150         .of_match_table = stih407_reset_match,
0151     },
0152 };
0153
0154 static int __init stih407_reset_init(void)
0155 {
0156     return platform_driver_register(&stih407_reset_driver);
0157 }
0158
0159 arch_initcall(stih407_reset_init);