drivers/reset/reset-starfive-jh7100.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Reset driver for the StarFive JH7100 SoC
0004  *
0005  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
0006  */
0007
0008 #include <linux/bitmap.h>
0009 #include <linux/io.h>
0010 #include <linux/io-64-nonatomic-lo-hi.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/mod_devicetable.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/reset-controller.h>
0015 #include <linux/spinlock.h>
0016
0017 #include <dt-bindings/reset/starfive-jh7100.h>
0018
0019 /* register offsets */
0020 #define JH7100_RESET_ASSERT0    0x00
0021 #define JH7100_RESET_ASSERT1    0x04
0022 #define JH7100_RESET_ASSERT2    0x08
0023 #define JH7100_RESET_ASSERT3    0x0c
0024 #define JH7100_RESET_STATUS0    0x10
0025 #define JH7100_RESET_STATUS1    0x14
0026 #define JH7100_RESET_STATUS2    0x18
0027 #define JH7100_RESET_STATUS3    0x1c
0028
0029 /*
0030  * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
0031  * line 32m + n, and writing a 0 deasserts the same line.
0032  * Most reset lines have their status inverted so a 0 bit in the STATUS
0033  * register means the line is asserted and a 1 means it's deasserted. A few
0034  * lines don't though, so store the expected value of the status registers when
0035  * all lines are asserted.
0036  */
0037 static const u64 jh7100_reset_asserted[2] = {
0038     /* STATUS0 */
0039     BIT_ULL_MASK(JH7100_RST_U74) |
0040     BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
0041     BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
0042     /* STATUS1 */
0043     BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
0044     BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
0045     /* STATUS2 */
0046     BIT_ULL_MASK(JH7100_RST_E24) |
0047     /* STATUS3 */
0048     0,
0049 };
0050
0051 struct jh7100_reset {
0052     struct reset_controller_dev rcdev;
0053     /* protect registers against concurrent read-modify-write */
0054     spinlock_t lock;
0055     void __iomem *base;
0056 };
0057
0058 static inline struct jh7100_reset *
0059 jh7100_reset_from(struct reset_controller_dev *rcdev)
0060 {
0061     return container_of(rcdev, struct jh7100_reset, rcdev);
0062 }
0063
0064 static int jh7100_reset_update(struct reset_controller_dev *rcdev,
0065                    unsigned long id, bool assert)
0066 {
0067     struct jh7100_reset *data = jh7100_reset_from(rcdev);
0068     unsigned long offset = BIT_ULL_WORD(id);
0069     u64 mask = BIT_ULL_MASK(id);
0070     void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
0071     void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
0072     u64 done = jh7100_reset_asserted[offset] & mask;
0073     u64 value;
0074     unsigned long flags;
0075     int ret;
0076
0077     if (!assert)
0078         done ^= mask;
0079
0080     spin_lock_irqsave(&data->lock, flags);
0081
0082     value = readq(reg_assert);
0083     if (assert)
0084         value |= mask;
0085     else
0086         value &= ~mask;
0087     writeq(value, reg_assert);
0088
0089     /* if the associated clock is gated, deasserting might otherwise hang forever */
0090     ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
0091
0092     spin_unlock_irqrestore(&data->lock, flags);
0093     return ret;
0094 }
0095
0096 static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
0097                    unsigned long id)
0098 {
0099     return jh7100_reset_update(rcdev, id, true);
0100 }
0101
0102 static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
0103                  unsigned long id)
0104 {
0105     return jh7100_reset_update(rcdev, id, false);
0106 }
0107
0108 static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
0109                   unsigned long id)
0110 {
0111     int ret;
0112
0113     ret = jh7100_reset_assert(rcdev, id);
0114     if (ret)
0115         return ret;
0116
0117     return jh7100_reset_deassert(rcdev, id);
0118 }
0119
0120 static int jh7100_reset_status(struct reset_controller_dev *rcdev,
0121                    unsigned long id)
0122 {
0123     struct jh7100_reset *data = jh7100_reset_from(rcdev);
0124     unsigned long offset = BIT_ULL_WORD(id);
0125     u64 mask = BIT_ULL_MASK(id);
0126     void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
0127     u64 value = readq(reg_status);
0128
0129     return !((value ^ jh7100_reset_asserted[offset]) & mask);
0130 }
0131
0132 static const struct reset_control_ops jh7100_reset_ops = {
0133     .assert     = jh7100_reset_assert,
0134     .deassert   = jh7100_reset_deassert,
0135     .reset      = jh7100_reset_reset,
0136     .status     = jh7100_reset_status,
0137 };
0138
0139 static int __init jh7100_reset_probe(struct platform_device *pdev)
0140 {
0141     struct jh7100_reset *data;
0142
0143     data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
0144     if (!data)
0145         return -ENOMEM;
0146
0147     data->base = devm_platform_ioremap_resource(pdev, 0);
0148     if (IS_ERR(data->base))
0149         return PTR_ERR(data->base);
0150
0151     data->rcdev.ops = &jh7100_reset_ops;
0152     data->rcdev.owner = THIS_MODULE;
0153     data->rcdev.nr_resets = JH7100_RSTN_END;
0154     data->rcdev.dev = &pdev->dev;
0155     data->rcdev.of_node = pdev->dev.of_node;
0156     spin_lock_init(&data->lock);
0157
0158     return devm_reset_controller_register(&pdev->dev, &data->rcdev);
0159 }
0160
0161 static const struct of_device_id jh7100_reset_dt_ids[] = {
0162     { .compatible = "starfive,jh7100-reset" },
0163     { /* sentinel */ }
0164 };
0165
0166 static struct platform_driver jh7100_reset_driver = {
0167     .driver = {
0168         .name = "jh7100-reset",
0169         .of_match_table = jh7100_reset_dt_ids,
0170         .suppress_bind_attrs = true,
0171     },
0172 };
0173 builtin_platform_driver_probe(jh7100_reset_driver, jh7100_reset_probe);