drivers/reset/reset-simple.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Simple Reset Controller Driver
0004  *
0005  * Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
0006  *
0007  * Based on Allwinner SoCs Reset Controller driver
0008  *
0009  * Copyright 2013 Maxime Ripard
0010  *
0011  * Maxime Ripard <maxime.ripard@free-electrons.com>
0012  */
0013
0014 #include <linux/delay.h>
0015 #include <linux/device.h>
0016 #include <linux/err.h>
0017 #include <linux/io.h>
0018 #include <linux/of.h>
0019 #include <linux/of_device.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/reset-controller.h>
0022 #include <linux/reset/reset-simple.h>
0023 #include <linux/spinlock.h>
0024
0025 static inline struct reset_simple_data *
0026 to_reset_simple_data(struct reset_controller_dev *rcdev)
0027 {
0028     return container_of(rcdev, struct reset_simple_data, rcdev);
0029 }
0030
0031 static int reset_simple_update(struct reset_controller_dev *rcdev,
0032                    unsigned long id, bool assert)
0033 {
0034     struct reset_simple_data *data = to_reset_simple_data(rcdev);
0035     int reg_width = sizeof(u32);
0036     int bank = id / (reg_width * BITS_PER_BYTE);
0037     int offset = id % (reg_width * BITS_PER_BYTE);
0038     unsigned long flags;
0039     u32 reg;
0040
0041     spin_lock_irqsave(&data->lock, flags);
0042
0043     reg = readl(data->membase + (bank * reg_width));
0044     if (assert ^ data->active_low)
0045         reg |= BIT(offset);
0046     else
0047         reg &= ~BIT(offset);
0048     writel(reg, data->membase + (bank * reg_width));
0049
0050     spin_unlock_irqrestore(&data->lock, flags);
0051
0052     return 0;
0053 }
0054
0055 static int reset_simple_assert(struct reset_controller_dev *rcdev,
0056                    unsigned long id)
0057 {
0058     return reset_simple_update(rcdev, id, true);
0059 }
0060
0061 static int reset_simple_deassert(struct reset_controller_dev *rcdev,
0062                  unsigned long id)
0063 {
0064     return reset_simple_update(rcdev, id, false);
0065 }
0066
0067 static int reset_simple_reset(struct reset_controller_dev *rcdev,
0068                   unsigned long id)
0069 {
0070     struct reset_simple_data *data = to_reset_simple_data(rcdev);
0071     int ret;
0072
0073     if (!data->reset_us)
0074         return -ENOTSUPP;
0075
0076     ret = reset_simple_assert(rcdev, id);
0077     if (ret)
0078         return ret;
0079
0080     usleep_range(data->reset_us, data->reset_us * 2);
0081
0082     return reset_simple_deassert(rcdev, id);
0083 }
0084
0085 static int reset_simple_status(struct reset_controller_dev *rcdev,
0086                    unsigned long id)
0087 {
0088     struct reset_simple_data *data = to_reset_simple_data(rcdev);
0089     int reg_width = sizeof(u32);
0090     int bank = id / (reg_width * BITS_PER_BYTE);
0091     int offset = id % (reg_width * BITS_PER_BYTE);
0092     u32 reg;
0093
0094     reg = readl(data->membase + (bank * reg_width));
0095
0096     return !(reg & BIT(offset)) ^ !data->status_active_low;
0097 }
0098
0099 const struct reset_control_ops reset_simple_ops = {
0100     .assert     = reset_simple_assert,
0101     .deassert   = reset_simple_deassert,
0102     .reset      = reset_simple_reset,
0103     .status     = reset_simple_status,
0104 };
0105 EXPORT_SYMBOL_GPL(reset_simple_ops);
0106
0107 /**
0108  * struct reset_simple_devdata - simple reset controller properties
0109  * @reg_offset: offset between base address and first reset register.
0110  * @nr_resets: number of resets. If not set, default to resource size in bits.
0111  * @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
0112  *              are set to assert the reset.
0113  * @status_active_low: if true, bits read back as cleared while the reset is
0114  *                     asserted. Otherwise, bits read back as set while the
0115  *                     reset is asserted.
0116  */
0117 struct reset_simple_devdata {
0118     u32 reg_offset;
0119     u32 nr_resets;
0120     bool active_low;
0121     bool status_active_low;
0122 };
0123
0124 #define SOCFPGA_NR_BANKS    8
0125
0126 static const struct reset_simple_devdata reset_simple_socfpga = {
0127     .reg_offset = 0x20,
0128     .nr_resets = SOCFPGA_NR_BANKS * 32,
0129     .status_active_low = true,
0130 };
0131
0132 static const struct reset_simple_devdata reset_simple_active_low = {
0133     .active_low = true,
0134     .status_active_low = true,
0135 };
0136
0137 static const struct of_device_id reset_simple_dt_ids[] = {
0138     { .compatible = "altr,stratix10-rst-mgr",
0139         .data = &reset_simple_socfpga },
0140     { .compatible = "st,stm32-rcc", },
0141     { .compatible = "allwinner,sun6i-a31-clock-reset",
0142         .data = &reset_simple_active_low },
0143     { .compatible = "zte,zx296718-reset",
0144         .data = &reset_simple_active_low },
0145     { .compatible = "aspeed,ast2400-lpc-reset" },
0146     { .compatible = "aspeed,ast2500-lpc-reset" },
0147     { .compatible = "aspeed,ast2600-lpc-reset" },
0148     { .compatible = "bitmain,bm1880-reset",
0149         .data = &reset_simple_active_low },
0150     { .compatible = "brcm,bcm4908-misc-pcie-reset",
0151         .data = &reset_simple_active_low },
0152     { .compatible = "snps,dw-high-reset" },
0153     { .compatible = "snps,dw-low-reset",
0154         .data = &reset_simple_active_low },
0155     { /* sentinel */ },
0156 };
0157
0158 static int reset_simple_probe(struct platform_device *pdev)
0159 {
0160     struct device *dev = &pdev->dev;
0161     const struct reset_simple_devdata *devdata;
0162     struct reset_simple_data *data;
0163     void __iomem *membase;
0164     struct resource *res;
0165     u32 reg_offset = 0;
0166
0167     devdata = of_device_get_match_data(dev);
0168
0169     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0170     if (!data)
0171         return -ENOMEM;
0172
0173     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0174     membase = devm_ioremap_resource(dev, res);
0175     if (IS_ERR(membase))
0176         return PTR_ERR(membase);
0177
0178     spin_lock_init(&data->lock);
0179     data->membase = membase;
0180     data->rcdev.owner = THIS_MODULE;
0181     data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
0182     data->rcdev.ops = &reset_simple_ops;
0183     data->rcdev.of_node = dev->of_node;
0184
0185     if (devdata) {
0186         reg_offset = devdata->reg_offset;
0187         if (devdata->nr_resets)
0188             data->rcdev.nr_resets = devdata->nr_resets;
0189         data->active_low = devdata->active_low;
0190         data->status_active_low = devdata->status_active_low;
0191     }
0192
0193     data->membase += reg_offset;
0194
0195     return devm_reset_controller_register(dev, &data->rcdev);
0196 }
0197
0198 static struct platform_driver reset_simple_driver = {
0199     .probe  = reset_simple_probe,
0200     .driver = {
0201         .name       = "simple-reset",
0202         .of_match_table = reset_simple_dt_ids,
0203     },
0204 };
0205 builtin_platform_driver(reset_simple_driver);