drivers/reset/reset-rzg2l-usbphy-ctrl.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/G2L USBPHY control driver
0004  *
0005  * Copyright (C) 2021 Renesas Electronics Corporation
0006  */
0007
0008 #include <linux/io.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/reset.h>
0014 #include <linux/reset-controller.h>
0015
0016 #define RESET           0x000
0017
0018 #define RESET_SEL_PLLRESET  BIT(12)
0019 #define RESET_PLLRESET      BIT(8)
0020
0021 #define RESET_SEL_P2RESET   BIT(5)
0022 #define RESET_SEL_P1RESET   BIT(4)
0023 #define RESET_PHYRST_2      BIT(1)
0024 #define RESET_PHYRST_1      BIT(0)
0025
0026 #define PHY_RESET_PORT2     (RESET_SEL_P2RESET | RESET_PHYRST_2)
0027 #define PHY_RESET_PORT1     (RESET_SEL_P1RESET | RESET_PHYRST_1)
0028
0029 #define NUM_PORTS       2
0030
0031 struct rzg2l_usbphy_ctrl_priv {
0032     struct reset_controller_dev rcdev;
0033     struct reset_control *rstc;
0034     void __iomem *base;
0035
0036     spinlock_t lock;
0037 };
0038
0039 #define rcdev_to_priv(x)    container_of(x, struct rzg2l_usbphy_ctrl_priv, rcdev)
0040
0041 static int rzg2l_usbphy_ctrl_assert(struct reset_controller_dev *rcdev,
0042                     unsigned long id)
0043 {
0044     struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
0045     u32 port_mask = PHY_RESET_PORT1 | PHY_RESET_PORT2;
0046     void __iomem *base = priv->base;
0047     unsigned long flags;
0048     u32 val;
0049
0050     spin_lock_irqsave(&priv->lock, flags);
0051     val = readl(base + RESET);
0052     val |= id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
0053     if (port_mask == (val & port_mask))
0054         val |= RESET_PLLRESET;
0055     writel(val, base + RESET);
0056     spin_unlock_irqrestore(&priv->lock, flags);
0057
0058     return 0;
0059 }
0060
0061 static int rzg2l_usbphy_ctrl_deassert(struct reset_controller_dev *rcdev,
0062                       unsigned long id)
0063 {
0064     struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
0065     void __iomem *base = priv->base;
0066     unsigned long flags;
0067     u32 val;
0068
0069     spin_lock_irqsave(&priv->lock, flags);
0070     val = readl(base + RESET);
0071
0072     val |= RESET_SEL_PLLRESET;
0073     val &= ~(RESET_PLLRESET | (id ? PHY_RESET_PORT2 : PHY_RESET_PORT1));
0074     writel(val, base + RESET);
0075     spin_unlock_irqrestore(&priv->lock, flags);
0076
0077     return 0;
0078 }
0079
0080 static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
0081                     unsigned long id)
0082 {
0083     struct rzg2l_usbphy_ctrl_priv *priv = rcdev_to_priv(rcdev);
0084     u32 port_mask;
0085
0086     port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
0087
0088     return !!(readl(priv->base + RESET) & port_mask);
0089 }
0090
0091 static const struct of_device_id rzg2l_usbphy_ctrl_match_table[] = {
0092     { .compatible = "renesas,rzg2l-usbphy-ctrl" },
0093     { /* Sentinel */ }
0094 };
0095 MODULE_DEVICE_TABLE(of, rzg2l_usbphy_ctrl_match_table);
0096
0097 static const struct reset_control_ops rzg2l_usbphy_ctrl_reset_ops = {
0098     .assert = rzg2l_usbphy_ctrl_assert,
0099     .deassert = rzg2l_usbphy_ctrl_deassert,
0100     .status = rzg2l_usbphy_ctrl_status,
0101 };
0102
0103 static int rzg2l_usbphy_ctrl_probe(struct platform_device *pdev)
0104 {
0105     struct device *dev = &pdev->dev;
0106     struct rzg2l_usbphy_ctrl_priv *priv;
0107     unsigned long flags;
0108     int error;
0109     u32 val;
0110
0111     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0112     if (!priv)
0113         return -ENOMEM;
0114
0115     priv->base = devm_platform_ioremap_resource(pdev, 0);
0116     if (IS_ERR(priv->base))
0117         return PTR_ERR(priv->base);
0118
0119     priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0120     if (IS_ERR(priv->rstc))
0121         return dev_err_probe(dev, PTR_ERR(priv->rstc),
0122                      "failed to get reset\n");
0123
0124     error = reset_control_deassert(priv->rstc);
0125     if (error)
0126         return error;
0127
0128     priv->rcdev.ops = &rzg2l_usbphy_ctrl_reset_ops;
0129     priv->rcdev.of_reset_n_cells = 1;
0130     priv->rcdev.nr_resets = NUM_PORTS;
0131     priv->rcdev.of_node = dev->of_node;
0132     priv->rcdev.dev = dev;
0133
0134     error = devm_reset_controller_register(dev, &priv->rcdev);
0135     if (error)
0136         return error;
0137
0138     spin_lock_init(&priv->lock);
0139     dev_set_drvdata(dev, priv);
0140
0141     pm_runtime_enable(&pdev->dev);
0142     error = pm_runtime_resume_and_get(&pdev->dev);
0143     if (error < 0) {
0144         pm_runtime_disable(&pdev->dev);
0145         reset_control_assert(priv->rstc);
0146         return dev_err_probe(&pdev->dev, error, "pm_runtime_resume_and_get failed");
0147     }
0148
0149     /* put pll and phy into reset state */
0150     spin_lock_irqsave(&priv->lock, flags);
0151     val = readl(priv->base + RESET);
0152     val |= RESET_SEL_PLLRESET | RESET_PLLRESET | PHY_RESET_PORT2 | PHY_RESET_PORT1;
0153     writel(val, priv->base + RESET);
0154     spin_unlock_irqrestore(&priv->lock, flags);
0155
0156     return 0;
0157 }
0158
0159 static int rzg2l_usbphy_ctrl_remove(struct platform_device *pdev)
0160 {
0161     struct rzg2l_usbphy_ctrl_priv *priv = dev_get_drvdata(&pdev->dev);
0162
0163     pm_runtime_put(&pdev->dev);
0164     pm_runtime_disable(&pdev->dev);
0165     reset_control_assert(priv->rstc);
0166
0167     return 0;
0168 }
0169
0170 static struct platform_driver rzg2l_usbphy_ctrl_driver = {
0171     .driver = {
0172         .name       = "rzg2l_usbphy_ctrl",
0173         .of_match_table = rzg2l_usbphy_ctrl_match_table,
0174     },
0175     .probe  = rzg2l_usbphy_ctrl_probe,
0176     .remove = rzg2l_usbphy_ctrl_remove,
0177 };
0178 module_platform_driver(rzg2l_usbphy_ctrl_driver);
0179
0180 MODULE_LICENSE("GPL v2");
0181 MODULE_DESCRIPTION("Renesas RZ/G2L USBPHY Control");
0182 MODULE_AUTHOR("biju.das.jz@bp.renesas.com>");