drivers/reset/reset-qcom-pdc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include <linux/module.h>
0007 #include <linux/of_device.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/regmap.h>
0010 #include <linux/reset-controller.h>
0011
0012 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
0013
0014 #define RPMH_SDM845_PDC_SYNC_RESET  0x100
0015 #define RPMH_SC7280_PDC_SYNC_RESET  0x1000
0016
0017 struct qcom_pdc_reset_map {
0018     u8 bit;
0019 };
0020
0021 struct qcom_pdc_reset_desc {
0022     const struct qcom_pdc_reset_map *resets;
0023     size_t num_resets;
0024     unsigned int offset;
0025 };
0026
0027 struct qcom_pdc_reset_data {
0028     struct reset_controller_dev rcdev;
0029     struct regmap *regmap;
0030     const struct qcom_pdc_reset_desc *desc;
0031 };
0032
0033 static const struct regmap_config pdc_regmap_config = {
0034     .name       = "pdc-reset",
0035     .reg_bits   = 32,
0036     .reg_stride = 4,
0037     .val_bits   = 32,
0038     .max_register   = 0x20000,
0039     .fast_io    = true,
0040 };
0041
0042 static const struct qcom_pdc_reset_map sdm845_pdc_resets[] = {
0043     [PDC_APPS_SYNC_RESET] = {0},
0044     [PDC_SP_SYNC_RESET] = {1},
0045     [PDC_AUDIO_SYNC_RESET] = {2},
0046     [PDC_SENSORS_SYNC_RESET] = {3},
0047     [PDC_AOP_SYNC_RESET] = {4},
0048     [PDC_DEBUG_SYNC_RESET] = {5},
0049     [PDC_GPU_SYNC_RESET] = {6},
0050     [PDC_DISPLAY_SYNC_RESET] = {7},
0051     [PDC_COMPUTE_SYNC_RESET] = {8},
0052     [PDC_MODEM_SYNC_RESET] = {9},
0053 };
0054
0055 static const struct qcom_pdc_reset_desc sdm845_pdc_reset_desc = {
0056     .resets = sdm845_pdc_resets,
0057     .num_resets = ARRAY_SIZE(sdm845_pdc_resets),
0058     .offset = RPMH_SDM845_PDC_SYNC_RESET,
0059 };
0060
0061 static const struct qcom_pdc_reset_map sc7280_pdc_resets[] = {
0062     [PDC_APPS_SYNC_RESET] = {0},
0063     [PDC_SP_SYNC_RESET] = {1},
0064     [PDC_AUDIO_SYNC_RESET] = {2},
0065     [PDC_SENSORS_SYNC_RESET] = {3},
0066     [PDC_AOP_SYNC_RESET] = {4},
0067     [PDC_DEBUG_SYNC_RESET] = {5},
0068     [PDC_GPU_SYNC_RESET] = {6},
0069     [PDC_DISPLAY_SYNC_RESET] = {7},
0070     [PDC_COMPUTE_SYNC_RESET] = {8},
0071     [PDC_MODEM_SYNC_RESET] = {9},
0072     [PDC_WLAN_RF_SYNC_RESET] = {10},
0073     [PDC_WPSS_SYNC_RESET] = {11},
0074 };
0075
0076 static const struct qcom_pdc_reset_desc sc7280_pdc_reset_desc = {
0077     .resets = sc7280_pdc_resets,
0078     .num_resets = ARRAY_SIZE(sc7280_pdc_resets),
0079     .offset = RPMH_SC7280_PDC_SYNC_RESET,
0080 };
0081
0082 static inline struct qcom_pdc_reset_data *to_qcom_pdc_reset_data(
0083                 struct reset_controller_dev *rcdev)
0084 {
0085     return container_of(rcdev, struct qcom_pdc_reset_data, rcdev);
0086 }
0087
0088 static int qcom_pdc_control_assert(struct reset_controller_dev *rcdev,
0089                     unsigned long idx)
0090 {
0091     struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
0092     u32 mask = BIT(data->desc->resets[idx].bit);
0093
0094     return regmap_update_bits(data->regmap, data->desc->offset, mask, mask);
0095 }
0096
0097 static int qcom_pdc_control_deassert(struct reset_controller_dev *rcdev,
0098                     unsigned long idx)
0099 {
0100     struct qcom_pdc_reset_data *data = to_qcom_pdc_reset_data(rcdev);
0101     u32 mask = BIT(data->desc->resets[idx].bit);
0102
0103     return regmap_update_bits(data->regmap, data->desc->offset, mask, 0);
0104 }
0105
0106 static const struct reset_control_ops qcom_pdc_reset_ops = {
0107     .assert = qcom_pdc_control_assert,
0108     .deassert = qcom_pdc_control_deassert,
0109 };
0110
0111 static int qcom_pdc_reset_probe(struct platform_device *pdev)
0112 {
0113     const struct qcom_pdc_reset_desc *desc;
0114     struct qcom_pdc_reset_data *data;
0115     struct device *dev = &pdev->dev;
0116     void __iomem *base;
0117     struct resource *res;
0118
0119     desc = device_get_match_data(&pdev->dev);
0120     if (!desc)
0121         return -EINVAL;
0122
0123     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0124     if (!data)
0125         return -ENOMEM;
0126
0127     data->desc = desc;
0128     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0129     base = devm_ioremap_resource(dev, res);
0130     if (IS_ERR(base))
0131         return PTR_ERR(base);
0132
0133     data->regmap = devm_regmap_init_mmio(dev, base, &pdc_regmap_config);
0134     if (IS_ERR(data->regmap)) {
0135         dev_err(dev, "Unable to initialize regmap\n");
0136         return PTR_ERR(data->regmap);
0137     }
0138
0139     data->rcdev.owner = THIS_MODULE;
0140     data->rcdev.ops = &qcom_pdc_reset_ops;
0141     data->rcdev.nr_resets = desc->num_resets;
0142     data->rcdev.of_node = dev->of_node;
0143
0144     return devm_reset_controller_register(dev, &data->rcdev);
0145 }
0146
0147 static const struct of_device_id qcom_pdc_reset_of_match[] = {
0148     { .compatible = "qcom,sc7280-pdc-global", .data = &sc7280_pdc_reset_desc },
0149     { .compatible = "qcom,sdm845-pdc-global", .data = &sdm845_pdc_reset_desc },
0150     {}
0151 };
0152 MODULE_DEVICE_TABLE(of, qcom_pdc_reset_of_match);
0153
0154 static struct platform_driver qcom_pdc_reset_driver = {
0155     .probe = qcom_pdc_reset_probe,
0156     .driver = {
0157         .name = "qcom_pdc_reset",
0158         .of_match_table = qcom_pdc_reset_of_match,
0159     },
0160 };
0161 module_platform_driver(qcom_pdc_reset_driver);
0162
0163 MODULE_DESCRIPTION("Qualcomm PDC Reset Driver");
0164 MODULE_LICENSE("GPL v2");