drivers/reset/reset-npcm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2019 Nuvoton Technology corporation.
0003
0004 #include <linux/delay.h>
0005 #include <linux/err.h>
0006 #include <linux/io.h>
0007 #include <linux/init.h>
0008 #include <linux/of.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/reboot.h>
0012 #include <linux/reset-controller.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/regmap.h>
0016 #include <linux/of_address.h>
0017
0018 /* NPCM7xx GCR registers */
0019 #define NPCM_MDLR_OFFSET    0x7C
0020 #define NPCM7XX_MDLR_USBD0  BIT(9)
0021 #define NPCM7XX_MDLR_USBD1  BIT(8)
0022 #define NPCM7XX_MDLR_USBD2_4    BIT(21)
0023 #define NPCM7XX_MDLR_USBD5_9    BIT(22)
0024
0025 /* NPCM8xx MDLR bits */
0026 #define NPCM8XX_MDLR_USBD0_3    BIT(9)
0027 #define NPCM8XX_MDLR_USBD4_7    BIT(22)
0028 #define NPCM8XX_MDLR_USBD8  BIT(24)
0029 #define NPCM8XX_MDLR_USBD9  BIT(21)
0030
0031 #define NPCM_USB1PHYCTL_OFFSET  0x140
0032 #define NPCM_USB2PHYCTL_OFFSET  0x144
0033 #define NPCM_USB3PHYCTL_OFFSET  0x148
0034 #define NPCM_USBXPHYCTL_RS  BIT(28)
0035
0036 /* NPCM7xx Reset registers */
0037 #define NPCM_SWRSTR     0x14
0038 #define NPCM_SWRST      BIT(2)
0039
0040 #define NPCM_IPSRST1        0x20
0041 #define NPCM_IPSRST1_USBD1  BIT(5)
0042 #define NPCM_IPSRST1_USBD2  BIT(8)
0043 #define NPCM_IPSRST1_USBD3  BIT(25)
0044 #define NPCM_IPSRST1_USBD4  BIT(22)
0045 #define NPCM_IPSRST1_USBD5  BIT(23)
0046 #define NPCM_IPSRST1_USBD6  BIT(24)
0047
0048 #define NPCM_IPSRST2        0x24
0049 #define NPCM_IPSRST2_USB_HOST   BIT(26)
0050
0051 #define NPCM_IPSRST3        0x34
0052 #define NPCM_IPSRST3_USBD0  BIT(4)
0053 #define NPCM_IPSRST3_USBD7  BIT(5)
0054 #define NPCM_IPSRST3_USBD8  BIT(6)
0055 #define NPCM_IPSRST3_USBD9  BIT(7)
0056 #define NPCM_IPSRST3_USBPHY1    BIT(24)
0057 #define NPCM_IPSRST3_USBPHY2    BIT(25)
0058
0059 #define NPCM_IPSRST4        0x74
0060 #define NPCM_IPSRST4_USBPHY3    BIT(25)
0061 #define NPCM_IPSRST4_USB_HOST2  BIT(31)
0062
0063 #define NPCM_RC_RESETS_PER_REG  32
0064 #define NPCM_MASK_RESETS    GENMASK(4, 0)
0065
0066 enum {
0067     BMC_NPCM7XX = 0,
0068     BMC_NPCM8XX,
0069 };
0070
0071 static const u32 npxm7xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3};
0072 static const u32 npxm8xx_ipsrst[] = {NPCM_IPSRST1, NPCM_IPSRST2, NPCM_IPSRST3,
0073     NPCM_IPSRST4};
0074
0075 struct npcm_reset_info {
0076     u32 bmc_id;
0077     u32 num_ipsrst;
0078     const u32 *ipsrst;
0079 };
0080
0081 static const struct npcm_reset_info npxm7xx_reset_info[] = {
0082     {.bmc_id = BMC_NPCM7XX, .num_ipsrst = 3, .ipsrst = npxm7xx_ipsrst}};
0083 static const struct npcm_reset_info npxm8xx_reset_info[] = {
0084     {.bmc_id = BMC_NPCM8XX, .num_ipsrst = 4, .ipsrst = npxm8xx_ipsrst}};
0085
0086 struct npcm_rc_data {
0087     struct reset_controller_dev rcdev;
0088     struct notifier_block restart_nb;
0089     const struct npcm_reset_info *info;
0090     struct regmap *gcr_regmap;
0091     u32 sw_reset_number;
0092     void __iomem *base;
0093     spinlock_t lock;
0094 };
0095
0096 #define to_rc_data(p) container_of(p, struct npcm_rc_data, rcdev)
0097
0098 static int npcm_rc_restart(struct notifier_block *nb, unsigned long mode,
0099                void *cmd)
0100 {
0101     struct npcm_rc_data *rc = container_of(nb, struct npcm_rc_data,
0102                            restart_nb);
0103
0104     writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR);
0105     mdelay(1000);
0106
0107     pr_emerg("%s: unable to restart system\n", __func__);
0108
0109     return NOTIFY_DONE;
0110 }
0111
0112 static int npcm_rc_setclear_reset(struct reset_controller_dev *rcdev,
0113                   unsigned long id, bool set)
0114 {
0115     struct npcm_rc_data *rc = to_rc_data(rcdev);
0116     unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
0117     unsigned int ctrl_offset = id >> 8;
0118     unsigned long flags;
0119     u32 stat;
0120
0121     spin_lock_irqsave(&rc->lock, flags);
0122     stat = readl(rc->base + ctrl_offset);
0123     if (set)
0124         writel(stat | rst_bit, rc->base + ctrl_offset);
0125     else
0126         writel(stat & ~rst_bit, rc->base + ctrl_offset);
0127     spin_unlock_irqrestore(&rc->lock, flags);
0128
0129     return 0;
0130 }
0131
0132 static int npcm_rc_assert(struct reset_controller_dev *rcdev, unsigned long id)
0133 {
0134     return npcm_rc_setclear_reset(rcdev, id, true);
0135 }
0136
0137 static int npcm_rc_deassert(struct reset_controller_dev *rcdev,
0138                 unsigned long id)
0139 {
0140     return npcm_rc_setclear_reset(rcdev, id, false);
0141 }
0142
0143 static int npcm_rc_status(struct reset_controller_dev *rcdev,
0144               unsigned long id)
0145 {
0146     struct npcm_rc_data *rc = to_rc_data(rcdev);
0147     unsigned int rst_bit = BIT(id & NPCM_MASK_RESETS);
0148     unsigned int ctrl_offset = id >> 8;
0149
0150     return (readl(rc->base + ctrl_offset) & rst_bit);
0151 }
0152
0153 static int npcm_reset_xlate(struct reset_controller_dev *rcdev,
0154                 const struct of_phandle_args *reset_spec)
0155 {
0156     struct npcm_rc_data *rc = to_rc_data(rcdev);
0157     unsigned int offset, bit;
0158     bool offset_found = false;
0159     int off_num;
0160
0161     offset = reset_spec->args[0];
0162     for (off_num = 0 ; off_num < rc->info->num_ipsrst ; off_num++) {
0163         if (offset == rc->info->ipsrst[off_num]) {
0164             offset_found = true;
0165             break;
0166         }
0167     }
0168
0169     if (!offset_found) {
0170         dev_err(rcdev->dev, "Error reset register (0x%x)\n", offset);
0171         return -EINVAL;
0172     }
0173
0174     bit = reset_spec->args[1];
0175     if (bit >= NPCM_RC_RESETS_PER_REG) {
0176         dev_err(rcdev->dev, "Error reset number (%d)\n", bit);
0177         return -EINVAL;
0178     }
0179
0180     return (offset << 8) | bit;
0181 }
0182
0183 static const struct of_device_id npcm_rc_match[] = {
0184     { .compatible = "nuvoton,npcm750-reset", .data = &npxm7xx_reset_info},
0185     { .compatible = "nuvoton,npcm845-reset", .data = &npxm8xx_reset_info},
0186     { }
0187 };
0188
0189 static void npcm_usb_reset_npcm7xx(struct npcm_rc_data *rc)
0190 {
0191     u32 mdlr, iprst1, iprst2, iprst3;
0192     u32 ipsrst1_bits = 0;
0193     u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
0194     u32 ipsrst3_bits = 0;
0195
0196     /* checking which USB device is enabled */
0197     regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
0198     if (!(mdlr & NPCM7XX_MDLR_USBD0))
0199         ipsrst3_bits |= NPCM_IPSRST3_USBD0;
0200     if (!(mdlr & NPCM7XX_MDLR_USBD1))
0201         ipsrst1_bits |= NPCM_IPSRST1_USBD1;
0202     if (!(mdlr & NPCM7XX_MDLR_USBD2_4))
0203         ipsrst1_bits |= (NPCM_IPSRST1_USBD2 |
0204                  NPCM_IPSRST1_USBD3 |
0205                  NPCM_IPSRST1_USBD4);
0206     if (!(mdlr & NPCM7XX_MDLR_USBD0)) {
0207         ipsrst1_bits |= (NPCM_IPSRST1_USBD5 |
0208                  NPCM_IPSRST1_USBD6);
0209         ipsrst3_bits |= (NPCM_IPSRST3_USBD7 |
0210                  NPCM_IPSRST3_USBD8 |
0211                  NPCM_IPSRST3_USBD9);
0212     }
0213
0214     /* assert reset USB PHY and USB devices */
0215     iprst1 = readl(rc->base + NPCM_IPSRST1);
0216     iprst2 = readl(rc->base + NPCM_IPSRST2);
0217     iprst3 = readl(rc->base + NPCM_IPSRST3);
0218
0219     iprst1 |= ipsrst1_bits;
0220     iprst2 |= ipsrst2_bits;
0221     iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
0222            NPCM_IPSRST3_USBPHY2);
0223
0224     writel(iprst1, rc->base + NPCM_IPSRST1);
0225     writel(iprst2, rc->base + NPCM_IPSRST2);
0226     writel(iprst3, rc->base + NPCM_IPSRST3);
0227
0228     /* clear USB PHY RS bit */
0229     regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
0230                NPCM_USBXPHYCTL_RS, 0);
0231     regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
0232                NPCM_USBXPHYCTL_RS, 0);
0233
0234     /* deassert reset USB PHY */
0235     iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
0236     writel(iprst3, rc->base + NPCM_IPSRST3);
0237
0238     udelay(50);
0239
0240     /* set USB PHY RS bit */
0241     regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
0242                NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
0243     regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
0244                NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
0245
0246     /* deassert reset USB devices*/
0247     iprst1 &= ~ipsrst1_bits;
0248     iprst2 &= ~ipsrst2_bits;
0249     iprst3 &= ~ipsrst3_bits;
0250
0251     writel(iprst1, rc->base + NPCM_IPSRST1);
0252     writel(iprst2, rc->base + NPCM_IPSRST2);
0253     writel(iprst3, rc->base + NPCM_IPSRST3);
0254 }
0255
0256 static void npcm_usb_reset_npcm8xx(struct npcm_rc_data *rc)
0257 {
0258     u32 mdlr, iprst1, iprst2, iprst3, iprst4;
0259     u32 ipsrst1_bits = 0;
0260     u32 ipsrst2_bits = NPCM_IPSRST2_USB_HOST;
0261     u32 ipsrst3_bits = 0;
0262     u32 ipsrst4_bits = NPCM_IPSRST4_USB_HOST2 | NPCM_IPSRST4_USBPHY3;
0263
0264     /* checking which USB device is enabled */
0265     regmap_read(rc->gcr_regmap, NPCM_MDLR_OFFSET, &mdlr);
0266     if (!(mdlr & NPCM8XX_MDLR_USBD0_3)) {
0267         ipsrst3_bits |= NPCM_IPSRST3_USBD0;
0268         ipsrst1_bits |= (NPCM_IPSRST1_USBD1 |
0269                  NPCM_IPSRST1_USBD2 |
0270                  NPCM_IPSRST1_USBD3);
0271     }
0272     if (!(mdlr & NPCM8XX_MDLR_USBD4_7)) {
0273         ipsrst1_bits |= (NPCM_IPSRST1_USBD4 |
0274                  NPCM_IPSRST1_USBD5 |
0275                  NPCM_IPSRST1_USBD6);
0276         ipsrst3_bits |= NPCM_IPSRST3_USBD7;
0277     }
0278
0279     if (!(mdlr & NPCM8XX_MDLR_USBD8))
0280         ipsrst3_bits |= NPCM_IPSRST3_USBD8;
0281     if (!(mdlr & NPCM8XX_MDLR_USBD9))
0282         ipsrst3_bits |= NPCM_IPSRST3_USBD9;
0283
0284     /* assert reset USB PHY and USB devices */
0285     iprst1 = readl(rc->base + NPCM_IPSRST1);
0286     iprst2 = readl(rc->base + NPCM_IPSRST2);
0287     iprst3 = readl(rc->base + NPCM_IPSRST3);
0288     iprst4 = readl(rc->base + NPCM_IPSRST4);
0289
0290     iprst1 |= ipsrst1_bits;
0291     iprst2 |= ipsrst2_bits;
0292     iprst3 |= (ipsrst3_bits | NPCM_IPSRST3_USBPHY1 |
0293            NPCM_IPSRST3_USBPHY2);
0294     iprst4 |= ipsrst4_bits;
0295
0296     writel(iprst1, rc->base + NPCM_IPSRST1);
0297     writel(iprst2, rc->base + NPCM_IPSRST2);
0298     writel(iprst3, rc->base + NPCM_IPSRST3);
0299     writel(iprst4, rc->base + NPCM_IPSRST4);
0300
0301     /* clear USB PHY RS bit */
0302     regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
0303                NPCM_USBXPHYCTL_RS, 0);
0304     regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
0305                NPCM_USBXPHYCTL_RS, 0);
0306     regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
0307                NPCM_USBXPHYCTL_RS, 0);
0308
0309     /* deassert reset USB PHY */
0310     iprst3 &= ~(NPCM_IPSRST3_USBPHY1 | NPCM_IPSRST3_USBPHY2);
0311     writel(iprst3, rc->base + NPCM_IPSRST3);
0312     iprst4 &= ~NPCM_IPSRST4_USBPHY3;
0313     writel(iprst4, rc->base + NPCM_IPSRST4);
0314
0315     /* set USB PHY RS bit */
0316     regmap_update_bits(rc->gcr_regmap, NPCM_USB1PHYCTL_OFFSET,
0317                NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
0318     regmap_update_bits(rc->gcr_regmap, NPCM_USB2PHYCTL_OFFSET,
0319                NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
0320     regmap_update_bits(rc->gcr_regmap, NPCM_USB3PHYCTL_OFFSET,
0321                NPCM_USBXPHYCTL_RS, NPCM_USBXPHYCTL_RS);
0322
0323     /* deassert reset USB devices*/
0324     iprst1 &= ~ipsrst1_bits;
0325     iprst2 &= ~ipsrst2_bits;
0326     iprst3 &= ~ipsrst3_bits;
0327     iprst4 &= ~ipsrst4_bits;
0328
0329     writel(iprst1, rc->base + NPCM_IPSRST1);
0330     writel(iprst2, rc->base + NPCM_IPSRST2);
0331     writel(iprst3, rc->base + NPCM_IPSRST3);
0332     writel(iprst4, rc->base + NPCM_IPSRST4);
0333 }
0334
0335 /*
0336  *  The following procedure should be observed in USB PHY, USB device and
0337  *  USB host initialization at BMC boot
0338  */
0339 static int npcm_usb_reset(struct platform_device *pdev, struct npcm_rc_data *rc)
0340 {
0341     struct device *dev = &pdev->dev;
0342
0343     rc->gcr_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr");
0344     if (IS_ERR(rc->gcr_regmap)) {
0345         dev_warn(&pdev->dev, "Failed to find nuvoton,sysgcr property, please update the device tree\n");
0346         dev_info(&pdev->dev, "Using nuvoton,npcm750-gcr for Poleg backward compatibility\n");
0347         rc->gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
0348         if (IS_ERR(rc->gcr_regmap)) {
0349             dev_err(&pdev->dev, "Failed to find nuvoton,npcm750-gcr");
0350             return PTR_ERR(rc->gcr_regmap);
0351         }
0352     }
0353
0354     rc->info = (const struct npcm_reset_info *)
0355             of_match_device(dev->driver->of_match_table, dev)->data;
0356     switch (rc->info->bmc_id) {
0357     case BMC_NPCM7XX:
0358         npcm_usb_reset_npcm7xx(rc);
0359         break;
0360     case BMC_NPCM8XX:
0361         npcm_usb_reset_npcm8xx(rc);
0362         break;
0363     default:
0364         return -ENODEV;
0365     }
0366
0367     return 0;
0368 }
0369
0370 static const struct reset_control_ops npcm_rc_ops = {
0371     .assert     = npcm_rc_assert,
0372     .deassert   = npcm_rc_deassert,
0373     .status     = npcm_rc_status,
0374 };
0375
0376 static int npcm_rc_probe(struct platform_device *pdev)
0377 {
0378     struct npcm_rc_data *rc;
0379     int ret;
0380
0381     rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
0382     if (!rc)
0383         return -ENOMEM;
0384
0385     rc->base = devm_platform_ioremap_resource(pdev, 0);
0386     if (IS_ERR(rc->base))
0387         return PTR_ERR(rc->base);
0388
0389     spin_lock_init(&rc->lock);
0390
0391     rc->rcdev.owner = THIS_MODULE;
0392     rc->rcdev.ops = &npcm_rc_ops;
0393     rc->rcdev.of_node = pdev->dev.of_node;
0394     rc->rcdev.of_reset_n_cells = 2;
0395     rc->rcdev.of_xlate = npcm_reset_xlate;
0396
0397     platform_set_drvdata(pdev, rc);
0398
0399     ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev);
0400     if (ret) {
0401         dev_err(&pdev->dev, "unable to register device\n");
0402         return ret;
0403     }
0404
0405     if (npcm_usb_reset(pdev, rc))
0406         dev_warn(&pdev->dev, "NPCM USB reset failed, can cause issues with UDC and USB host\n");
0407
0408     if (!of_property_read_u32(pdev->dev.of_node, "nuvoton,sw-reset-number",
0409                   &rc->sw_reset_number)) {
0410         if (rc->sw_reset_number && rc->sw_reset_number < 5) {
0411             rc->restart_nb.priority = 192,
0412             rc->restart_nb.notifier_call = npcm_rc_restart,
0413             ret = register_restart_handler(&rc->restart_nb);
0414             if (ret)
0415                 dev_warn(&pdev->dev, "failed to register restart handler\n");
0416         }
0417     }
0418
0419     return ret;
0420 }
0421
0422 static struct platform_driver npcm_rc_driver = {
0423     .probe  = npcm_rc_probe,
0424     .driver = {
0425         .name           = "npcm-reset",
0426         .of_match_table     = npcm_rc_match,
0427         .suppress_bind_attrs    = true,
0428     },
0429 };
0430 builtin_platform_driver(npcm_rc_driver);