drivers/reset/reset-microchip-sparx5.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Microchip Sparx5 Switch Reset driver
0003  *
0004  * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
0005  *
0006  * The Sparx5 Chip Register Model can be browsed at this location:
0007  * https://github.com/microchip-ung/sparx-5_reginfo
0008  */
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/of_device.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <linux/reset-controller.h>
0015
0016 struct reset_props {
0017     u32 protect_reg;
0018     u32 protect_bit;
0019     u32 reset_reg;
0020     u32 reset_bit;
0021 };
0022
0023 struct mchp_reset_context {
0024     struct regmap *cpu_ctrl;
0025     struct regmap *gcb_ctrl;
0026     struct reset_controller_dev rcdev;
0027     const struct reset_props *props;
0028 };
0029
0030 static struct regmap_config sparx5_reset_regmap_config = {
0031     .reg_bits   = 32,
0032     .val_bits   = 32,
0033     .reg_stride = 4,
0034 };
0035
0036 static int sparx5_switch_reset(struct mchp_reset_context *ctx)
0037 {
0038     u32 val;
0039
0040     /* Make sure the core is PROTECTED from reset */
0041     regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
0042                ctx->props->protect_bit, ctx->props->protect_bit);
0043
0044     /* Start soft reset */
0045     regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg,
0046              ctx->props->reset_bit);
0047
0048     /* Wait for soft reset done */
0049     return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val,
0050                     (val & ctx->props->reset_bit) == 0,
0051                     1, 100);
0052 }
0053
0054 static int sparx5_reset_noop(struct reset_controller_dev *rcdev,
0055                  unsigned long id)
0056 {
0057     return 0;
0058 }
0059
0060 static const struct reset_control_ops sparx5_reset_ops = {
0061     .reset = sparx5_reset_noop,
0062 };
0063
0064 static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
0065                   struct regmap **target)
0066 {
0067     struct device_node *syscon_np;
0068     struct regmap *regmap;
0069     int err;
0070
0071     syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
0072     if (!syscon_np)
0073         return -ENODEV;
0074     regmap = syscon_node_to_regmap(syscon_np);
0075     of_node_put(syscon_np);
0076     if (IS_ERR(regmap)) {
0077         err = PTR_ERR(regmap);
0078         dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
0079         return err;
0080     }
0081     *target = regmap;
0082     return 0;
0083 }
0084
0085 static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
0086                   struct regmap **target)
0087 {
0088     struct resource *res;
0089     struct regmap *map;
0090     void __iomem *mem;
0091
0092     mem = devm_platform_get_and_ioremap_resource(pdev, index, &res);
0093     if (IS_ERR(mem)) {
0094         dev_err(&pdev->dev, "Could not map resource %d\n", index);
0095         return PTR_ERR(mem);
0096     }
0097     sparx5_reset_regmap_config.name = res->name;
0098     map = devm_regmap_init_mmio(&pdev->dev, mem, &sparx5_reset_regmap_config);
0099     if (IS_ERR(map))
0100         return PTR_ERR(map);
0101     *target = map;
0102     return 0;
0103 }
0104
0105 static int mchp_sparx5_reset_probe(struct platform_device *pdev)
0106 {
0107     struct device_node *dn = pdev->dev.of_node;
0108     struct mchp_reset_context *ctx;
0109     int err;
0110
0111     ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
0112     if (!ctx)
0113         return -ENOMEM;
0114
0115     err = mchp_sparx5_map_syscon(pdev, "cpu-syscon", &ctx->cpu_ctrl);
0116     if (err)
0117         return err;
0118     err = mchp_sparx5_map_io(pdev, 0, &ctx->gcb_ctrl);
0119     if (err)
0120         return err;
0121
0122     ctx->rcdev.owner = THIS_MODULE;
0123     ctx->rcdev.nr_resets = 1;
0124     ctx->rcdev.ops = &sparx5_reset_ops;
0125     ctx->rcdev.of_node = dn;
0126     ctx->props = device_get_match_data(&pdev->dev);
0127
0128     /* Issue the reset very early, our actual reset callback is a noop. */
0129     err = sparx5_switch_reset(ctx);
0130     if (err)
0131         return err;
0132
0133     return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
0134 }
0135
0136 static const struct reset_props reset_props_sparx5 = {
0137     .protect_reg    = 0x84,
0138     .protect_bit    = BIT(10),
0139     .reset_reg      = 0x0,
0140     .reset_bit      = BIT(1),
0141 };
0142
0143 static const struct reset_props reset_props_lan966x = {
0144     .protect_reg    = 0x88,
0145     .protect_bit    = BIT(5),
0146     .reset_reg      = 0x0,
0147     .reset_bit      = BIT(1),
0148 };
0149
0150 static const struct of_device_id mchp_sparx5_reset_of_match[] = {
0151     {
0152         .compatible = "microchip,sparx5-switch-reset",
0153         .data = &reset_props_sparx5,
0154     }, {
0155         .compatible = "microchip,lan966x-switch-reset",
0156         .data = &reset_props_lan966x,
0157     },
0158     { }
0159 };
0160
0161 static struct platform_driver mchp_sparx5_reset_driver = {
0162     .probe = mchp_sparx5_reset_probe,
0163     .driver = {
0164         .name = "sparx5-switch-reset",
0165         .of_match_table = mchp_sparx5_reset_of_match,
0166     },
0167 };
0168
0169 static int __init mchp_sparx5_reset_init(void)
0170 {
0171     return platform_driver_register(&mchp_sparx5_reset_driver);
0172 }
0173
0174 /*
0175  * Because this is a global reset, keep this postcore_initcall() to issue the
0176  * reset as early as possible during the kernel startup.
0177  */
0178 postcore_initcall(mchp_sparx5_reset_init);
0179
0180 MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
0181 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
0182 MODULE_LICENSE("Dual MIT/GPL");