drivers/reset/reset-lpc18xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Reset driver for NXP LPC18xx/43xx Reset Generation Unit (RGU).
0004  *
0005  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/init.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/reboot.h>
0016 #include <linux/reset-controller.h>
0017 #include <linux/spinlock.h>
0018
0019 /* LPC18xx RGU registers */
0020 #define LPC18XX_RGU_CTRL0       0x100
0021 #define LPC18XX_RGU_CTRL1       0x104
0022 #define LPC18XX_RGU_ACTIVE_STATUS0  0x150
0023 #define LPC18XX_RGU_ACTIVE_STATUS1  0x154
0024
0025 #define LPC18XX_RGU_RESETS_PER_REG  32
0026
0027 /* Internal reset outputs */
0028 #define LPC18XX_RGU_CORE_RST    0
0029 #define LPC43XX_RGU_M0SUB_RST   12
0030 #define LPC43XX_RGU_M0APP_RST   56
0031
0032 struct lpc18xx_rgu_data {
0033     struct reset_controller_dev rcdev;
0034     struct notifier_block restart_nb;
0035     struct clk *clk_delay;
0036     struct clk *clk_reg;
0037     void __iomem *base;
0038     spinlock_t lock;
0039     u32 delay_us;
0040 };
0041
0042 #define to_rgu_data(p) container_of(p, struct lpc18xx_rgu_data, rcdev)
0043
0044 static int lpc18xx_rgu_restart(struct notifier_block *nb, unsigned long mode,
0045                    void *cmd)
0046 {
0047     struct lpc18xx_rgu_data *rc = container_of(nb, struct lpc18xx_rgu_data,
0048                            restart_nb);
0049
0050     writel(BIT(LPC18XX_RGU_CORE_RST), rc->base + LPC18XX_RGU_CTRL0);
0051     mdelay(2000);
0052
0053     pr_emerg("%s: unable to restart system\n", __func__);
0054
0055     return NOTIFY_DONE;
0056 }
0057
0058 /*
0059  * The LPC18xx RGU has mostly self-deasserting resets except for the
0060  * two reset lines going to the internal Cortex-M0 cores.
0061  *
0062  * To prevent the M0 core resets from accidentally getting deasserted
0063  * status register must be check and bits in control register set to
0064  * preserve the state.
0065  */
0066 static int lpc18xx_rgu_setclear_reset(struct reset_controller_dev *rcdev,
0067                       unsigned long id, bool set)
0068 {
0069     struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
0070     u32 stat_offset = LPC18XX_RGU_ACTIVE_STATUS0;
0071     u32 ctrl_offset = LPC18XX_RGU_CTRL0;
0072     unsigned long flags;
0073     u32 stat, rst_bit;
0074
0075     stat_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
0076     ctrl_offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
0077     rst_bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
0078
0079     spin_lock_irqsave(&rc->lock, flags);
0080     stat = ~readl(rc->base + stat_offset);
0081     if (set)
0082         writel(stat | rst_bit, rc->base + ctrl_offset);
0083     else
0084         writel(stat & ~rst_bit, rc->base + ctrl_offset);
0085     spin_unlock_irqrestore(&rc->lock, flags);
0086
0087     return 0;
0088 }
0089
0090 static int lpc18xx_rgu_assert(struct reset_controller_dev *rcdev,
0091                   unsigned long id)
0092 {
0093     return lpc18xx_rgu_setclear_reset(rcdev, id, true);
0094 }
0095
0096 static int lpc18xx_rgu_deassert(struct reset_controller_dev *rcdev,
0097                 unsigned long id)
0098 {
0099     return lpc18xx_rgu_setclear_reset(rcdev, id, false);
0100 }
0101
0102 /* Only M0 cores require explicit reset deassert */
0103 static int lpc18xx_rgu_reset(struct reset_controller_dev *rcdev,
0104                  unsigned long id)
0105 {
0106     struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
0107
0108     lpc18xx_rgu_assert(rcdev, id);
0109     udelay(rc->delay_us);
0110
0111     switch (id) {
0112     case LPC43XX_RGU_M0SUB_RST:
0113     case LPC43XX_RGU_M0APP_RST:
0114         lpc18xx_rgu_setclear_reset(rcdev, id, false);
0115     }
0116
0117     return 0;
0118 }
0119
0120 static int lpc18xx_rgu_status(struct reset_controller_dev *rcdev,
0121                   unsigned long id)
0122 {
0123     struct lpc18xx_rgu_data *rc = to_rgu_data(rcdev);
0124     u32 bit, offset = LPC18XX_RGU_ACTIVE_STATUS0;
0125
0126     offset += (id / LPC18XX_RGU_RESETS_PER_REG) * sizeof(u32);
0127     bit = 1 << (id % LPC18XX_RGU_RESETS_PER_REG);
0128
0129     return !(readl(rc->base + offset) & bit);
0130 }
0131
0132 static const struct reset_control_ops lpc18xx_rgu_ops = {
0133     .reset      = lpc18xx_rgu_reset,
0134     .assert     = lpc18xx_rgu_assert,
0135     .deassert   = lpc18xx_rgu_deassert,
0136     .status     = lpc18xx_rgu_status,
0137 };
0138
0139 static int lpc18xx_rgu_probe(struct platform_device *pdev)
0140 {
0141     struct lpc18xx_rgu_data *rc;
0142     struct resource *res;
0143     u32 fcclk, firc;
0144     int ret;
0145
0146     rc = devm_kzalloc(&pdev->dev, sizeof(*rc), GFP_KERNEL);
0147     if (!rc)
0148         return -ENOMEM;
0149
0150     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0151     rc->base = devm_ioremap_resource(&pdev->dev, res);
0152     if (IS_ERR(rc->base))
0153         return PTR_ERR(rc->base);
0154
0155     rc->clk_reg = devm_clk_get(&pdev->dev, "reg");
0156     if (IS_ERR(rc->clk_reg)) {
0157         dev_err(&pdev->dev, "reg clock not found\n");
0158         return PTR_ERR(rc->clk_reg);
0159     }
0160
0161     rc->clk_delay = devm_clk_get(&pdev->dev, "delay");
0162     if (IS_ERR(rc->clk_delay)) {
0163         dev_err(&pdev->dev, "delay clock not found\n");
0164         return PTR_ERR(rc->clk_delay);
0165     }
0166
0167     ret = clk_prepare_enable(rc->clk_reg);
0168     if (ret) {
0169         dev_err(&pdev->dev, "unable to enable reg clock\n");
0170         return ret;
0171     }
0172
0173     ret = clk_prepare_enable(rc->clk_delay);
0174     if (ret) {
0175         dev_err(&pdev->dev, "unable to enable delay clock\n");
0176         goto dis_clk_reg;
0177     }
0178
0179     fcclk = clk_get_rate(rc->clk_reg) / USEC_PER_SEC;
0180     firc = clk_get_rate(rc->clk_delay) / USEC_PER_SEC;
0181     if (fcclk == 0 || firc == 0)
0182         rc->delay_us = 2;
0183     else
0184         rc->delay_us = DIV_ROUND_UP(fcclk, firc * firc);
0185
0186     spin_lock_init(&rc->lock);
0187
0188     rc->rcdev.owner = THIS_MODULE;
0189     rc->rcdev.nr_resets = 64;
0190     rc->rcdev.ops = &lpc18xx_rgu_ops;
0191     rc->rcdev.of_node = pdev->dev.of_node;
0192
0193     platform_set_drvdata(pdev, rc);
0194
0195     ret = reset_controller_register(&rc->rcdev);
0196     if (ret) {
0197         dev_err(&pdev->dev, "unable to register device\n");
0198         goto dis_clks;
0199     }
0200
0201     rc->restart_nb.priority = 192,
0202     rc->restart_nb.notifier_call = lpc18xx_rgu_restart,
0203     ret = register_restart_handler(&rc->restart_nb);
0204     if (ret)
0205         dev_warn(&pdev->dev, "failed to register restart handler\n");
0206
0207     return 0;
0208
0209 dis_clks:
0210     clk_disable_unprepare(rc->clk_delay);
0211 dis_clk_reg:
0212     clk_disable_unprepare(rc->clk_reg);
0213
0214     return ret;
0215 }
0216
0217 static const struct of_device_id lpc18xx_rgu_match[] = {
0218     { .compatible = "nxp,lpc1850-rgu" },
0219     { }
0220 };
0221
0222 static struct platform_driver lpc18xx_rgu_driver = {
0223     .probe  = lpc18xx_rgu_probe,
0224     .driver = {
0225         .name           = "lpc18xx-reset",
0226         .of_match_table     = lpc18xx_rgu_match,
0227         .suppress_bind_attrs    = true,
0228     },
0229 };
0230 builtin_platform_driver(lpc18xx_rgu_driver);