drivers/reset/reset-intel-gw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2019 Intel Corporation.
0004  * Lei Chuanhua <Chuanhua.lei@intel.com>
0005  */
0006
0007 #include <linux/bitfield.h>
0008 #include <linux/init.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/reboot.h>
0012 #include <linux/regmap.h>
0013 #include <linux/reset-controller.h>
0014
0015 #define RCU_RST_STAT    0x0024
0016 #define RCU_RST_REQ 0x0048
0017
0018 #define REG_OFFSET_MASK GENMASK(31, 16)
0019 #define BIT_OFFSET_MASK GENMASK(15, 8)
0020 #define STAT_BIT_OFFSET_MASK    GENMASK(7, 0)
0021
0022 #define to_reset_data(x)    container_of(x, struct intel_reset_data, rcdev)
0023
0024 struct intel_reset_soc {
0025     bool legacy;
0026     u32 reset_cell_count;
0027 };
0028
0029 struct intel_reset_data {
0030     struct reset_controller_dev rcdev;
0031     struct notifier_block restart_nb;
0032     const struct intel_reset_soc *soc_data;
0033     struct regmap *regmap;
0034     struct device *dev;
0035     u32 reboot_id;
0036 };
0037
0038 static const struct regmap_config intel_rcu_regmap_config = {
0039     .name =     "intel-reset",
0040     .reg_bits = 32,
0041     .reg_stride =   4,
0042     .val_bits = 32,
0043     .fast_io =  true,
0044 };
0045
0046 /*
0047  * Reset status register offset relative to
0048  * the reset control register(X) is X + 4
0049  */
0050 static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data,
0051                      unsigned long id, u32 *rst_req,
0052                      u32 *req_bit, u32 *stat_bit)
0053 {
0054     *rst_req = FIELD_GET(REG_OFFSET_MASK, id);
0055     *req_bit = FIELD_GET(BIT_OFFSET_MASK, id);
0056
0057     if (data->soc_data->legacy)
0058         *stat_bit = FIELD_GET(STAT_BIT_OFFSET_MASK, id);
0059     else
0060         *stat_bit = *req_bit;
0061
0062     if (data->soc_data->legacy && *rst_req == RCU_RST_REQ)
0063         return RCU_RST_STAT;
0064     else
0065         return *rst_req + 0x4;
0066 }
0067
0068 static int intel_set_clr_bits(struct intel_reset_data *data, unsigned long id,
0069                   bool set)
0070 {
0071     u32 rst_req, req_bit, rst_stat, stat_bit, val;
0072     int ret;
0073
0074     rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req,
0075                          &req_bit, &stat_bit);
0076
0077     val = set ? BIT(req_bit) : 0;
0078     ret = regmap_update_bits(data->regmap, rst_req,  BIT(req_bit), val);
0079     if (ret)
0080         return ret;
0081
0082     return regmap_read_poll_timeout(data->regmap, rst_stat, val,
0083                     set == !!(val & BIT(stat_bit)), 20,
0084                     200);
0085 }
0086
0087 static int intel_assert_device(struct reset_controller_dev *rcdev,
0088                    unsigned long id)
0089 {
0090     struct intel_reset_data *data = to_reset_data(rcdev);
0091     int ret;
0092
0093     ret = intel_set_clr_bits(data, id, true);
0094     if (ret)
0095         dev_err(data->dev, "Reset assert failed %d\n", ret);
0096
0097     return ret;
0098 }
0099
0100 static int intel_deassert_device(struct reset_controller_dev *rcdev,
0101                  unsigned long id)
0102 {
0103     struct intel_reset_data *data = to_reset_data(rcdev);
0104     int ret;
0105
0106     ret = intel_set_clr_bits(data, id, false);
0107     if (ret)
0108         dev_err(data->dev, "Reset deassert failed %d\n", ret);
0109
0110     return ret;
0111 }
0112
0113 static int intel_reset_status(struct reset_controller_dev *rcdev,
0114                   unsigned long id)
0115 {
0116     struct intel_reset_data *data = to_reset_data(rcdev);
0117     u32 rst_req, req_bit, rst_stat, stat_bit, val;
0118     int ret;
0119
0120     rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req,
0121                          &req_bit, &stat_bit);
0122     ret = regmap_read(data->regmap, rst_stat, &val);
0123     if (ret)
0124         return ret;
0125
0126     return !!(val & BIT(stat_bit));
0127 }
0128
0129 static const struct reset_control_ops intel_reset_ops = {
0130     .assert =   intel_assert_device,
0131     .deassert = intel_deassert_device,
0132     .status =   intel_reset_status,
0133 };
0134
0135 static int intel_reset_xlate(struct reset_controller_dev *rcdev,
0136                  const struct of_phandle_args *spec)
0137 {
0138     struct intel_reset_data *data = to_reset_data(rcdev);
0139     u32 id;
0140
0141     if (spec->args[1] > 31)
0142         return -EINVAL;
0143
0144     id = FIELD_PREP(REG_OFFSET_MASK, spec->args[0]);
0145     id |= FIELD_PREP(BIT_OFFSET_MASK, spec->args[1]);
0146
0147     if (data->soc_data->legacy) {
0148         if (spec->args[2] > 31)
0149             return -EINVAL;
0150
0151         id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, spec->args[2]);
0152     }
0153
0154     return id;
0155 }
0156
0157 static int intel_reset_restart_handler(struct notifier_block *nb,
0158                        unsigned long action, void *data)
0159 {
0160     struct intel_reset_data *reset_data;
0161
0162     reset_data = container_of(nb, struct intel_reset_data, restart_nb);
0163     intel_assert_device(&reset_data->rcdev, reset_data->reboot_id);
0164
0165     return NOTIFY_DONE;
0166 }
0167
0168 static int intel_reset_probe(struct platform_device *pdev)
0169 {
0170     struct device_node *np = pdev->dev.of_node;
0171     struct device *dev = &pdev->dev;
0172     struct intel_reset_data *data;
0173     void __iomem *base;
0174     u32 rb_id[3];
0175     int ret;
0176
0177     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0178     if (!data)
0179         return -ENOMEM;
0180
0181     data->soc_data = of_device_get_match_data(dev);
0182     if (!data->soc_data)
0183         return -ENODEV;
0184
0185     base = devm_platform_ioremap_resource(pdev, 0);
0186     if (IS_ERR(base))
0187         return PTR_ERR(base);
0188
0189     data->regmap = devm_regmap_init_mmio(dev, base,
0190                          &intel_rcu_regmap_config);
0191     if (IS_ERR(data->regmap)) {
0192         dev_err(dev, "regmap initialization failed\n");
0193         return PTR_ERR(data->regmap);
0194     }
0195
0196     ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id,
0197                          data->soc_data->reset_cell_count);
0198     if (ret) {
0199         dev_err(dev, "Failed to get global reset offset!\n");
0200         return ret;
0201     }
0202
0203     data->dev =         dev;
0204     data->rcdev.of_node =       np;
0205     data->rcdev.owner =     dev->driver->owner;
0206     data->rcdev.ops =       &intel_reset_ops;
0207     data->rcdev.of_xlate =      intel_reset_xlate;
0208     data->rcdev.of_reset_n_cells =  data->soc_data->reset_cell_count;
0209     ret = devm_reset_controller_register(&pdev->dev, &data->rcdev);
0210     if (ret)
0211         return ret;
0212
0213     data->reboot_id = FIELD_PREP(REG_OFFSET_MASK, rb_id[0]);
0214     data->reboot_id |= FIELD_PREP(BIT_OFFSET_MASK, rb_id[1]);
0215
0216     if (data->soc_data->legacy)
0217         data->reboot_id |= FIELD_PREP(STAT_BIT_OFFSET_MASK, rb_id[2]);
0218
0219     data->restart_nb.notifier_call =    intel_reset_restart_handler;
0220     data->restart_nb.priority =     128;
0221     register_restart_handler(&data->restart_nb);
0222
0223     return 0;
0224 }
0225
0226 static const struct intel_reset_soc xrx200_data = {
0227     .legacy =       true,
0228     .reset_cell_count = 3,
0229 };
0230
0231 static const struct intel_reset_soc lgm_data = {
0232     .legacy =       false,
0233     .reset_cell_count = 2,
0234 };
0235
0236 static const struct of_device_id intel_reset_match[] = {
0237     { .compatible = "intel,rcu-lgm", .data = &lgm_data },
0238     { .compatible = "intel,rcu-xrx200", .data = &xrx200_data },
0239     {}
0240 };
0241
0242 static struct platform_driver intel_reset_driver = {
0243     .probe = intel_reset_probe,
0244     .driver = {
0245         .name = "intel-reset",
0246         .of_match_table = intel_reset_match,
0247     },
0248 };
0249
0250 static int __init intel_reset_init(void)
0251 {
0252     return platform_driver_register(&intel_reset_driver);
0253 }
0254
0255 /*
0256  * RCU is system core entity which is in Always On Domain whose clocks
0257  * or resource initialization happens in system core initialization.
0258  * Also, it is required for most of the platform or architecture
0259  * specific devices to perform reset operation as part of initialization.
0260  * So perform RCU as post core initialization.
0261  */
0262 postcore_initcall(intel_reset_init);