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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017, Impinj, Inc.
0004  *
0005  * i.MX7 System Reset Controller (SRC) driver
0006  *
0007  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
0008  */
0009 
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/reset-controller.h>
0015 #include <linux/regmap.h>
0016 #include <dt-bindings/reset/imx7-reset.h>
0017 #include <dt-bindings/reset/imx8mq-reset.h>
0018 #include <dt-bindings/reset/imx8mp-reset.h>
0019 
0020 struct imx7_src_signal {
0021     unsigned int offset, bit;
0022 };
0023 
0024 struct imx7_src_variant {
0025     const struct imx7_src_signal *signals;
0026     unsigned int signals_num;
0027     struct reset_control_ops ops;
0028 };
0029 
0030 struct imx7_src {
0031     struct reset_controller_dev rcdev;
0032     struct regmap *regmap;
0033     const struct imx7_src_signal *signals;
0034 };
0035 
0036 enum imx7_src_registers {
0037     SRC_A7RCR0      = 0x0004,
0038     SRC_M4RCR       = 0x000c,
0039     SRC_ERCR        = 0x0014,
0040     SRC_HSICPHY_RCR     = 0x001c,
0041     SRC_USBOPHY1_RCR    = 0x0020,
0042     SRC_USBOPHY2_RCR    = 0x0024,
0043     SRC_MIPIPHY_RCR     = 0x0028,
0044     SRC_PCIEPHY_RCR     = 0x002c,
0045     SRC_DDRC_RCR        = 0x1000,
0046 };
0047 
0048 static int imx7_reset_update(struct imx7_src *imx7src,
0049                  unsigned long id, unsigned int value)
0050 {
0051     const struct imx7_src_signal *signal = &imx7src->signals[id];
0052 
0053     return regmap_update_bits(imx7src->regmap,
0054                   signal->offset, signal->bit, value);
0055 }
0056 
0057 static const struct imx7_src_signal imx7_src_signals[IMX7_RESET_NUM] = {
0058     [IMX7_RESET_A7_CORE_POR_RESET0] = { SRC_A7RCR0, BIT(0) },
0059     [IMX7_RESET_A7_CORE_POR_RESET1] = { SRC_A7RCR0, BIT(1) },
0060     [IMX7_RESET_A7_CORE_RESET0]     = { SRC_A7RCR0, BIT(4) },
0061     [IMX7_RESET_A7_CORE_RESET1] = { SRC_A7RCR0, BIT(5) },
0062     [IMX7_RESET_A7_DBG_RESET0]  = { SRC_A7RCR0, BIT(8) },
0063     [IMX7_RESET_A7_DBG_RESET1]  = { SRC_A7RCR0, BIT(9) },
0064     [IMX7_RESET_A7_ETM_RESET0]  = { SRC_A7RCR0, BIT(12) },
0065     [IMX7_RESET_A7_ETM_RESET1]  = { SRC_A7RCR0, BIT(13) },
0066     [IMX7_RESET_A7_SOC_DBG_RESET]   = { SRC_A7RCR0, BIT(20) },
0067     [IMX7_RESET_A7_L2RESET]     = { SRC_A7RCR0, BIT(21) },
0068     [IMX7_RESET_SW_M4C_RST]     = { SRC_M4RCR, BIT(1) },
0069     [IMX7_RESET_SW_M4P_RST]     = { SRC_M4RCR, BIT(2) },
0070     [IMX7_RESET_EIM_RST]        = { SRC_ERCR, BIT(0) },
0071     [IMX7_RESET_HSICPHY_PORT_RST]   = { SRC_HSICPHY_RCR, BIT(1) },
0072     [IMX7_RESET_USBPHY1_POR]    = { SRC_USBOPHY1_RCR, BIT(0) },
0073     [IMX7_RESET_USBPHY1_PORT_RST]   = { SRC_USBOPHY1_RCR, BIT(1) },
0074     [IMX7_RESET_USBPHY2_POR]    = { SRC_USBOPHY2_RCR, BIT(0) },
0075     [IMX7_RESET_USBPHY2_PORT_RST]   = { SRC_USBOPHY2_RCR, BIT(1) },
0076     [IMX7_RESET_MIPI_PHY_MRST]  = { SRC_MIPIPHY_RCR, BIT(1) },
0077     [IMX7_RESET_MIPI_PHY_SRST]  = { SRC_MIPIPHY_RCR, BIT(2) },
0078     [IMX7_RESET_PCIEPHY]        = { SRC_PCIEPHY_RCR, BIT(2) | BIT(1) },
0079     [IMX7_RESET_PCIEPHY_PERST]  = { SRC_PCIEPHY_RCR, BIT(3) },
0080     [IMX7_RESET_PCIE_CTRL_APPS_EN]  = { SRC_PCIEPHY_RCR, BIT(6) },
0081     [IMX7_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
0082     [IMX7_RESET_DDRC_PRST]      = { SRC_DDRC_RCR, BIT(0) },
0083     [IMX7_RESET_DDRC_CORE_RST]  = { SRC_DDRC_RCR, BIT(1) },
0084 };
0085 
0086 static struct imx7_src *to_imx7_src(struct reset_controller_dev *rcdev)
0087 {
0088     return container_of(rcdev, struct imx7_src, rcdev);
0089 }
0090 
0091 static int imx7_reset_set(struct reset_controller_dev *rcdev,
0092               unsigned long id, bool assert)
0093 {
0094     struct imx7_src *imx7src = to_imx7_src(rcdev);
0095     const unsigned int bit = imx7src->signals[id].bit;
0096     unsigned int value = assert ? bit : 0;
0097 
0098     switch (id) {
0099     case IMX7_RESET_PCIEPHY:
0100         /*
0101          * wait for more than 10us to release phy g_rst and
0102          * btnrst
0103          */
0104         if (!assert)
0105             udelay(10);
0106         break;
0107 
0108     case IMX7_RESET_PCIE_CTRL_APPS_EN:
0109         value = assert ? 0 : bit;
0110         break;
0111     }
0112 
0113     return imx7_reset_update(imx7src, id, value);
0114 }
0115 
0116 static int imx7_reset_assert(struct reset_controller_dev *rcdev,
0117                  unsigned long id)
0118 {
0119     return imx7_reset_set(rcdev, id, true);
0120 }
0121 
0122 static int imx7_reset_deassert(struct reset_controller_dev *rcdev,
0123                    unsigned long id)
0124 {
0125     return imx7_reset_set(rcdev, id, false);
0126 }
0127 
0128 static const struct imx7_src_variant variant_imx7 = {
0129     .signals = imx7_src_signals,
0130     .signals_num = ARRAY_SIZE(imx7_src_signals),
0131     .ops = {
0132         .assert   = imx7_reset_assert,
0133         .deassert = imx7_reset_deassert,
0134     },
0135 };
0136 
0137 enum imx8mq_src_registers {
0138     SRC_A53RCR0     = 0x0004,
0139     SRC_HDMI_RCR        = 0x0030,
0140     SRC_DISP_RCR        = 0x0034,
0141     SRC_GPU_RCR     = 0x0040,
0142     SRC_VPU_RCR     = 0x0044,
0143     SRC_PCIE2_RCR       = 0x0048,
0144     SRC_MIPIPHY1_RCR    = 0x004c,
0145     SRC_MIPIPHY2_RCR    = 0x0050,
0146     SRC_DDRC2_RCR       = 0x1004,
0147 };
0148 
0149 enum imx8mp_src_registers {
0150     SRC_SUPERMIX_RCR    = 0x0018,
0151     SRC_AUDIOMIX_RCR    = 0x001c,
0152     SRC_MLMIX_RCR       = 0x0028,
0153     SRC_GPU2D_RCR       = 0x0038,
0154     SRC_GPU3D_RCR       = 0x003c,
0155     SRC_VPU_G1_RCR      = 0x0048,
0156     SRC_VPU_G2_RCR      = 0x004c,
0157     SRC_VPUVC8KE_RCR    = 0x0050,
0158     SRC_NOC_RCR     = 0x0054,
0159 };
0160 
0161 static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
0162     [IMX8MQ_RESET_A53_CORE_POR_RESET0]  = { SRC_A53RCR0, BIT(0) },
0163     [IMX8MQ_RESET_A53_CORE_POR_RESET1]  = { SRC_A53RCR0, BIT(1) },
0164     [IMX8MQ_RESET_A53_CORE_POR_RESET2]  = { SRC_A53RCR0, BIT(2) },
0165     [IMX8MQ_RESET_A53_CORE_POR_RESET3]  = { SRC_A53RCR0, BIT(3) },
0166     [IMX8MQ_RESET_A53_CORE_RESET0]      = { SRC_A53RCR0, BIT(4) },
0167     [IMX8MQ_RESET_A53_CORE_RESET1]      = { SRC_A53RCR0, BIT(5) },
0168     [IMX8MQ_RESET_A53_CORE_RESET2]      = { SRC_A53RCR0, BIT(6) },
0169     [IMX8MQ_RESET_A53_CORE_RESET3]      = { SRC_A53RCR0, BIT(7) },
0170     [IMX8MQ_RESET_A53_DBG_RESET0]       = { SRC_A53RCR0, BIT(8) },
0171     [IMX8MQ_RESET_A53_DBG_RESET1]       = { SRC_A53RCR0, BIT(9) },
0172     [IMX8MQ_RESET_A53_DBG_RESET2]       = { SRC_A53RCR0, BIT(10) },
0173     [IMX8MQ_RESET_A53_DBG_RESET3]       = { SRC_A53RCR0, BIT(11) },
0174     [IMX8MQ_RESET_A53_ETM_RESET0]       = { SRC_A53RCR0, BIT(12) },
0175     [IMX8MQ_RESET_A53_ETM_RESET1]       = { SRC_A53RCR0, BIT(13) },
0176     [IMX8MQ_RESET_A53_ETM_RESET2]       = { SRC_A53RCR0, BIT(14) },
0177     [IMX8MQ_RESET_A53_ETM_RESET3]       = { SRC_A53RCR0, BIT(15) },
0178     [IMX8MQ_RESET_A53_SOC_DBG_RESET]    = { SRC_A53RCR0, BIT(20) },
0179     [IMX8MQ_RESET_A53_L2RESET]      = { SRC_A53RCR0, BIT(21) },
0180     [IMX8MQ_RESET_SW_NON_SCLR_M4C_RST]  = { SRC_M4RCR, BIT(0) },
0181     [IMX8MQ_RESET_SW_M4C_RST]       = { SRC_M4RCR, BIT(1) },
0182     [IMX8MQ_RESET_SW_M4P_RST]       = { SRC_M4RCR, BIT(2) },
0183     [IMX8MQ_RESET_M4_ENABLE]        = { SRC_M4RCR, BIT(3) },
0184     [IMX8MQ_RESET_OTG1_PHY_RESET]       = { SRC_USBOPHY1_RCR, BIT(0) },
0185     [IMX8MQ_RESET_OTG2_PHY_RESET]       = { SRC_USBOPHY2_RCR, BIT(0) },
0186     [IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N]    = { SRC_MIPIPHY_RCR, BIT(1) },
0187     [IMX8MQ_RESET_MIPI_DSI_RESET_N]     = { SRC_MIPIPHY_RCR, BIT(2) },
0188     [IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
0189     [IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
0190     [IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N]    = { SRC_MIPIPHY_RCR, BIT(5) },
0191     [IMX8MQ_RESET_PCIEPHY]          = { SRC_PCIEPHY_RCR,
0192                             BIT(2) | BIT(1) },
0193     [IMX8MQ_RESET_PCIEPHY_PERST]        = { SRC_PCIEPHY_RCR, BIT(3) },
0194     [IMX8MQ_RESET_PCIE_CTRL_APPS_EN]    = { SRC_PCIEPHY_RCR, BIT(6) },
0195     [IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF]   = { SRC_PCIEPHY_RCR, BIT(11) },
0196     [IMX8MQ_RESET_HDMI_PHY_APB_RESET]   = { SRC_HDMI_RCR, BIT(0) },
0197     [IMX8MQ_RESET_DISP_RESET]       = { SRC_DISP_RCR, BIT(0) },
0198     [IMX8MQ_RESET_GPU_RESET]        = { SRC_GPU_RCR, BIT(0) },
0199     [IMX8MQ_RESET_VPU_RESET]        = { SRC_VPU_RCR, BIT(0) },
0200     [IMX8MQ_RESET_PCIEPHY2]         = { SRC_PCIE2_RCR,
0201                             BIT(2) | BIT(1) },
0202     [IMX8MQ_RESET_PCIEPHY2_PERST]       = { SRC_PCIE2_RCR, BIT(3) },
0203     [IMX8MQ_RESET_PCIE2_CTRL_APPS_EN]   = { SRC_PCIE2_RCR, BIT(6) },
0204     [IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF]  = { SRC_PCIE2_RCR, BIT(11) },
0205     [IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
0206     [IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET]  = { SRC_MIPIPHY1_RCR, BIT(1) },
0207     [IMX8MQ_RESET_MIPI_CSI1_ESC_RESET]  = { SRC_MIPIPHY1_RCR, BIT(2) },
0208     [IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
0209     [IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET]  = { SRC_MIPIPHY2_RCR, BIT(1) },
0210     [IMX8MQ_RESET_MIPI_CSI2_ESC_RESET]  = { SRC_MIPIPHY2_RCR, BIT(2) },
0211     [IMX8MQ_RESET_DDRC1_PRST]       = { SRC_DDRC_RCR, BIT(0) },
0212     [IMX8MQ_RESET_DDRC1_CORE_RESET]     = { SRC_DDRC_RCR, BIT(1) },
0213     [IMX8MQ_RESET_DDRC1_PHY_RESET]      = { SRC_DDRC_RCR, BIT(2) },
0214     [IMX8MQ_RESET_DDRC2_PHY_RESET]      = { SRC_DDRC2_RCR, BIT(0) },
0215     [IMX8MQ_RESET_DDRC2_CORE_RESET]     = { SRC_DDRC2_RCR, BIT(1) },
0216     [IMX8MQ_RESET_DDRC2_PRST]       = { SRC_DDRC2_RCR, BIT(2) },
0217 };
0218 
0219 static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
0220                 unsigned long id, bool assert)
0221 {
0222     struct imx7_src *imx7src = to_imx7_src(rcdev);
0223     const unsigned int bit = imx7src->signals[id].bit;
0224     unsigned int value = assert ? bit : 0;
0225 
0226     switch (id) {
0227     case IMX8MQ_RESET_PCIEPHY:
0228     case IMX8MQ_RESET_PCIEPHY2:
0229         /*
0230          * wait for more than 10us to release phy g_rst and
0231          * btnrst
0232          */
0233         if (!assert)
0234             udelay(10);
0235         break;
0236 
0237     case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
0238     case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
0239     case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
0240     case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
0241     case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
0242     case IMX8MQ_RESET_MIPI_DSI_RESET_N:
0243     case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N:
0244     case IMX8MQ_RESET_M4_ENABLE:
0245         value = assert ? 0 : bit;
0246         break;
0247     }
0248 
0249     return imx7_reset_update(imx7src, id, value);
0250 }
0251 
0252 static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
0253                    unsigned long id)
0254 {
0255     return imx8mq_reset_set(rcdev, id, true);
0256 }
0257 
0258 static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
0259                  unsigned long id)
0260 {
0261     return imx8mq_reset_set(rcdev, id, false);
0262 }
0263 
0264 static const struct imx7_src_variant variant_imx8mq = {
0265     .signals = imx8mq_src_signals,
0266     .signals_num = ARRAY_SIZE(imx8mq_src_signals),
0267     .ops = {
0268         .assert   = imx8mq_reset_assert,
0269         .deassert = imx8mq_reset_deassert,
0270     },
0271 };
0272 
0273 static const struct imx7_src_signal imx8mp_src_signals[IMX8MP_RESET_NUM] = {
0274     [IMX8MP_RESET_A53_CORE_POR_RESET0]  = { SRC_A53RCR0, BIT(0) },
0275     [IMX8MP_RESET_A53_CORE_POR_RESET1]  = { SRC_A53RCR0, BIT(1) },
0276     [IMX8MP_RESET_A53_CORE_POR_RESET2]  = { SRC_A53RCR0, BIT(2) },
0277     [IMX8MP_RESET_A53_CORE_POR_RESET3]  = { SRC_A53RCR0, BIT(3) },
0278     [IMX8MP_RESET_A53_CORE_RESET0]      = { SRC_A53RCR0, BIT(4) },
0279     [IMX8MP_RESET_A53_CORE_RESET1]      = { SRC_A53RCR0, BIT(5) },
0280     [IMX8MP_RESET_A53_CORE_RESET2]      = { SRC_A53RCR0, BIT(6) },
0281     [IMX8MP_RESET_A53_CORE_RESET3]      = { SRC_A53RCR0, BIT(7) },
0282     [IMX8MP_RESET_A53_DBG_RESET0]       = { SRC_A53RCR0, BIT(8) },
0283     [IMX8MP_RESET_A53_DBG_RESET1]       = { SRC_A53RCR0, BIT(9) },
0284     [IMX8MP_RESET_A53_DBG_RESET2]       = { SRC_A53RCR0, BIT(10) },
0285     [IMX8MP_RESET_A53_DBG_RESET3]       = { SRC_A53RCR0, BIT(11) },
0286     [IMX8MP_RESET_A53_ETM_RESET0]       = { SRC_A53RCR0, BIT(12) },
0287     [IMX8MP_RESET_A53_ETM_RESET1]       = { SRC_A53RCR0, BIT(13) },
0288     [IMX8MP_RESET_A53_ETM_RESET2]       = { SRC_A53RCR0, BIT(14) },
0289     [IMX8MP_RESET_A53_ETM_RESET3]       = { SRC_A53RCR0, BIT(15) },
0290     [IMX8MP_RESET_A53_SOC_DBG_RESET]    = { SRC_A53RCR0, BIT(20) },
0291     [IMX8MP_RESET_A53_L2RESET]      = { SRC_A53RCR0, BIT(21) },
0292     [IMX8MP_RESET_SW_NON_SCLR_M7C_RST]  = { SRC_M4RCR, BIT(0) },
0293     [IMX8MP_RESET_OTG1_PHY_RESET]       = { SRC_USBOPHY1_RCR, BIT(0) },
0294     [IMX8MP_RESET_OTG2_PHY_RESET]       = { SRC_USBOPHY2_RCR, BIT(0) },
0295     [IMX8MP_RESET_SUPERMIX_RESET]       = { SRC_SUPERMIX_RCR, BIT(0) },
0296     [IMX8MP_RESET_AUDIOMIX_RESET]       = { SRC_AUDIOMIX_RCR, BIT(0) },
0297     [IMX8MP_RESET_MLMIX_RESET]      = { SRC_MLMIX_RCR, BIT(0) },
0298     [IMX8MP_RESET_PCIEPHY]          = { SRC_PCIEPHY_RCR, BIT(2) },
0299     [IMX8MP_RESET_PCIEPHY_PERST]        = { SRC_PCIEPHY_RCR, BIT(3) },
0300     [IMX8MP_RESET_PCIE_CTRL_APPS_EN]    = { SRC_PCIEPHY_RCR, BIT(6) },
0301     [IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF]   = { SRC_PCIEPHY_RCR, BIT(11) },
0302     [IMX8MP_RESET_HDMI_PHY_APB_RESET]   = { SRC_HDMI_RCR, BIT(0) },
0303     [IMX8MP_RESET_MEDIA_RESET]      = { SRC_DISP_RCR, BIT(0) },
0304     [IMX8MP_RESET_GPU2D_RESET]      = { SRC_GPU2D_RCR, BIT(0) },
0305     [IMX8MP_RESET_GPU3D_RESET]      = { SRC_GPU3D_RCR, BIT(0) },
0306     [IMX8MP_RESET_GPU_RESET]        = { SRC_GPU_RCR, BIT(0) },
0307     [IMX8MP_RESET_VPU_RESET]        = { SRC_VPU_RCR, BIT(0) },
0308     [IMX8MP_RESET_VPU_G1_RESET]     = { SRC_VPU_G1_RCR, BIT(0) },
0309     [IMX8MP_RESET_VPU_G2_RESET]     = { SRC_VPU_G2_RCR, BIT(0) },
0310     [IMX8MP_RESET_VPUVC8KE_RESET]       = { SRC_VPUVC8KE_RCR, BIT(0) },
0311     [IMX8MP_RESET_NOC_RESET]        = { SRC_NOC_RCR, BIT(0) },
0312 };
0313 
0314 static int imx8mp_reset_set(struct reset_controller_dev *rcdev,
0315                 unsigned long id, bool assert)
0316 {
0317     struct imx7_src *imx7src = to_imx7_src(rcdev);
0318     const unsigned int bit = imx7src->signals[id].bit;
0319     unsigned int value = assert ? bit : 0;
0320 
0321     switch (id) {
0322     case IMX8MP_RESET_PCIEPHY:
0323         /*
0324          * wait for more than 10us to release phy g_rst and
0325          * btnrst
0326          */
0327         if (!assert)
0328             udelay(10);
0329         break;
0330 
0331     case IMX8MP_RESET_PCIE_CTRL_APPS_EN:
0332     case IMX8MP_RESET_PCIEPHY_PERST:
0333         value = assert ? 0 : bit;
0334         break;
0335     }
0336 
0337     return imx7_reset_update(imx7src, id, value);
0338 }
0339 
0340 static int imx8mp_reset_assert(struct reset_controller_dev *rcdev,
0341                    unsigned long id)
0342 {
0343     return imx8mp_reset_set(rcdev, id, true);
0344 }
0345 
0346 static int imx8mp_reset_deassert(struct reset_controller_dev *rcdev,
0347                  unsigned long id)
0348 {
0349     return imx8mp_reset_set(rcdev, id, false);
0350 }
0351 
0352 static const struct imx7_src_variant variant_imx8mp = {
0353     .signals = imx8mp_src_signals,
0354     .signals_num = ARRAY_SIZE(imx8mp_src_signals),
0355     .ops = {
0356         .assert   = imx8mp_reset_assert,
0357         .deassert = imx8mp_reset_deassert,
0358     },
0359 };
0360 
0361 static int imx7_reset_probe(struct platform_device *pdev)
0362 {
0363     struct imx7_src *imx7src;
0364     struct device *dev = &pdev->dev;
0365     struct regmap_config config = { .name = "src" };
0366     const struct imx7_src_variant *variant = of_device_get_match_data(dev);
0367 
0368     imx7src = devm_kzalloc(dev, sizeof(*imx7src), GFP_KERNEL);
0369     if (!imx7src)
0370         return -ENOMEM;
0371 
0372     imx7src->signals = variant->signals;
0373     imx7src->regmap = syscon_node_to_regmap(dev->of_node);
0374     if (IS_ERR(imx7src->regmap)) {
0375         dev_err(dev, "Unable to get imx7-src regmap");
0376         return PTR_ERR(imx7src->regmap);
0377     }
0378     regmap_attach_dev(dev, imx7src->regmap, &config);
0379 
0380     imx7src->rcdev.owner     = THIS_MODULE;
0381     imx7src->rcdev.nr_resets = variant->signals_num;
0382     imx7src->rcdev.ops       = &variant->ops;
0383     imx7src->rcdev.of_node   = dev->of_node;
0384 
0385     return devm_reset_controller_register(dev, &imx7src->rcdev);
0386 }
0387 
0388 static const struct of_device_id imx7_reset_dt_ids[] = {
0389     { .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
0390     { .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
0391     { .compatible = "fsl,imx8mp-src", .data = &variant_imx8mp },
0392     { /* sentinel */ },
0393 };
0394 MODULE_DEVICE_TABLE(of, imx7_reset_dt_ids);
0395 
0396 static struct platform_driver imx7_reset_driver = {
0397     .probe  = imx7_reset_probe,
0398     .driver = {
0399         .name       = KBUILD_MODNAME,
0400         .of_match_table = imx7_reset_dt_ids,
0401     },
0402 };
0403 module_platform_driver(imx7_reset_driver);
0404 
0405 MODULE_AUTHOR("Andrey Smirnov <andrew.smirnov@gmail.com>");
0406 MODULE_DESCRIPTION("NXP i.MX7 reset driver");
0407 MODULE_LICENSE("GPL v2");
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