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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // wm8350.c  --  Voltage and current regulation for the Wolfson WM8350 PMIC
0004 //
0005 // Copyright 2007, 2008 Wolfson Microelectronics PLC.
0006 //
0007 // Author: Liam Girdwood
0008 //         linux@wolfsonmicro.com
0009 
0010 #include <linux/module.h>
0011 #include <linux/moduleparam.h>
0012 #include <linux/init.h>
0013 #include <linux/bitops.h>
0014 #include <linux/err.h>
0015 #include <linux/i2c.h>
0016 #include <linux/mfd/wm8350/core.h>
0017 #include <linux/mfd/wm8350/pmic.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/regulator/driver.h>
0020 #include <linux/regulator/machine.h>
0021 
0022 /* Maximum value possible for VSEL */
0023 #define WM8350_DCDC_MAX_VSEL 0x66
0024 
0025 /* Microamps */
0026 static const unsigned int isink_cur[] = {
0027     4,
0028     5,
0029     6,
0030     7,
0031     8,
0032     10,
0033     11,
0034     14,
0035     16,
0036     19,
0037     23,
0038     27,
0039     32,
0040     39,
0041     46,
0042     54,
0043     65,
0044     77,
0045     92,
0046     109,
0047     130,
0048     154,
0049     183,
0050     218,
0051     259,
0052     308,
0053     367,
0054     436,
0055     518,
0056     616,
0057     733,
0058     872,
0059     1037,
0060     1233,
0061     1466,
0062     1744,
0063     2073,
0064     2466,
0065     2933,
0066     3487,
0067     4147,
0068     4932,
0069     5865,
0070     6975,
0071     8294,
0072     9864,
0073     11730,
0074     13949,
0075     16589,
0076     19728,
0077     23460,
0078     27899,
0079     33178,
0080     39455,
0081     46920,
0082     55798,
0083     66355,
0084     78910,
0085     93840,
0086     111596,
0087     132710,
0088     157820,
0089     187681,
0090     223191
0091 };
0092 
0093 /* turn on ISINK followed by DCDC */
0094 static int wm8350_isink_enable(struct regulator_dev *rdev)
0095 {
0096     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0097     int isink = rdev_get_id(rdev);
0098 
0099     switch (isink) {
0100     case WM8350_ISINK_A:
0101         switch (wm8350->pmic.isink_A_dcdc) {
0102         case WM8350_DCDC_2:
0103         case WM8350_DCDC_5:
0104             wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
0105                     WM8350_CS1_ENA);
0106             wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
0107                     WM8350_CS1_DRIVE);
0108             wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
0109                     1 << (wm8350->pmic.isink_A_dcdc -
0110                           WM8350_DCDC_1));
0111             break;
0112         default:
0113             return -EINVAL;
0114         }
0115         break;
0116     case WM8350_ISINK_B:
0117         switch (wm8350->pmic.isink_B_dcdc) {
0118         case WM8350_DCDC_2:
0119         case WM8350_DCDC_5:
0120             wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
0121                     WM8350_CS2_ENA);
0122             wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
0123                     WM8350_CS2_DRIVE);
0124             wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
0125                     1 << (wm8350->pmic.isink_B_dcdc -
0126                           WM8350_DCDC_1));
0127             break;
0128         default:
0129             return -EINVAL;
0130         }
0131         break;
0132     default:
0133         return -EINVAL;
0134     }
0135     return 0;
0136 }
0137 
0138 static int wm8350_isink_disable(struct regulator_dev *rdev)
0139 {
0140     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0141     int isink = rdev_get_id(rdev);
0142 
0143     switch (isink) {
0144     case WM8350_ISINK_A:
0145         switch (wm8350->pmic.isink_A_dcdc) {
0146         case WM8350_DCDC_2:
0147         case WM8350_DCDC_5:
0148             wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
0149                       1 << (wm8350->pmic.isink_A_dcdc -
0150                         WM8350_DCDC_1));
0151             wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
0152                       WM8350_CS1_ENA);
0153             break;
0154         default:
0155             return -EINVAL;
0156         }
0157         break;
0158     case WM8350_ISINK_B:
0159         switch (wm8350->pmic.isink_B_dcdc) {
0160         case WM8350_DCDC_2:
0161         case WM8350_DCDC_5:
0162             wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
0163                       1 << (wm8350->pmic.isink_B_dcdc -
0164                         WM8350_DCDC_1));
0165             wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
0166                       WM8350_CS2_ENA);
0167             break;
0168         default:
0169             return -EINVAL;
0170         }
0171         break;
0172     default:
0173         return -EINVAL;
0174     }
0175     return 0;
0176 }
0177 
0178 static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
0179 {
0180     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0181     int isink = rdev_get_id(rdev);
0182 
0183     switch (isink) {
0184     case WM8350_ISINK_A:
0185         return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
0186             0x8000;
0187     case WM8350_ISINK_B:
0188         return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
0189             0x8000;
0190     }
0191     return -EINVAL;
0192 }
0193 
0194 static int wm8350_isink_enable_time(struct regulator_dev *rdev)
0195 {
0196     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0197     int isink = rdev_get_id(rdev);
0198     int reg;
0199 
0200     switch (isink) {
0201     case WM8350_ISINK_A:
0202         reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
0203         break;
0204     case WM8350_ISINK_B:
0205         reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
0206         break;
0207     default:
0208         return -EINVAL;
0209     }
0210 
0211     if (reg & WM8350_CS1_FLASH_MODE) {
0212         switch (reg & WM8350_CS1_ON_RAMP_MASK) {
0213         case 0:
0214             return 0;
0215         case 1:
0216             return 1950;
0217         case 2:
0218             return 3910;
0219         case 3:
0220             return 7800;
0221         }
0222     } else {
0223         switch (reg & WM8350_CS1_ON_RAMP_MASK) {
0224         case 0:
0225             return 0;
0226         case 1:
0227             return 250000;
0228         case 2:
0229             return 500000;
0230         case 3:
0231             return 1000000;
0232         }
0233     }
0234 
0235     return -EINVAL;
0236 }
0237 
0238 
0239 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
0240                u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
0241                u16 drive)
0242 {
0243     switch (isink) {
0244     case WM8350_ISINK_A:
0245         wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
0246                  (mode ? WM8350_CS1_FLASH_MODE : 0) |
0247                  (trigger ? WM8350_CS1_TRIGSRC : 0) |
0248                  duration | on_ramp | off_ramp | drive);
0249         break;
0250     case WM8350_ISINK_B:
0251         wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
0252                  (mode ? WM8350_CS2_FLASH_MODE : 0) |
0253                  (trigger ? WM8350_CS2_TRIGSRC : 0) |
0254                  duration | on_ramp | off_ramp | drive);
0255         break;
0256     default:
0257         return -EINVAL;
0258     }
0259     return 0;
0260 }
0261 EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
0262 
0263 static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
0264 {
0265     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0266     int sel, volt_reg, dcdc = rdev_get_id(rdev);
0267     u16 val;
0268 
0269     dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
0270 
0271     switch (dcdc) {
0272     case WM8350_DCDC_1:
0273         volt_reg = WM8350_DCDC1_LOW_POWER;
0274         break;
0275     case WM8350_DCDC_3:
0276         volt_reg = WM8350_DCDC3_LOW_POWER;
0277         break;
0278     case WM8350_DCDC_4:
0279         volt_reg = WM8350_DCDC4_LOW_POWER;
0280         break;
0281     case WM8350_DCDC_6:
0282         volt_reg = WM8350_DCDC6_LOW_POWER;
0283         break;
0284     case WM8350_DCDC_2:
0285     case WM8350_DCDC_5:
0286     default:
0287         return -EINVAL;
0288     }
0289 
0290     sel = regulator_map_voltage_linear(rdev, uV, uV);
0291     if (sel < 0)
0292         return sel;
0293 
0294     /* all DCDCs have same mV bits */
0295     val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
0296     wm8350_reg_write(wm8350, volt_reg, val | sel);
0297     return 0;
0298 }
0299 
0300 static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
0301 {
0302     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0303     int dcdc = rdev_get_id(rdev);
0304     u16 val;
0305 
0306     switch (dcdc) {
0307     case WM8350_DCDC_1:
0308         val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
0309             & ~WM8350_DCDC_HIB_MODE_MASK;
0310         wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
0311             val | wm8350->pmic.dcdc1_hib_mode);
0312         break;
0313     case WM8350_DCDC_3:
0314         val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
0315             & ~WM8350_DCDC_HIB_MODE_MASK;
0316         wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
0317             val | wm8350->pmic.dcdc3_hib_mode);
0318         break;
0319     case WM8350_DCDC_4:
0320         val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
0321             & ~WM8350_DCDC_HIB_MODE_MASK;
0322         wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
0323             val | wm8350->pmic.dcdc4_hib_mode);
0324         break;
0325     case WM8350_DCDC_6:
0326         val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
0327             & ~WM8350_DCDC_HIB_MODE_MASK;
0328         wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
0329             val | wm8350->pmic.dcdc6_hib_mode);
0330         break;
0331     case WM8350_DCDC_2:
0332     case WM8350_DCDC_5:
0333     default:
0334         return -EINVAL;
0335     }
0336 
0337     return 0;
0338 }
0339 
0340 static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
0341 {
0342     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0343     int dcdc = rdev_get_id(rdev);
0344     u16 val;
0345 
0346     switch (dcdc) {
0347     case WM8350_DCDC_1:
0348         val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
0349         wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
0350         wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
0351                  val | WM8350_DCDC_HIB_MODE_DIS);
0352         break;
0353     case WM8350_DCDC_3:
0354         val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
0355         wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
0356         wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
0357                  val | WM8350_DCDC_HIB_MODE_DIS);
0358         break;
0359     case WM8350_DCDC_4:
0360         val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
0361         wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
0362         wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
0363                  val | WM8350_DCDC_HIB_MODE_DIS);
0364         break;
0365     case WM8350_DCDC_6:
0366         val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
0367         wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
0368         wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
0369                  val | WM8350_DCDC_HIB_MODE_DIS);
0370         break;
0371     case WM8350_DCDC_2:
0372     case WM8350_DCDC_5:
0373     default:
0374         return -EINVAL;
0375     }
0376 
0377     return 0;
0378 }
0379 
0380 static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
0381 {
0382     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0383     int dcdc = rdev_get_id(rdev);
0384     u16 val;
0385 
0386     switch (dcdc) {
0387     case WM8350_DCDC_2:
0388         val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
0389             & ~WM8350_DC2_HIB_MODE_MASK;
0390         wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
0391             (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
0392         break;
0393     case WM8350_DCDC_5:
0394         val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
0395             & ~WM8350_DC5_HIB_MODE_MASK;
0396         wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
0397             (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
0398         break;
0399     default:
0400         return -EINVAL;
0401     }
0402     return 0;
0403 }
0404 
0405 static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
0406 {
0407     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0408     int dcdc = rdev_get_id(rdev);
0409     u16 val;
0410 
0411     switch (dcdc) {
0412     case WM8350_DCDC_2:
0413         val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
0414             & ~WM8350_DC2_HIB_MODE_MASK;
0415         wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
0416             (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
0417         break;
0418     case WM8350_DCDC_5:
0419         val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
0420             & ~WM8350_DC5_HIB_MODE_MASK;
0421         wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
0422             (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
0423         break;
0424     default:
0425         return -EINVAL;
0426     }
0427     return 0;
0428 }
0429 
0430 static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
0431     unsigned int mode)
0432 {
0433     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0434     int dcdc = rdev_get_id(rdev);
0435     u16 *hib_mode;
0436 
0437     switch (dcdc) {
0438     case WM8350_DCDC_1:
0439         hib_mode = &wm8350->pmic.dcdc1_hib_mode;
0440         break;
0441     case WM8350_DCDC_3:
0442         hib_mode = &wm8350->pmic.dcdc3_hib_mode;
0443         break;
0444     case WM8350_DCDC_4:
0445         hib_mode = &wm8350->pmic.dcdc4_hib_mode;
0446         break;
0447     case WM8350_DCDC_6:
0448         hib_mode = &wm8350->pmic.dcdc6_hib_mode;
0449         break;
0450     case WM8350_DCDC_2:
0451     case WM8350_DCDC_5:
0452     default:
0453         return -EINVAL;
0454     }
0455 
0456     switch (mode) {
0457     case REGULATOR_MODE_NORMAL:
0458         *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
0459         break;
0460     case REGULATOR_MODE_IDLE:
0461         *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
0462         break;
0463     case REGULATOR_MODE_STANDBY:
0464         *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
0465         break;
0466     default:
0467         return -EINVAL;
0468     }
0469 
0470     return 0;
0471 }
0472 
0473 static const struct linear_range wm8350_ldo_ranges[] = {
0474     REGULATOR_LINEAR_RANGE(900000, 0, 15, 50000),
0475     REGULATOR_LINEAR_RANGE(1800000, 16, 31, 100000),
0476 };
0477 
0478 static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
0479 {
0480     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0481     int sel, volt_reg, ldo = rdev_get_id(rdev);
0482     u16 val;
0483 
0484     dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, uV / 1000);
0485 
0486     switch (ldo) {
0487     case WM8350_LDO_1:
0488         volt_reg = WM8350_LDO1_LOW_POWER;
0489         break;
0490     case WM8350_LDO_2:
0491         volt_reg = WM8350_LDO2_LOW_POWER;
0492         break;
0493     case WM8350_LDO_3:
0494         volt_reg = WM8350_LDO3_LOW_POWER;
0495         break;
0496     case WM8350_LDO_4:
0497         volt_reg = WM8350_LDO4_LOW_POWER;
0498         break;
0499     default:
0500         return -EINVAL;
0501     }
0502 
0503     sel = regulator_map_voltage_linear_range(rdev, uV, uV);
0504     if (sel < 0)
0505         return sel;
0506 
0507     /* all LDOs have same mV bits */
0508     val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
0509     wm8350_reg_write(wm8350, volt_reg, val | sel);
0510     return 0;
0511 }
0512 
0513 static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
0514 {
0515     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0516     int volt_reg, ldo = rdev_get_id(rdev);
0517     u16 val;
0518 
0519     switch (ldo) {
0520     case WM8350_LDO_1:
0521         volt_reg = WM8350_LDO1_LOW_POWER;
0522         break;
0523     case WM8350_LDO_2:
0524         volt_reg = WM8350_LDO2_LOW_POWER;
0525         break;
0526     case WM8350_LDO_3:
0527         volt_reg = WM8350_LDO3_LOW_POWER;
0528         break;
0529     case WM8350_LDO_4:
0530         volt_reg = WM8350_LDO4_LOW_POWER;
0531         break;
0532     default:
0533         return -EINVAL;
0534     }
0535 
0536     /* all LDOs have same mV bits */
0537     val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
0538     wm8350_reg_write(wm8350, volt_reg, val);
0539     return 0;
0540 }
0541 
0542 static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
0543 {
0544     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0545     int volt_reg, ldo = rdev_get_id(rdev);
0546     u16 val;
0547 
0548     switch (ldo) {
0549     case WM8350_LDO_1:
0550         volt_reg = WM8350_LDO1_LOW_POWER;
0551         break;
0552     case WM8350_LDO_2:
0553         volt_reg = WM8350_LDO2_LOW_POWER;
0554         break;
0555     case WM8350_LDO_3:
0556         volt_reg = WM8350_LDO3_LOW_POWER;
0557         break;
0558     case WM8350_LDO_4:
0559         volt_reg = WM8350_LDO4_LOW_POWER;
0560         break;
0561     default:
0562         return -EINVAL;
0563     }
0564 
0565     /* all LDOs have same mV bits */
0566     val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
0567     wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
0568     return 0;
0569 }
0570 
0571 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
0572              u16 stop, u16 fault)
0573 {
0574     int slot_reg;
0575     u16 val;
0576 
0577     dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
0578         __func__, dcdc, start, stop);
0579 
0580     /* slot valid ? */
0581     if (start > 15 || stop > 15)
0582         return -EINVAL;
0583 
0584     switch (dcdc) {
0585     case WM8350_DCDC_1:
0586         slot_reg = WM8350_DCDC1_TIMEOUTS;
0587         break;
0588     case WM8350_DCDC_2:
0589         slot_reg = WM8350_DCDC2_TIMEOUTS;
0590         break;
0591     case WM8350_DCDC_3:
0592         slot_reg = WM8350_DCDC3_TIMEOUTS;
0593         break;
0594     case WM8350_DCDC_4:
0595         slot_reg = WM8350_DCDC4_TIMEOUTS;
0596         break;
0597     case WM8350_DCDC_5:
0598         slot_reg = WM8350_DCDC5_TIMEOUTS;
0599         break;
0600     case WM8350_DCDC_6:
0601         slot_reg = WM8350_DCDC6_TIMEOUTS;
0602         break;
0603     default:
0604         return -EINVAL;
0605     }
0606 
0607     val = wm8350_reg_read(wm8350, slot_reg) &
0608         ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
0609           WM8350_DC1_ERRACT_MASK);
0610     wm8350_reg_write(wm8350, slot_reg,
0611              val | (start << WM8350_DC1_ENSLOT_SHIFT) |
0612              (stop << WM8350_DC1_SDSLOT_SHIFT) |
0613              (fault << WM8350_DC1_ERRACT_SHIFT));
0614 
0615     return 0;
0616 }
0617 EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
0618 
0619 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
0620 {
0621     int slot_reg;
0622     u16 val;
0623 
0624     dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
0625         __func__, ldo, start, stop);
0626 
0627     /* slot valid ? */
0628     if (start > 15 || stop > 15)
0629         return -EINVAL;
0630 
0631     switch (ldo) {
0632     case WM8350_LDO_1:
0633         slot_reg = WM8350_LDO1_TIMEOUTS;
0634         break;
0635     case WM8350_LDO_2:
0636         slot_reg = WM8350_LDO2_TIMEOUTS;
0637         break;
0638     case WM8350_LDO_3:
0639         slot_reg = WM8350_LDO3_TIMEOUTS;
0640         break;
0641     case WM8350_LDO_4:
0642         slot_reg = WM8350_LDO4_TIMEOUTS;
0643         break;
0644     default:
0645         return -EINVAL;
0646     }
0647 
0648     val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
0649     wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
0650     return 0;
0651 }
0652 EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
0653 
0654 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
0655                u16 ilim, u16 ramp, u16 feedback)
0656 {
0657     u16 val;
0658 
0659     dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
0660         mode ? "normal" : "boost", ilim ? "low" : "normal");
0661 
0662     switch (dcdc) {
0663     case WM8350_DCDC_2:
0664         val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
0665             & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
0666             WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
0667         wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
0668                  (mode << WM8350_DC2_MODE_SHIFT) |
0669                  (ilim << WM8350_DC2_ILIM_SHIFT) |
0670                  (ramp << WM8350_DC2_RMP_SHIFT) |
0671                  (feedback << WM8350_DC2_FBSRC_SHIFT));
0672         break;
0673     case WM8350_DCDC_5:
0674         val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
0675             & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
0676             WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
0677         wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
0678                  (mode << WM8350_DC5_MODE_SHIFT) |
0679                  (ilim << WM8350_DC5_ILIM_SHIFT) |
0680                  (ramp << WM8350_DC5_RMP_SHIFT) |
0681                  (feedback << WM8350_DC5_FBSRC_SHIFT));
0682         break;
0683     default:
0684         return -EINVAL;
0685     }
0686 
0687     return 0;
0688 }
0689 EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
0690 
0691 static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
0692 {
0693     int reg = 0, ret;
0694 
0695     switch (dcdc) {
0696     case WM8350_DCDC_1:
0697         reg = WM8350_DCDC1_FORCE_PWM;
0698         break;
0699     case WM8350_DCDC_3:
0700         reg = WM8350_DCDC3_FORCE_PWM;
0701         break;
0702     case WM8350_DCDC_4:
0703         reg = WM8350_DCDC4_FORCE_PWM;
0704         break;
0705     case WM8350_DCDC_6:
0706         reg = WM8350_DCDC6_FORCE_PWM;
0707         break;
0708     default:
0709         return -EINVAL;
0710     }
0711 
0712     if (enable)
0713         ret = wm8350_set_bits(wm8350, reg,
0714             WM8350_DCDC1_FORCE_PWM_ENA);
0715     else
0716         ret = wm8350_clear_bits(wm8350, reg,
0717             WM8350_DCDC1_FORCE_PWM_ENA);
0718     return ret;
0719 }
0720 
0721 static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
0722 {
0723     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0724     int dcdc = rdev_get_id(rdev);
0725     u16 val;
0726 
0727     if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
0728         return -EINVAL;
0729 
0730     if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
0731         return -EINVAL;
0732 
0733     val = 1 << (dcdc - WM8350_DCDC_1);
0734 
0735     switch (mode) {
0736     case REGULATOR_MODE_FAST:
0737         /* force continuous mode */
0738         wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
0739         wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
0740         force_continuous_enable(wm8350, dcdc, 1);
0741         break;
0742     case REGULATOR_MODE_NORMAL:
0743         /* active / pulse skipping */
0744         wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
0745         wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
0746         force_continuous_enable(wm8350, dcdc, 0);
0747         break;
0748     case REGULATOR_MODE_IDLE:
0749         /* standby mode */
0750         force_continuous_enable(wm8350, dcdc, 0);
0751         wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
0752         wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
0753         break;
0754     case REGULATOR_MODE_STANDBY:
0755         /* LDO mode */
0756         force_continuous_enable(wm8350, dcdc, 0);
0757         wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
0758         break;
0759     }
0760 
0761     return 0;
0762 }
0763 
0764 static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
0765 {
0766     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
0767     int dcdc = rdev_get_id(rdev);
0768     u16 mask, sleep, active, force;
0769     int mode = REGULATOR_MODE_NORMAL;
0770     int reg;
0771 
0772     switch (dcdc) {
0773     case WM8350_DCDC_1:
0774         reg = WM8350_DCDC1_FORCE_PWM;
0775         break;
0776     case WM8350_DCDC_3:
0777         reg = WM8350_DCDC3_FORCE_PWM;
0778         break;
0779     case WM8350_DCDC_4:
0780         reg = WM8350_DCDC4_FORCE_PWM;
0781         break;
0782     case WM8350_DCDC_6:
0783         reg = WM8350_DCDC6_FORCE_PWM;
0784         break;
0785     default:
0786         return -EINVAL;
0787     }
0788 
0789     mask = 1 << (dcdc - WM8350_DCDC_1);
0790     active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
0791     force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
0792     sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
0793 
0794     dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
0795         mask, active, sleep, force);
0796 
0797     if (active && !sleep) {
0798         if (force)
0799             mode = REGULATOR_MODE_FAST;
0800         else
0801             mode = REGULATOR_MODE_NORMAL;
0802     } else if (!active && !sleep)
0803         mode = REGULATOR_MODE_IDLE;
0804     else if (sleep)
0805         mode = REGULATOR_MODE_STANDBY;
0806 
0807     return mode;
0808 }
0809 
0810 static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
0811 {
0812     return REGULATOR_MODE_NORMAL;
0813 }
0814 
0815 struct wm8350_dcdc_efficiency {
0816     int uA_load_min;
0817     int uA_load_max;
0818     unsigned int mode;
0819 };
0820 
0821 static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
0822     {0, 10000, REGULATOR_MODE_STANDBY},       /* 0 - 10mA - LDO */
0823     {10000, 100000, REGULATOR_MODE_IDLE},     /* 10mA - 100mA - Standby */
0824     {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
0825     {-1, -1, REGULATOR_MODE_NORMAL},
0826 };
0827 
0828 static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
0829     {0, 10000, REGULATOR_MODE_STANDBY},      /* 0 - 10mA - LDO */
0830     {10000, 100000, REGULATOR_MODE_IDLE},    /* 10mA - 100mA - Standby */
0831     {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
0832     {-1, -1, REGULATOR_MODE_NORMAL},
0833 };
0834 
0835 static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
0836 {
0837     int i = 0;
0838 
0839     while (eff[i].uA_load_min != -1) {
0840         if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
0841             return eff[i].mode;
0842         i++;
0843     }
0844     return REGULATOR_MODE_NORMAL;
0845 }
0846 
0847 /* Query the regulator for it's most efficient mode @ uV,uA
0848  * WM8350 regulator efficiency is pretty similar over
0849  * different input and output uV.
0850  */
0851 static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
0852                          int input_uV, int output_uV,
0853                          int output_uA)
0854 {
0855     int dcdc = rdev_get_id(rdev), mode;
0856 
0857     switch (dcdc) {
0858     case WM8350_DCDC_1:
0859     case WM8350_DCDC_6:
0860         mode = get_mode(output_uA, dcdc1_6_efficiency);
0861         break;
0862     case WM8350_DCDC_3:
0863     case WM8350_DCDC_4:
0864         mode = get_mode(output_uA, dcdc3_4_efficiency);
0865         break;
0866     default:
0867         mode = REGULATOR_MODE_NORMAL;
0868         break;
0869     }
0870     return mode;
0871 }
0872 
0873 static const struct regulator_ops wm8350_dcdc_ops = {
0874     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0875     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0876     .list_voltage = regulator_list_voltage_linear,
0877     .map_voltage = regulator_map_voltage_linear,
0878     .enable = regulator_enable_regmap,
0879     .disable = regulator_disable_regmap,
0880     .is_enabled = regulator_is_enabled_regmap,
0881     .get_mode = wm8350_dcdc_get_mode,
0882     .set_mode = wm8350_dcdc_set_mode,
0883     .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
0884     .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
0885     .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
0886     .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
0887     .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
0888 };
0889 
0890 static const struct regulator_ops wm8350_dcdc2_5_ops = {
0891     .enable = regulator_enable_regmap,
0892     .disable = regulator_disable_regmap,
0893     .is_enabled = regulator_is_enabled_regmap,
0894     .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
0895     .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
0896 };
0897 
0898 static const struct regulator_ops wm8350_ldo_ops = {
0899     .map_voltage = regulator_map_voltage_linear_range,
0900     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0901     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0902     .list_voltage = regulator_list_voltage_linear_range,
0903     .enable = regulator_enable_regmap,
0904     .disable = regulator_disable_regmap,
0905     .is_enabled = regulator_is_enabled_regmap,
0906     .get_mode = wm8350_ldo_get_mode,
0907     .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
0908     .set_suspend_enable = wm8350_ldo_set_suspend_enable,
0909     .set_suspend_disable = wm8350_ldo_set_suspend_disable,
0910 };
0911 
0912 static const struct regulator_ops wm8350_isink_ops = {
0913     .set_current_limit = regulator_set_current_limit_regmap,
0914     .get_current_limit = regulator_get_current_limit_regmap,
0915     .enable = wm8350_isink_enable,
0916     .disable = wm8350_isink_disable,
0917     .is_enabled = wm8350_isink_is_enabled,
0918     .enable_time = wm8350_isink_enable_time,
0919 };
0920 
0921 static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
0922     {
0923         .name = "DCDC1",
0924         .id = WM8350_DCDC_1,
0925         .ops = &wm8350_dcdc_ops,
0926         .irq = WM8350_IRQ_UV_DC1,
0927         .type = REGULATOR_VOLTAGE,
0928         .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
0929         .min_uV = 850000,
0930         .uV_step = 25000,
0931         .vsel_reg = WM8350_DCDC1_CONTROL,
0932         .vsel_mask = WM8350_DC1_VSEL_MASK,
0933         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0934         .enable_mask = WM8350_DC1_ENA,
0935         .owner = THIS_MODULE,
0936     },
0937     {
0938         .name = "DCDC2",
0939         .id = WM8350_DCDC_2,
0940         .ops = &wm8350_dcdc2_5_ops,
0941         .irq = WM8350_IRQ_UV_DC2,
0942         .type = REGULATOR_VOLTAGE,
0943         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0944         .enable_mask = WM8350_DC2_ENA,
0945         .owner = THIS_MODULE,
0946     },
0947     {
0948         .name = "DCDC3",
0949         .id = WM8350_DCDC_3,
0950         .ops = &wm8350_dcdc_ops,
0951         .irq = WM8350_IRQ_UV_DC3,
0952         .type = REGULATOR_VOLTAGE,
0953         .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
0954         .min_uV = 850000,
0955         .uV_step = 25000,
0956         .vsel_reg = WM8350_DCDC3_CONTROL,
0957         .vsel_mask = WM8350_DC3_VSEL_MASK,
0958         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0959         .enable_mask = WM8350_DC3_ENA,
0960         .owner = THIS_MODULE,
0961     },
0962     {
0963         .name = "DCDC4",
0964         .id = WM8350_DCDC_4,
0965         .ops = &wm8350_dcdc_ops,
0966         .irq = WM8350_IRQ_UV_DC4,
0967         .type = REGULATOR_VOLTAGE,
0968         .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
0969         .min_uV = 850000,
0970         .uV_step = 25000,
0971         .vsel_reg = WM8350_DCDC4_CONTROL,
0972         .vsel_mask = WM8350_DC4_VSEL_MASK,
0973         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0974         .enable_mask = WM8350_DC4_ENA,
0975         .owner = THIS_MODULE,
0976     },
0977     {
0978         .name = "DCDC5",
0979         .id = WM8350_DCDC_5,
0980         .ops = &wm8350_dcdc2_5_ops,
0981         .irq = WM8350_IRQ_UV_DC5,
0982         .type = REGULATOR_VOLTAGE,
0983         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0984         .enable_mask = WM8350_DC5_ENA,
0985         .owner = THIS_MODULE,
0986      },
0987     {
0988         .name = "DCDC6",
0989         .id = WM8350_DCDC_6,
0990         .ops = &wm8350_dcdc_ops,
0991         .irq = WM8350_IRQ_UV_DC6,
0992         .type = REGULATOR_VOLTAGE,
0993         .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
0994         .min_uV = 850000,
0995         .uV_step = 25000,
0996         .vsel_reg = WM8350_DCDC6_CONTROL,
0997         .vsel_mask = WM8350_DC6_VSEL_MASK,
0998         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
0999         .enable_mask = WM8350_DC6_ENA,
1000         .owner = THIS_MODULE,
1001     },
1002     {
1003         .name = "LDO1",
1004         .id = WM8350_LDO_1,
1005         .ops = &wm8350_ldo_ops,
1006         .irq = WM8350_IRQ_UV_LDO1,
1007         .type = REGULATOR_VOLTAGE,
1008         .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1009         .linear_ranges = wm8350_ldo_ranges,
1010         .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1011         .vsel_reg = WM8350_LDO1_CONTROL,
1012         .vsel_mask = WM8350_LDO1_VSEL_MASK,
1013         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1014         .enable_mask = WM8350_LDO1_ENA,
1015         .owner = THIS_MODULE,
1016     },
1017     {
1018         .name = "LDO2",
1019         .id = WM8350_LDO_2,
1020         .ops = &wm8350_ldo_ops,
1021         .irq = WM8350_IRQ_UV_LDO2,
1022         .type = REGULATOR_VOLTAGE,
1023         .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1024         .linear_ranges = wm8350_ldo_ranges,
1025         .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1026         .vsel_reg = WM8350_LDO2_CONTROL,
1027         .vsel_mask = WM8350_LDO2_VSEL_MASK,
1028         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1029         .enable_mask = WM8350_LDO2_ENA,
1030         .owner = THIS_MODULE,
1031     },
1032     {
1033         .name = "LDO3",
1034         .id = WM8350_LDO_3,
1035         .ops = &wm8350_ldo_ops,
1036         .irq = WM8350_IRQ_UV_LDO3,
1037         .type = REGULATOR_VOLTAGE,
1038         .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1039         .linear_ranges = wm8350_ldo_ranges,
1040         .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1041         .vsel_reg = WM8350_LDO3_CONTROL,
1042         .vsel_mask = WM8350_LDO3_VSEL_MASK,
1043         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1044         .enable_mask = WM8350_LDO3_ENA,
1045         .owner = THIS_MODULE,
1046     },
1047     {
1048         .name = "LDO4",
1049         .id = WM8350_LDO_4,
1050         .ops = &wm8350_ldo_ops,
1051         .irq = WM8350_IRQ_UV_LDO4,
1052         .type = REGULATOR_VOLTAGE,
1053         .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1054         .linear_ranges = wm8350_ldo_ranges,
1055         .n_linear_ranges = ARRAY_SIZE(wm8350_ldo_ranges),
1056         .vsel_reg = WM8350_LDO4_CONTROL,
1057         .vsel_mask = WM8350_LDO4_VSEL_MASK,
1058         .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1059         .enable_mask = WM8350_LDO4_ENA,
1060         .owner = THIS_MODULE,
1061     },
1062     {
1063         .name = "ISINKA",
1064         .id = WM8350_ISINK_A,
1065         .ops = &wm8350_isink_ops,
1066         .irq = WM8350_IRQ_CS1,
1067         .type = REGULATOR_CURRENT,
1068         .owner = THIS_MODULE,
1069         .curr_table = isink_cur,
1070         .n_current_limits = ARRAY_SIZE(isink_cur),
1071         .csel_reg = WM8350_CURRENT_SINK_DRIVER_A,
1072         .csel_mask = WM8350_CS1_ISEL_MASK,
1073      },
1074     {
1075         .name = "ISINKB",
1076         .id = WM8350_ISINK_B,
1077         .ops = &wm8350_isink_ops,
1078         .irq = WM8350_IRQ_CS2,
1079         .type = REGULATOR_CURRENT,
1080         .owner = THIS_MODULE,
1081         .curr_table = isink_cur,
1082         .n_current_limits = ARRAY_SIZE(isink_cur),
1083         .csel_reg = WM8350_CURRENT_SINK_DRIVER_B,
1084         .csel_mask = WM8350_CS2_ISEL_MASK,
1085      },
1086 };
1087 
1088 static irqreturn_t pmic_uv_handler(int irq, void *data)
1089 {
1090     struct regulator_dev *rdev = (struct regulator_dev *)data;
1091 
1092     if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1093         regulator_notifier_call_chain(rdev,
1094                           REGULATOR_EVENT_REGULATION_OUT,
1095                           NULL);
1096     else
1097         regulator_notifier_call_chain(rdev,
1098                           REGULATOR_EVENT_UNDER_VOLTAGE,
1099                           NULL);
1100 
1101     return IRQ_HANDLED;
1102 }
1103 
1104 static int wm8350_regulator_probe(struct platform_device *pdev)
1105 {
1106     struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1107     struct regulator_config config = { };
1108     struct regulator_dev *rdev;
1109     int ret;
1110     u16 val;
1111 
1112     if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1113         return -ENODEV;
1114 
1115     /* do any regulator specific init */
1116     switch (pdev->id) {
1117     case WM8350_DCDC_1:
1118         val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1119         wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1120         break;
1121     case WM8350_DCDC_3:
1122         val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1123         wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1124         break;
1125     case WM8350_DCDC_4:
1126         val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1127         wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1128         break;
1129     case WM8350_DCDC_6:
1130         val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1131         wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1132         break;
1133     }
1134 
1135     config.dev = &pdev->dev;
1136     config.init_data = dev_get_platdata(&pdev->dev);
1137     config.driver_data = dev_get_drvdata(&pdev->dev);
1138     config.regmap = wm8350->regmap;
1139 
1140     /* register regulator */
1141     rdev = devm_regulator_register(&pdev->dev, &wm8350_reg[pdev->id],
1142                        &config);
1143     if (IS_ERR(rdev)) {
1144         dev_err(&pdev->dev, "failed to register %s\n",
1145             wm8350_reg[pdev->id].name);
1146         return PTR_ERR(rdev);
1147     }
1148 
1149     /* register regulator IRQ */
1150     ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1151                   pmic_uv_handler, 0, "UV", rdev);
1152     if (ret < 0) {
1153         dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1154             wm8350_reg[pdev->id].name);
1155         return ret;
1156     }
1157 
1158     return 0;
1159 }
1160 
1161 static int wm8350_regulator_remove(struct platform_device *pdev)
1162 {
1163     struct regulator_dev *rdev = platform_get_drvdata(pdev);
1164     struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1165 
1166     wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1167 
1168     return 0;
1169 }
1170 
1171 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1172                   struct regulator_init_data *initdata)
1173 {
1174     struct platform_device *pdev;
1175     int ret;
1176     if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1177         return -EINVAL;
1178 
1179     if (wm8350->pmic.pdev[reg])
1180         return -EBUSY;
1181 
1182     if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1183         reg > wm8350->pmic.max_dcdc)
1184         return -ENODEV;
1185     if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1186         reg > wm8350->pmic.max_isink)
1187         return -ENODEV;
1188 
1189     pdev = platform_device_alloc("wm8350-regulator", reg);
1190     if (!pdev)
1191         return -ENOMEM;
1192 
1193     wm8350->pmic.pdev[reg] = pdev;
1194 
1195     initdata->driver_data = wm8350;
1196 
1197     pdev->dev.platform_data = initdata;
1198     pdev->dev.parent = wm8350->dev;
1199     platform_set_drvdata(pdev, wm8350);
1200 
1201     ret = platform_device_add(pdev);
1202 
1203     if (ret != 0) {
1204         dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1205             reg, ret);
1206         platform_device_put(pdev);
1207         wm8350->pmic.pdev[reg] = NULL;
1208     }
1209 
1210     return ret;
1211 }
1212 EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1213 
1214 /**
1215  * wm8350_register_led - Register a WM8350 LED output
1216  *
1217  * @wm8350: The WM8350 device to configure.
1218  * @lednum: LED device index to create.
1219  * @dcdc: The DCDC to use for the LED.
1220  * @isink: The ISINK to use for the LED.
1221  * @pdata: Configuration for the LED.
1222  *
1223  * The WM8350 supports the use of an ISINK together with a DCDC to
1224  * provide a power-efficient LED driver.  This function registers the
1225  * regulators and instantiates the platform device for a LED.  The
1226  * operating modes for the LED regulators must be configured using
1227  * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1228  * wm8350_dcdc_set_slot() prior to calling this function.
1229  */
1230 int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1231             struct wm8350_led_platform_data *pdata)
1232 {
1233     struct wm8350_led *led;
1234     struct platform_device *pdev;
1235     int ret;
1236 
1237     if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1238         dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1239         return -ENODEV;
1240     }
1241 
1242     led = &wm8350->pmic.led[lednum];
1243 
1244     if (led->pdev) {
1245         dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1246         return -EINVAL;
1247     }
1248 
1249     pdev = platform_device_alloc("wm8350-led", lednum);
1250     if (pdev == NULL) {
1251         dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1252         return -ENOMEM;
1253     }
1254 
1255     led->isink_consumer.dev_name = dev_name(&pdev->dev);
1256     led->isink_consumer.supply = "led_isink";
1257     led->isink_init.num_consumer_supplies = 1;
1258     led->isink_init.consumer_supplies = &led->isink_consumer;
1259     led->isink_init.constraints.min_uA = 0;
1260     led->isink_init.constraints.max_uA = pdata->max_uA;
1261     led->isink_init.constraints.valid_ops_mask
1262         = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1263     led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1264     ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1265     if (ret != 0) {
1266         platform_device_put(pdev);
1267         return ret;
1268     }
1269 
1270     led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1271     led->dcdc_consumer.supply = "led_vcc";
1272     led->dcdc_init.num_consumer_supplies = 1;
1273     led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1274     led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1275     led->dcdc_init.constraints.valid_ops_mask =  REGULATOR_CHANGE_STATUS;
1276     ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1277     if (ret != 0) {
1278         platform_device_put(pdev);
1279         return ret;
1280     }
1281 
1282     switch (isink) {
1283     case WM8350_ISINK_A:
1284         wm8350->pmic.isink_A_dcdc = dcdc;
1285         break;
1286     case WM8350_ISINK_B:
1287         wm8350->pmic.isink_B_dcdc = dcdc;
1288         break;
1289     }
1290 
1291     pdev->dev.platform_data = pdata;
1292     pdev->dev.parent = wm8350->dev;
1293     ret = platform_device_add(pdev);
1294     if (ret != 0) {
1295         dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1296             lednum, ret);
1297         platform_device_put(pdev);
1298         return ret;
1299     }
1300 
1301     led->pdev = pdev;
1302 
1303     return 0;
1304 }
1305 EXPORT_SYMBOL_GPL(wm8350_register_led);
1306 
1307 static struct platform_driver wm8350_regulator_driver = {
1308     .probe = wm8350_regulator_probe,
1309     .remove = wm8350_regulator_remove,
1310     .driver     = {
1311         .name   = "wm8350-regulator",
1312     },
1313 };
1314 
1315 static int __init wm8350_regulator_init(void)
1316 {
1317     return platform_driver_register(&wm8350_regulator_driver);
1318 }
1319 subsys_initcall(wm8350_regulator_init);
1320 
1321 static void __exit wm8350_regulator_exit(void)
1322 {
1323     platform_driver_unregister(&wm8350_regulator_driver);
1324 }
1325 module_exit(wm8350_regulator_exit);
1326 
1327 /* Module information */
1328 MODULE_AUTHOR("Liam Girdwood");
1329 MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1330 MODULE_LICENSE("GPL");
1331 MODULE_ALIAS("platform:wm8350-regulator");
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