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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) STMicroelectronics 2018
0003 // Author: Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
0004 
0005 #include <linux/interrupt.h>
0006 #include <linux/mfd/stpmic1.h>
0007 #include <linux/module.h>
0008 #include <linux/of_irq.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011 #include <linux/regulator/driver.h>
0012 #include <linux/regulator/machine.h>
0013 #include <linux/regulator/of_regulator.h>
0014 
0015 #include <dt-bindings/mfd/st,stpmic1.h>
0016 
0017 /**
0018  * struct stpmic1 regulator description: this structure is used as driver data
0019  * @desc: regulator framework description
0020  * @mask_reset_reg: mask reset register address
0021  * @mask_reset_mask: mask rank and mask reset register mask
0022  * @icc_reg: icc register address
0023  * @icc_mask: icc register mask
0024  */
0025 struct stpmic1_regulator_cfg {
0026     struct regulator_desc desc;
0027     u8 mask_reset_reg;
0028     u8 mask_reset_mask;
0029     u8 icc_reg;
0030     u8 icc_mask;
0031 };
0032 
0033 static int stpmic1_set_mode(struct regulator_dev *rdev, unsigned int mode);
0034 static unsigned int stpmic1_get_mode(struct regulator_dev *rdev);
0035 static int stpmic1_set_icc(struct regulator_dev *rdev, int lim, int severity,
0036                bool enable);
0037 static unsigned int stpmic1_map_mode(unsigned int mode);
0038 
0039 enum {
0040     STPMIC1_BUCK1 = 0,
0041     STPMIC1_BUCK2 = 1,
0042     STPMIC1_BUCK3 = 2,
0043     STPMIC1_BUCK4 = 3,
0044     STPMIC1_LDO1 = 4,
0045     STPMIC1_LDO2 = 5,
0046     STPMIC1_LDO3 = 6,
0047     STPMIC1_LDO4 = 7,
0048     STPMIC1_LDO5 = 8,
0049     STPMIC1_LDO6 = 9,
0050     STPMIC1_VREF_DDR = 10,
0051     STPMIC1_BOOST = 11,
0052     STPMIC1_VBUS_OTG = 12,
0053     STPMIC1_SW_OUT = 13,
0054 };
0055 
0056 /* Enable time worst case is 5000mV/(2250uV/uS) */
0057 #define PMIC_ENABLE_TIME_US 2200
0058 /* Ramp delay worst case is (2250uV/uS) */
0059 #define PMIC_RAMP_DELAY 2200
0060 
0061 static const struct linear_range buck1_ranges[] = {
0062     REGULATOR_LINEAR_RANGE(725000, 0, 4, 0),
0063     REGULATOR_LINEAR_RANGE(725000, 5, 36, 25000),
0064     REGULATOR_LINEAR_RANGE(1500000, 37, 63, 0),
0065 };
0066 
0067 static const struct linear_range buck2_ranges[] = {
0068     REGULATOR_LINEAR_RANGE(1000000, 0, 17, 0),
0069     REGULATOR_LINEAR_RANGE(1050000, 18, 19, 0),
0070     REGULATOR_LINEAR_RANGE(1100000, 20, 21, 0),
0071     REGULATOR_LINEAR_RANGE(1150000, 22, 23, 0),
0072     REGULATOR_LINEAR_RANGE(1200000, 24, 25, 0),
0073     REGULATOR_LINEAR_RANGE(1250000, 26, 27, 0),
0074     REGULATOR_LINEAR_RANGE(1300000, 28, 29, 0),
0075     REGULATOR_LINEAR_RANGE(1350000, 30, 31, 0),
0076     REGULATOR_LINEAR_RANGE(1400000, 32, 33, 0),
0077     REGULATOR_LINEAR_RANGE(1450000, 34, 35, 0),
0078     REGULATOR_LINEAR_RANGE(1500000, 36, 63, 0),
0079 };
0080 
0081 static const struct linear_range buck3_ranges[] = {
0082     REGULATOR_LINEAR_RANGE(1000000, 0, 19, 0),
0083     REGULATOR_LINEAR_RANGE(1100000, 20, 23, 0),
0084     REGULATOR_LINEAR_RANGE(1200000, 24, 27, 0),
0085     REGULATOR_LINEAR_RANGE(1300000, 28, 31, 0),
0086     REGULATOR_LINEAR_RANGE(1400000, 32, 35, 0),
0087     REGULATOR_LINEAR_RANGE(1500000, 36, 55, 100000),
0088     REGULATOR_LINEAR_RANGE(3400000, 56, 63, 0),
0089 };
0090 
0091 static const struct linear_range buck4_ranges[] = {
0092     REGULATOR_LINEAR_RANGE(600000, 0, 27, 25000),
0093     REGULATOR_LINEAR_RANGE(1300000, 28, 29, 0),
0094     REGULATOR_LINEAR_RANGE(1350000, 30, 31, 0),
0095     REGULATOR_LINEAR_RANGE(1400000, 32, 33, 0),
0096     REGULATOR_LINEAR_RANGE(1450000, 34, 35, 0),
0097     REGULATOR_LINEAR_RANGE(1500000, 36, 60, 100000),
0098     REGULATOR_LINEAR_RANGE(3900000, 61, 63, 0),
0099 };
0100 
0101 static const struct linear_range ldo1_ranges[] = {
0102     REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
0103     REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
0104     REGULATOR_LINEAR_RANGE(3300000, 25, 31, 0),
0105 };
0106 
0107 static const struct linear_range ldo2_ranges[] = {
0108     REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
0109     REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
0110     REGULATOR_LINEAR_RANGE(3300000, 25, 30, 0),
0111 };
0112 
0113 static const struct linear_range ldo3_ranges[] = {
0114     REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
0115     REGULATOR_LINEAR_RANGE(1700000, 8, 24, 100000),
0116     REGULATOR_LINEAR_RANGE(3300000, 25, 30, 0),
0117     /* with index 31 LDO3 is in DDR mode */
0118     REGULATOR_LINEAR_RANGE(500000, 31, 31, 0),
0119 };
0120 
0121 static const struct linear_range ldo5_ranges[] = {
0122     REGULATOR_LINEAR_RANGE(1700000, 0, 7, 0),
0123     REGULATOR_LINEAR_RANGE(1700000, 8, 30, 100000),
0124     REGULATOR_LINEAR_RANGE(3900000, 31, 31, 0),
0125 };
0126 
0127 static const struct linear_range ldo6_ranges[] = {
0128     REGULATOR_LINEAR_RANGE(900000, 0, 24, 100000),
0129     REGULATOR_LINEAR_RANGE(3300000, 25, 31, 0),
0130 };
0131 
0132 static const struct regulator_ops stpmic1_ldo_ops = {
0133     .list_voltage = regulator_list_voltage_linear_range,
0134     .map_voltage = regulator_map_voltage_linear_range,
0135     .is_enabled = regulator_is_enabled_regmap,
0136     .enable = regulator_enable_regmap,
0137     .disable = regulator_disable_regmap,
0138     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0139     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0140     .set_over_current_protection = stpmic1_set_icc,
0141 };
0142 
0143 static const struct regulator_ops stpmic1_ldo3_ops = {
0144     .list_voltage = regulator_list_voltage_linear_range,
0145     .map_voltage = regulator_map_voltage_iterate,
0146     .is_enabled = regulator_is_enabled_regmap,
0147     .enable = regulator_enable_regmap,
0148     .disable = regulator_disable_regmap,
0149     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0150     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0151     .get_bypass = regulator_get_bypass_regmap,
0152     .set_bypass = regulator_set_bypass_regmap,
0153     .set_over_current_protection = stpmic1_set_icc,
0154 };
0155 
0156 static const struct regulator_ops stpmic1_ldo4_fixed_regul_ops = {
0157     .is_enabled = regulator_is_enabled_regmap,
0158     .enable = regulator_enable_regmap,
0159     .disable = regulator_disable_regmap,
0160     .set_over_current_protection = stpmic1_set_icc,
0161 };
0162 
0163 static const struct regulator_ops stpmic1_buck_ops = {
0164     .list_voltage = regulator_list_voltage_linear_range,
0165     .map_voltage = regulator_map_voltage_linear_range,
0166     .is_enabled = regulator_is_enabled_regmap,
0167     .enable = regulator_enable_regmap,
0168     .disable = regulator_disable_regmap,
0169     .get_voltage_sel = regulator_get_voltage_sel_regmap,
0170     .set_voltage_sel = regulator_set_voltage_sel_regmap,
0171     .set_pull_down = regulator_set_pull_down_regmap,
0172     .set_mode = stpmic1_set_mode,
0173     .get_mode = stpmic1_get_mode,
0174     .set_over_current_protection = stpmic1_set_icc,
0175 };
0176 
0177 static const struct regulator_ops stpmic1_vref_ddr_ops = {
0178     .is_enabled = regulator_is_enabled_regmap,
0179     .enable = regulator_enable_regmap,
0180     .disable = regulator_disable_regmap,
0181 };
0182 
0183 static const struct regulator_ops stpmic1_boost_regul_ops = {
0184     .is_enabled = regulator_is_enabled_regmap,
0185     .enable = regulator_enable_regmap,
0186     .disable = regulator_disable_regmap,
0187     .set_over_current_protection = stpmic1_set_icc,
0188 };
0189 
0190 static const struct regulator_ops stpmic1_switch_regul_ops = {
0191     .is_enabled = regulator_is_enabled_regmap,
0192     .enable = regulator_enable_regmap,
0193     .disable = regulator_disable_regmap,
0194     .set_over_current_protection = stpmic1_set_icc,
0195     .set_active_discharge = regulator_set_active_discharge_regmap,
0196 };
0197 
0198 #define REG_LDO(ids, base) { \
0199     .name = #ids, \
0200     .id = STPMIC1_##ids, \
0201     .n_voltages = 32, \
0202     .ops = &stpmic1_ldo_ops, \
0203     .linear_ranges = base ## _ranges, \
0204     .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \
0205     .type = REGULATOR_VOLTAGE, \
0206     .owner = THIS_MODULE, \
0207     .vsel_reg = ids##_ACTIVE_CR, \
0208     .vsel_mask = LDO_VOLTAGE_MASK, \
0209     .enable_reg = ids##_ACTIVE_CR, \
0210     .enable_mask = LDO_ENABLE_MASK, \
0211     .enable_val = 1, \
0212     .disable_val = 0, \
0213     .enable_time = PMIC_ENABLE_TIME_US, \
0214     .ramp_delay = PMIC_RAMP_DELAY, \
0215     .supply_name = #base, \
0216 }
0217 
0218 #define REG_LDO3(ids, base) { \
0219     .name = #ids, \
0220     .id = STPMIC1_##ids, \
0221     .n_voltages = 32, \
0222     .ops = &stpmic1_ldo3_ops, \
0223     .linear_ranges = ldo3_ranges, \
0224     .n_linear_ranges = ARRAY_SIZE(ldo3_ranges), \
0225     .type = REGULATOR_VOLTAGE, \
0226     .owner = THIS_MODULE, \
0227     .vsel_reg = LDO3_ACTIVE_CR, \
0228     .vsel_mask = LDO_VOLTAGE_MASK, \
0229     .enable_reg = LDO3_ACTIVE_CR, \
0230     .enable_mask = LDO_ENABLE_MASK, \
0231     .enable_val = 1, \
0232     .disable_val = 0, \
0233     .enable_time = PMIC_ENABLE_TIME_US, \
0234     .ramp_delay = PMIC_RAMP_DELAY, \
0235     .bypass_reg = LDO3_ACTIVE_CR, \
0236     .bypass_mask = LDO_BYPASS_MASK, \
0237     .bypass_val_on = LDO_BYPASS_MASK, \
0238     .bypass_val_off = 0, \
0239     .supply_name = #base, \
0240 }
0241 
0242 #define REG_LDO4(ids, base) { \
0243     .name = #ids, \
0244     .id = STPMIC1_##ids, \
0245     .n_voltages = 1, \
0246     .ops = &stpmic1_ldo4_fixed_regul_ops, \
0247     .type = REGULATOR_VOLTAGE, \
0248     .owner = THIS_MODULE, \
0249     .min_uV = 3300000, \
0250     .fixed_uV = 3300000, \
0251     .enable_reg = LDO4_ACTIVE_CR, \
0252     .enable_mask = LDO_ENABLE_MASK, \
0253     .enable_val = 1, \
0254     .disable_val = 0, \
0255     .enable_time = PMIC_ENABLE_TIME_US, \
0256     .ramp_delay = PMIC_RAMP_DELAY, \
0257     .supply_name = #base, \
0258 }
0259 
0260 #define REG_BUCK(ids, base) { \
0261     .name = #ids, \
0262     .id = STPMIC1_##ids, \
0263     .ops = &stpmic1_buck_ops, \
0264     .n_voltages = 64, \
0265     .linear_ranges = base ## _ranges, \
0266     .n_linear_ranges = ARRAY_SIZE(base ## _ranges), \
0267     .type = REGULATOR_VOLTAGE, \
0268     .owner = THIS_MODULE, \
0269     .vsel_reg = ids##_ACTIVE_CR, \
0270     .vsel_mask = BUCK_VOLTAGE_MASK, \
0271     .enable_reg = ids##_ACTIVE_CR, \
0272     .enable_mask = BUCK_ENABLE_MASK, \
0273     .enable_val = 1, \
0274     .disable_val = 0, \
0275     .enable_time = PMIC_ENABLE_TIME_US, \
0276     .ramp_delay = PMIC_RAMP_DELAY, \
0277     .of_map_mode = stpmic1_map_mode, \
0278     .pull_down_reg = ids##_PULL_DOWN_REG, \
0279     .pull_down_mask = ids##_PULL_DOWN_MASK, \
0280     .supply_name = #base, \
0281 }
0282 
0283 #define REG_VREF_DDR(ids, base) { \
0284     .name = #ids, \
0285     .id = STPMIC1_##ids, \
0286     .n_voltages = 1, \
0287     .ops = &stpmic1_vref_ddr_ops, \
0288     .type = REGULATOR_VOLTAGE, \
0289     .owner = THIS_MODULE, \
0290     .min_uV = 500000, \
0291     .fixed_uV = 500000, \
0292     .enable_reg = VREF_DDR_ACTIVE_CR, \
0293     .enable_mask = BUCK_ENABLE_MASK, \
0294     .enable_val = 1, \
0295     .disable_val = 0, \
0296     .enable_time = PMIC_ENABLE_TIME_US, \
0297     .supply_name = #base, \
0298 }
0299 
0300 #define REG_BOOST(ids, base) { \
0301     .name = #ids, \
0302     .id = STPMIC1_##ids, \
0303     .n_voltages = 1, \
0304     .ops = &stpmic1_boost_regul_ops, \
0305     .type = REGULATOR_VOLTAGE, \
0306     .owner = THIS_MODULE, \
0307     .min_uV = 0, \
0308     .fixed_uV = 5000000, \
0309     .enable_reg = BST_SW_CR, \
0310     .enable_mask = BOOST_ENABLED, \
0311     .enable_val = BOOST_ENABLED, \
0312     .disable_val = 0, \
0313     .enable_time = PMIC_ENABLE_TIME_US, \
0314     .supply_name = #base, \
0315 }
0316 
0317 #define REG_VBUS_OTG(ids, base) { \
0318     .name = #ids, \
0319     .id = STPMIC1_##ids, \
0320     .n_voltages = 1, \
0321     .ops = &stpmic1_switch_regul_ops, \
0322     .type = REGULATOR_VOLTAGE, \
0323     .owner = THIS_MODULE, \
0324     .min_uV = 0, \
0325     .fixed_uV = 5000000, \
0326     .enable_reg = BST_SW_CR, \
0327     .enable_mask = USBSW_OTG_SWITCH_ENABLED, \
0328     .enable_val = USBSW_OTG_SWITCH_ENABLED, \
0329     .disable_val = 0, \
0330     .enable_time = PMIC_ENABLE_TIME_US, \
0331     .supply_name = #base, \
0332     .active_discharge_reg = BST_SW_CR, \
0333     .active_discharge_mask = VBUS_OTG_DISCHARGE, \
0334     .active_discharge_on = VBUS_OTG_DISCHARGE, \
0335 }
0336 
0337 #define REG_SW_OUT(ids, base) { \
0338     .name = #ids, \
0339     .id = STPMIC1_##ids, \
0340     .n_voltages = 1, \
0341     .ops = &stpmic1_switch_regul_ops, \
0342     .type = REGULATOR_VOLTAGE, \
0343     .owner = THIS_MODULE, \
0344     .min_uV = 0, \
0345     .fixed_uV = 5000000, \
0346     .enable_reg = BST_SW_CR, \
0347     .enable_mask = SWIN_SWOUT_ENABLED, \
0348     .enable_val = SWIN_SWOUT_ENABLED, \
0349     .disable_val = 0, \
0350     .enable_time = PMIC_ENABLE_TIME_US, \
0351     .supply_name = #base, \
0352     .active_discharge_reg = BST_SW_CR, \
0353     .active_discharge_mask = SW_OUT_DISCHARGE, \
0354     .active_discharge_on = SW_OUT_DISCHARGE, \
0355 }
0356 
0357 static const struct stpmic1_regulator_cfg stpmic1_regulator_cfgs[] = {
0358     [STPMIC1_BUCK1] = {
0359         .desc = REG_BUCK(BUCK1, buck1),
0360         .icc_reg = BUCKS_ICCTO_CR,
0361         .icc_mask = BIT(0),
0362         .mask_reset_reg = BUCKS_MASK_RESET_CR,
0363         .mask_reset_mask = BIT(0),
0364     },
0365     [STPMIC1_BUCK2] = {
0366         .desc = REG_BUCK(BUCK2, buck2),
0367         .icc_reg = BUCKS_ICCTO_CR,
0368         .icc_mask = BIT(1),
0369         .mask_reset_reg = BUCKS_MASK_RESET_CR,
0370         .mask_reset_mask = BIT(1),
0371     },
0372     [STPMIC1_BUCK3] = {
0373         .desc = REG_BUCK(BUCK3, buck3),
0374         .icc_reg = BUCKS_ICCTO_CR,
0375         .icc_mask = BIT(2),
0376         .mask_reset_reg = BUCKS_MASK_RESET_CR,
0377         .mask_reset_mask = BIT(2),
0378     },
0379     [STPMIC1_BUCK4] = {
0380         .desc = REG_BUCK(BUCK4, buck4),
0381         .icc_reg = BUCKS_ICCTO_CR,
0382         .icc_mask = BIT(3),
0383         .mask_reset_reg = BUCKS_MASK_RESET_CR,
0384         .mask_reset_mask = BIT(3),
0385     },
0386     [STPMIC1_LDO1] = {
0387         .desc = REG_LDO(LDO1, ldo1),
0388         .icc_reg = LDOS_ICCTO_CR,
0389         .icc_mask = BIT(0),
0390         .mask_reset_reg = LDOS_MASK_RESET_CR,
0391         .mask_reset_mask = BIT(0),
0392     },
0393     [STPMIC1_LDO2] = {
0394         .desc = REG_LDO(LDO2, ldo2),
0395         .icc_reg = LDOS_ICCTO_CR,
0396         .icc_mask = BIT(1),
0397         .mask_reset_reg = LDOS_MASK_RESET_CR,
0398         .mask_reset_mask = BIT(1),
0399     },
0400     [STPMIC1_LDO3] = {
0401         .desc = REG_LDO3(LDO3, ldo3),
0402         .icc_reg = LDOS_ICCTO_CR,
0403         .icc_mask = BIT(2),
0404         .mask_reset_reg = LDOS_MASK_RESET_CR,
0405         .mask_reset_mask = BIT(2),
0406     },
0407     [STPMIC1_LDO4] = {
0408         .desc = REG_LDO4(LDO4, ldo4),
0409         .icc_reg = LDOS_ICCTO_CR,
0410         .icc_mask = BIT(3),
0411         .mask_reset_reg = LDOS_MASK_RESET_CR,
0412         .mask_reset_mask = BIT(3),
0413     },
0414     [STPMIC1_LDO5] = {
0415         .desc = REG_LDO(LDO5, ldo5),
0416         .icc_reg = LDOS_ICCTO_CR,
0417         .icc_mask = BIT(4),
0418         .mask_reset_reg = LDOS_MASK_RESET_CR,
0419         .mask_reset_mask = BIT(4),
0420     },
0421     [STPMIC1_LDO6] = {
0422         .desc = REG_LDO(LDO6, ldo6),
0423         .icc_reg = LDOS_ICCTO_CR,
0424         .icc_mask = BIT(5),
0425         .mask_reset_reg = LDOS_MASK_RESET_CR,
0426         .mask_reset_mask = BIT(5),
0427     },
0428     [STPMIC1_VREF_DDR] = {
0429         .desc = REG_VREF_DDR(VREF_DDR, vref_ddr),
0430         .mask_reset_reg = LDOS_MASK_RESET_CR,
0431         .mask_reset_mask = BIT(6),
0432     },
0433     [STPMIC1_BOOST] = {
0434         .desc = REG_BOOST(BOOST, boost),
0435         .icc_reg = BUCKS_ICCTO_CR,
0436         .icc_mask = BIT(6),
0437     },
0438     [STPMIC1_VBUS_OTG] = {
0439         .desc = REG_VBUS_OTG(VBUS_OTG, pwr_sw1),
0440         .icc_reg = BUCKS_ICCTO_CR,
0441         .icc_mask = BIT(4),
0442     },
0443     [STPMIC1_SW_OUT] = {
0444         .desc = REG_SW_OUT(SW_OUT, pwr_sw2),
0445         .icc_reg = BUCKS_ICCTO_CR,
0446         .icc_mask = BIT(5),
0447     },
0448 };
0449 
0450 static unsigned int stpmic1_map_mode(unsigned int mode)
0451 {
0452     switch (mode) {
0453     case STPMIC1_BUCK_MODE_NORMAL:
0454         return REGULATOR_MODE_NORMAL;
0455     case STPMIC1_BUCK_MODE_LP:
0456         return REGULATOR_MODE_STANDBY;
0457     default:
0458         return REGULATOR_MODE_INVALID;
0459     }
0460 }
0461 
0462 static unsigned int stpmic1_get_mode(struct regulator_dev *rdev)
0463 {
0464     int value;
0465     struct regmap *regmap = rdev_get_regmap(rdev);
0466 
0467     regmap_read(regmap, rdev->desc->enable_reg, &value);
0468 
0469     if (value & STPMIC1_BUCK_MODE_LP)
0470         return REGULATOR_MODE_STANDBY;
0471 
0472     return REGULATOR_MODE_NORMAL;
0473 }
0474 
0475 static int stpmic1_set_mode(struct regulator_dev *rdev, unsigned int mode)
0476 {
0477     int value;
0478     struct regmap *regmap = rdev_get_regmap(rdev);
0479 
0480     switch (mode) {
0481     case REGULATOR_MODE_NORMAL:
0482         value = STPMIC1_BUCK_MODE_NORMAL;
0483         break;
0484     case REGULATOR_MODE_STANDBY:
0485         value = STPMIC1_BUCK_MODE_LP;
0486         break;
0487     default:
0488         return -EINVAL;
0489     }
0490 
0491     return regmap_update_bits(regmap, rdev->desc->enable_reg,
0492                   STPMIC1_BUCK_MODE_LP, value);
0493 }
0494 
0495 static int stpmic1_set_icc(struct regulator_dev *rdev, int lim, int severity,
0496                bool enable)
0497 {
0498     struct stpmic1_regulator_cfg *cfg = rdev_get_drvdata(rdev);
0499     struct regmap *regmap = rdev_get_regmap(rdev);
0500 
0501     /*
0502      * The code seems like one bit in a register controls whether OCP is
0503      * enabled. So we might be able to turn it off here is if that
0504      * was requested. I won't support this because I don't have the HW.
0505      * Feel free to try and implement if you have the HW and need kernel
0506      * to disable this.
0507      *
0508      * Also, I don't know if limit can be configured or if we support
0509      * error/warning instead of protect. So I just keep existing logic
0510      * and assume no.
0511      */
0512     if (lim || severity != REGULATOR_SEVERITY_PROT || !enable)
0513         return -EINVAL;
0514 
0515     /* enable switch off in case of over current */
0516     return regmap_update_bits(regmap, cfg->icc_reg, cfg->icc_mask,
0517                   cfg->icc_mask);
0518 }
0519 
0520 static irqreturn_t stpmic1_curlim_irq_handler(int irq, void *data)
0521 {
0522     struct regulator_dev *rdev = (struct regulator_dev *)data;
0523 
0524     /* Send an overcurrent notification */
0525     regulator_notifier_call_chain(rdev,
0526                       REGULATOR_EVENT_OVER_CURRENT,
0527                       NULL);
0528 
0529     return IRQ_HANDLED;
0530 }
0531 
0532 #define MATCH(_name, _id) \
0533     [STPMIC1_##_id] = { \
0534         .name = #_name, \
0535         .desc = &stpmic1_regulator_cfgs[STPMIC1_##_id].desc, \
0536     }
0537 
0538 static struct of_regulator_match stpmic1_matches[] = {
0539     MATCH(buck1, BUCK1),
0540     MATCH(buck2, BUCK2),
0541     MATCH(buck3, BUCK3),
0542     MATCH(buck4, BUCK4),
0543     MATCH(ldo1, LDO1),
0544     MATCH(ldo2, LDO2),
0545     MATCH(ldo3, LDO3),
0546     MATCH(ldo4, LDO4),
0547     MATCH(ldo5, LDO5),
0548     MATCH(ldo6, LDO6),
0549     MATCH(vref_ddr, VREF_DDR),
0550     MATCH(boost, BOOST),
0551     MATCH(pwr_sw1, VBUS_OTG),
0552     MATCH(pwr_sw2, SW_OUT),
0553 };
0554 
0555 static int stpmic1_regulator_register(struct platform_device *pdev, int id,
0556                       struct of_regulator_match *match,
0557                       const struct stpmic1_regulator_cfg *cfg)
0558 {
0559     struct stpmic1 *pmic_dev = dev_get_drvdata(pdev->dev.parent);
0560     struct regulator_dev *rdev;
0561     struct regulator_config config = {};
0562     int ret = 0;
0563     int irq;
0564 
0565     config.dev = &pdev->dev;
0566     config.init_data = match->init_data;
0567     config.of_node = match->of_node;
0568     config.regmap = pmic_dev->regmap;
0569     config.driver_data = (void *)cfg;
0570 
0571     rdev = devm_regulator_register(&pdev->dev, &cfg->desc, &config);
0572     if (IS_ERR(rdev)) {
0573         dev_err(&pdev->dev, "failed to register %s regulator\n",
0574             cfg->desc.name);
0575         return PTR_ERR(rdev);
0576     }
0577 
0578     /* set mask reset */
0579     if (of_get_property(config.of_node, "st,mask-reset", NULL) &&
0580         cfg->mask_reset_reg != 0) {
0581         ret = regmap_update_bits(pmic_dev->regmap,
0582                      cfg->mask_reset_reg,
0583                      cfg->mask_reset_mask,
0584                      cfg->mask_reset_mask);
0585         if (ret) {
0586             dev_err(&pdev->dev, "set mask reset failed\n");
0587             return ret;
0588         }
0589     }
0590 
0591     /* setup an irq handler for over-current detection */
0592     irq = of_irq_get(config.of_node, 0);
0593     if (irq > 0) {
0594         ret = devm_request_threaded_irq(&pdev->dev,
0595                         irq, NULL,
0596                         stpmic1_curlim_irq_handler,
0597                         IRQF_ONESHOT | IRQF_SHARED,
0598                         pdev->name, rdev);
0599         if (ret) {
0600             dev_err(&pdev->dev, "Request IRQ failed\n");
0601             return ret;
0602         }
0603     }
0604     return 0;
0605 }
0606 
0607 static int stpmic1_regulator_probe(struct platform_device *pdev)
0608 {
0609     int i, ret;
0610 
0611     ret = of_regulator_match(&pdev->dev, pdev->dev.of_node, stpmic1_matches,
0612                  ARRAY_SIZE(stpmic1_matches));
0613     if (ret < 0) {
0614         dev_err(&pdev->dev,
0615             "Error in PMIC regulator device tree node");
0616         return ret;
0617     }
0618 
0619     for (i = 0; i < ARRAY_SIZE(stpmic1_regulator_cfgs); i++) {
0620         ret = stpmic1_regulator_register(pdev, i, &stpmic1_matches[i],
0621                          &stpmic1_regulator_cfgs[i]);
0622         if (ret < 0)
0623             return ret;
0624     }
0625 
0626     dev_dbg(&pdev->dev, "stpmic1_regulator driver probed\n");
0627 
0628     return 0;
0629 }
0630 
0631 static const struct of_device_id of_pmic_regulator_match[] = {
0632     { .compatible = "st,stpmic1-regulators" },
0633     { },
0634 };
0635 
0636 MODULE_DEVICE_TABLE(of, of_pmic_regulator_match);
0637 
0638 static struct platform_driver stpmic1_regulator_driver = {
0639     .driver = {
0640         .name = "stpmic1-regulator",
0641         .of_match_table = of_match_ptr(of_pmic_regulator_match),
0642     },
0643     .probe = stpmic1_regulator_probe,
0644 };
0645 
0646 module_platform_driver(stpmic1_regulator_driver);
0647 
0648 MODULE_DESCRIPTION("STPMIC1 PMIC voltage regulator driver");
0649 MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
0650 MODULE_LICENSE("GPL v2");
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