drivers/regulator/stm32-pwr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) STMicroelectronics 2019
0003 // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
0004 //          Pascal Paillet <p.paillet@st.com>.
0005
0006 #include <linux/io.h>
0007 #include <linux/iopoll.h>
0008 #include <linux/module.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/regulator/driver.h>
0013 #include <linux/regulator/of_regulator.h>
0014
0015 /*
0016  * Registers description
0017  */
0018 #define REG_PWR_CR3 0x0C
0019
0020 #define USB_3_3_EN BIT(24)
0021 #define USB_3_3_RDY BIT(26)
0022 #define REG_1_8_EN BIT(28)
0023 #define REG_1_8_RDY BIT(29)
0024 #define REG_1_1_EN BIT(30)
0025 #define REG_1_1_RDY BIT(31)
0026
0027 /* list of supported regulators */
0028 enum {
0029     PWR_REG11,
0030     PWR_REG18,
0031     PWR_USB33,
0032     STM32PWR_REG_NUM_REGS
0033 };
0034
0035 static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
0036     [PWR_REG11] = REG_1_1_RDY,
0037     [PWR_REG18] = REG_1_8_RDY,
0038     [PWR_USB33] = USB_3_3_RDY,
0039 };
0040
0041 struct stm32_pwr_reg {
0042     void __iomem *base;
0043     u32 ready_mask;
0044 };
0045
0046 static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
0047 {
0048     struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
0049     u32 val;
0050
0051     val = readl_relaxed(priv->base + REG_PWR_CR3);
0052
0053     return (val & priv->ready_mask);
0054 }
0055
0056 static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
0057 {
0058     struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
0059     u32 val;
0060
0061     val = readl_relaxed(priv->base + REG_PWR_CR3);
0062
0063     return (val & rdev->desc->enable_mask);
0064 }
0065
0066 static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
0067 {
0068     struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
0069     int ret;
0070     u32 val;
0071
0072     val = readl_relaxed(priv->base + REG_PWR_CR3);
0073     val |= rdev->desc->enable_mask;
0074     writel_relaxed(val, priv->base + REG_PWR_CR3);
0075
0076     /* use an arbitrary timeout of 20ms */
0077     ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
0078                  100, 20 * 1000);
0079     if (ret)
0080         dev_err(&rdev->dev, "regulator enable timed out!\n");
0081
0082     return ret;
0083 }
0084
0085 static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
0086 {
0087     struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
0088     int ret;
0089     u32 val;
0090
0091     val = readl_relaxed(priv->base + REG_PWR_CR3);
0092     val &= ~rdev->desc->enable_mask;
0093     writel_relaxed(val, priv->base + REG_PWR_CR3);
0094
0095     /* use an arbitrary timeout of 20ms */
0096     ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
0097                  100, 20 * 1000);
0098     if (ret)
0099         dev_err(&rdev->dev, "regulator disable timed out!\n");
0100
0101     return ret;
0102 }
0103
0104 static const struct regulator_ops stm32_pwr_reg_ops = {
0105     .enable     = stm32_pwr_reg_enable,
0106     .disable    = stm32_pwr_reg_disable,
0107     .is_enabled = stm32_pwr_reg_is_enabled,
0108 };
0109
0110 #define PWR_REG(_id, _name, _volt, _en, _supply) \
0111     [_id] = { \
0112         .id = _id, \
0113         .name = _name, \
0114         .of_match = of_match_ptr(_name), \
0115         .n_voltages = 1, \
0116         .type = REGULATOR_VOLTAGE, \
0117         .fixed_uV = _volt, \
0118         .ops = &stm32_pwr_reg_ops, \
0119         .enable_mask = _en, \
0120         .owner = THIS_MODULE, \
0121         .supply_name = _supply, \
0122     } \
0123
0124 static const struct regulator_desc stm32_pwr_desc[] = {
0125     PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
0126     PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
0127     PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
0128 };
0129
0130 static int stm32_pwr_regulator_probe(struct platform_device *pdev)
0131 {
0132     struct device_node *np = pdev->dev.of_node;
0133     struct stm32_pwr_reg *priv;
0134     void __iomem *base;
0135     struct regulator_dev *rdev;
0136     struct regulator_config config = { };
0137     int i, ret = 0;
0138
0139     base = of_iomap(np, 0);
0140     if (!base) {
0141         dev_err(&pdev->dev, "Unable to map IO memory\n");
0142         return -ENOMEM;
0143     }
0144
0145     config.dev = &pdev->dev;
0146
0147     for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
0148         priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
0149                     GFP_KERNEL);
0150         if (!priv)
0151             return -ENOMEM;
0152         priv->base = base;
0153         priv->ready_mask = ready_mask_table[i];
0154         config.driver_data = priv;
0155
0156         rdev = devm_regulator_register(&pdev->dev,
0157                            &stm32_pwr_desc[i],
0158                            &config);
0159         if (IS_ERR(rdev)) {
0160             ret = PTR_ERR(rdev);
0161             dev_err(&pdev->dev,
0162                 "Failed to register regulator: %d\n", ret);
0163             break;
0164         }
0165     }
0166     return ret;
0167 }
0168
0169 static const struct of_device_id __maybe_unused stm32_pwr_of_match[] = {
0170     { .compatible = "st,stm32mp1,pwr-reg", },
0171     {},
0172 };
0173 MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
0174
0175 static struct platform_driver stm32_pwr_driver = {
0176     .probe = stm32_pwr_regulator_probe,
0177     .driver = {
0178         .name  = "stm32-pwr-regulator",
0179         .of_match_table = of_match_ptr(stm32_pwr_of_match),
0180     },
0181 };
0182 module_platform_driver(stm32_pwr_driver);
0183
0184 MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
0185 MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
0186 MODULE_LICENSE("GPL v2");