0001
0002
0003
0004
0005
0006
0007
0008 #include <linux/err.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/i2c.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/irq.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/driver.h>
0018 #include <linux/regulator/machine.h>
0019 #include <linux/regulator/of_regulator.h>
0020 #include "slg51000-regulator.h"
0021
0022 #define SLG51000_SCTL_EVT 7
0023 #define SLG51000_MAX_EVT_REGISTER 8
0024 #define SLG51000_LDOHP_LV_MIN 1200000
0025 #define SLG51000_LDOHP_HV_MIN 2400000
0026
0027 enum slg51000_regulators {
0028 SLG51000_REGULATOR_LDO1 = 0,
0029 SLG51000_REGULATOR_LDO2,
0030 SLG51000_REGULATOR_LDO3,
0031 SLG51000_REGULATOR_LDO4,
0032 SLG51000_REGULATOR_LDO5,
0033 SLG51000_REGULATOR_LDO6,
0034 SLG51000_REGULATOR_LDO7,
0035 SLG51000_MAX_REGULATORS,
0036 };
0037
0038 struct slg51000 {
0039 struct device *dev;
0040 struct regmap *regmap;
0041 struct regulator_desc *rdesc[SLG51000_MAX_REGULATORS];
0042 struct regulator_dev *rdev[SLG51000_MAX_REGULATORS];
0043 struct gpio_desc *cs_gpiod;
0044 int chip_irq;
0045 };
0046
0047 struct slg51000_evt_sta {
0048 unsigned int ereg;
0049 unsigned int sreg;
0050 };
0051
0052 static const struct slg51000_evt_sta es_reg[SLG51000_MAX_EVT_REGISTER] = {
0053 {SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS},
0054 {SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS},
0055 {SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS},
0056 {SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS},
0057 {SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS},
0058 {SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS},
0059 {SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS},
0060 {SLG51000_SYSCTL_EVENT, SLG51000_SYSCTL_STATUS},
0061 };
0062
0063 static const struct regmap_range slg51000_writeable_ranges[] = {
0064 regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A,
0065 SLG51000_SYSCTL_MATRIX_CONF_A),
0066 regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
0067 regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
0068 regmap_reg_range(SLG51000_LDO1_IRQ_MASK, SLG51000_LDO1_IRQ_MASK),
0069 regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
0070 regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
0071 regmap_reg_range(SLG51000_LDO2_IRQ_MASK, SLG51000_LDO2_IRQ_MASK),
0072 regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
0073 regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
0074 regmap_reg_range(SLG51000_LDO3_IRQ_MASK, SLG51000_LDO3_IRQ_MASK),
0075 regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
0076 regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
0077 regmap_reg_range(SLG51000_LDO4_IRQ_MASK, SLG51000_LDO4_IRQ_MASK),
0078 regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
0079 regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
0080 regmap_reg_range(SLG51000_LDO5_IRQ_MASK, SLG51000_LDO5_IRQ_MASK),
0081 regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
0082 regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
0083 regmap_reg_range(SLG51000_LDO6_IRQ_MASK, SLG51000_LDO6_IRQ_MASK),
0084 regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
0085 regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
0086 regmap_reg_range(SLG51000_LDO7_IRQ_MASK, SLG51000_LDO7_IRQ_MASK),
0087 regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
0088 };
0089
0090 static const struct regmap_range slg51000_readable_ranges[] = {
0091 regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0,
0092 SLG51000_SYSCTL_PATN_ID_B2),
0093 regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A,
0094 SLG51000_SYSCTL_SYS_CONF_A),
0095 regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D,
0096 SLG51000_SYSCTL_MATRIX_CONF_B),
0097 regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C,
0098 SLG51000_SYSCTL_UVLO_CONF_A),
0099 regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_IRQ_MASK),
0100 regmap_reg_range(SLG51000_IO_GPIO1_CONF, SLG51000_IO_GPIO_STATUS),
0101 regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0,
0102 SLG51000_LUTARRAY_LUT_VAL_11),
0103 regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0,
0104 SLG51000_MUXARRAY_INPUT_SEL_63),
0105 regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0,
0106 SLG51000_PWRSEQ_INPUT_SENSE_CONF_B),
0107 regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
0108 regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
0109 regmap_reg_range(SLG51000_LDO1_MISC1, SLG51000_LDO1_VSEL_ACTUAL),
0110 regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_IRQ_MASK),
0111 regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
0112 regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
0113 regmap_reg_range(SLG51000_LDO2_MISC1, SLG51000_LDO2_VSEL_ACTUAL),
0114 regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_IRQ_MASK),
0115 regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
0116 regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
0117 regmap_reg_range(SLG51000_LDO3_CONF1, SLG51000_LDO3_VSEL_ACTUAL),
0118 regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_IRQ_MASK),
0119 regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
0120 regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
0121 regmap_reg_range(SLG51000_LDO4_CONF1, SLG51000_LDO4_VSEL_ACTUAL),
0122 regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_IRQ_MASK),
0123 regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
0124 regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
0125 regmap_reg_range(SLG51000_LDO5_TRIM2, SLG51000_LDO5_TRIM2),
0126 regmap_reg_range(SLG51000_LDO5_CONF1, SLG51000_LDO5_VSEL_ACTUAL),
0127 regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_IRQ_MASK),
0128 regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
0129 regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
0130 regmap_reg_range(SLG51000_LDO6_TRIM2, SLG51000_LDO6_TRIM2),
0131 regmap_reg_range(SLG51000_LDO6_CONF1, SLG51000_LDO6_VSEL_ACTUAL),
0132 regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_IRQ_MASK),
0133 regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
0134 regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
0135 regmap_reg_range(SLG51000_LDO7_CONF1, SLG51000_LDO7_VSEL_ACTUAL),
0136 regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_IRQ_MASK),
0137 regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
0138 regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
0139 regmap_reg_range(SLG51000_OTP_LOCK_OTP_PROG, SLG51000_OTP_LOCK_CTRL),
0140 regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1,
0141 SLG51000_LOCK_GLOBAL_LOCK_CTRL1),
0142 };
0143
0144 static const struct regmap_range slg51000_volatile_ranges[] = {
0145 regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_STATUS),
0146 regmap_reg_range(SLG51000_IO_GPIO_STATUS, SLG51000_IO_GPIO_STATUS),
0147 regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS),
0148 regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS),
0149 regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS),
0150 regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS),
0151 regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS),
0152 regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS),
0153 regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS),
0154 regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
0155 };
0156
0157 static const struct regmap_access_table slg51000_writeable_table = {
0158 .yes_ranges = slg51000_writeable_ranges,
0159 .n_yes_ranges = ARRAY_SIZE(slg51000_writeable_ranges),
0160 };
0161
0162 static const struct regmap_access_table slg51000_readable_table = {
0163 .yes_ranges = slg51000_readable_ranges,
0164 .n_yes_ranges = ARRAY_SIZE(slg51000_readable_ranges),
0165 };
0166
0167 static const struct regmap_access_table slg51000_volatile_table = {
0168 .yes_ranges = slg51000_volatile_ranges,
0169 .n_yes_ranges = ARRAY_SIZE(slg51000_volatile_ranges),
0170 };
0171
0172 static const struct regmap_config slg51000_regmap_config = {
0173 .reg_bits = 16,
0174 .val_bits = 8,
0175 .max_register = 0x8000,
0176 .wr_table = &slg51000_writeable_table,
0177 .rd_table = &slg51000_readable_table,
0178 .volatile_table = &slg51000_volatile_table,
0179 };
0180
0181 static const struct regulator_ops slg51000_regl_ops = {
0182 .enable = regulator_enable_regmap,
0183 .disable = regulator_disable_regmap,
0184 .is_enabled = regulator_is_enabled_regmap,
0185 .list_voltage = regulator_list_voltage_linear,
0186 .map_voltage = regulator_map_voltage_linear,
0187 .get_voltage_sel = regulator_get_voltage_sel_regmap,
0188 .set_voltage_sel = regulator_set_voltage_sel_regmap,
0189 };
0190
0191 static const struct regulator_ops slg51000_switch_ops = {
0192 .enable = regulator_enable_regmap,
0193 .disable = regulator_disable_regmap,
0194 .is_enabled = regulator_is_enabled_regmap,
0195 };
0196
0197 static int slg51000_of_parse_cb(struct device_node *np,
0198 const struct regulator_desc *desc,
0199 struct regulator_config *config)
0200 {
0201 struct gpio_desc *ena_gpiod;
0202
0203 ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), "enable", 0,
0204 GPIOD_OUT_LOW |
0205 GPIOD_FLAGS_BIT_NONEXCLUSIVE,
0206 "gpio-en-ldo");
0207 if (!IS_ERR(ena_gpiod))
0208 config->ena_gpiod = ena_gpiod;
0209
0210 return 0;
0211 }
0212
0213 #define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
0214 [SLG51000_REGULATOR_##_id] = { \
0215 .name = #_name, \
0216 .supply_name = _s_name, \
0217 .id = SLG51000_REGULATOR_##_id, \
0218 .of_match = of_match_ptr(#_name), \
0219 .of_parse_cb = slg51000_of_parse_cb, \
0220 .ops = &slg51000_regl_ops, \
0221 .regulators_node = of_match_ptr("regulators"), \
0222 .n_voltages = 256, \
0223 .min_uV = _min, \
0224 .uV_step = _step, \
0225 .linear_min_sel = 0, \
0226 .vsel_mask = SLG51000_VSEL_MASK, \
0227 .vsel_reg = SLG51000_##_id##_VSEL, \
0228 .enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A, \
0229 .enable_mask = BIT(SLG51000_REGULATOR_##_id), \
0230 .type = REGULATOR_VOLTAGE, \
0231 .owner = THIS_MODULE, \
0232 }
0233
0234 static struct regulator_desc regls_desc[SLG51000_MAX_REGULATORS] = {
0235 SLG51000_REGL_DESC(LDO1, ldo1, NULL, 2400000, 5000),
0236 SLG51000_REGL_DESC(LDO2, ldo2, NULL, 2400000, 5000),
0237 SLG51000_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000),
0238 SLG51000_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000),
0239 SLG51000_REGL_DESC(LDO5, ldo5, "vin5", 400000, 5000),
0240 SLG51000_REGL_DESC(LDO6, ldo6, "vin6", 400000, 5000),
0241 SLG51000_REGL_DESC(LDO7, ldo7, "vin7", 1200000, 10000),
0242 };
0243
0244 static int slg51000_regulator_init(struct slg51000 *chip)
0245 {
0246 struct regulator_config config = { };
0247 struct regulator_desc *rdesc;
0248 unsigned int reg, val;
0249 u8 vsel_range[2];
0250 int id, ret = 0;
0251 const unsigned int min_regs[SLG51000_MAX_REGULATORS] = {
0252 SLG51000_LDO1_MINV, SLG51000_LDO2_MINV, SLG51000_LDO3_MINV,
0253 SLG51000_LDO4_MINV, SLG51000_LDO5_MINV, SLG51000_LDO6_MINV,
0254 SLG51000_LDO7_MINV,
0255 };
0256
0257 for (id = 0; id < SLG51000_MAX_REGULATORS; id++) {
0258 chip->rdesc[id] = ®ls_desc[id];
0259 rdesc = chip->rdesc[id];
0260 config.regmap = chip->regmap;
0261 config.dev = chip->dev;
0262 config.driver_data = chip;
0263
0264 ret = regmap_bulk_read(chip->regmap, min_regs[id],
0265 vsel_range, 2);
0266 if (ret < 0) {
0267 dev_err(chip->dev,
0268 "Failed to read the MIN register\n");
0269 return ret;
0270 }
0271
0272 switch (id) {
0273 case SLG51000_REGULATOR_LDO1:
0274 case SLG51000_REGULATOR_LDO2:
0275 if (id == SLG51000_REGULATOR_LDO1)
0276 reg = SLG51000_LDO1_MISC1;
0277 else
0278 reg = SLG51000_LDO2_MISC1;
0279
0280 ret = regmap_read(chip->regmap, reg, &val);
0281 if (ret < 0) {
0282 dev_err(chip->dev,
0283 "Failed to read voltage range of ldo%d\n",
0284 id + 1);
0285 return ret;
0286 }
0287
0288 rdesc->linear_min_sel = vsel_range[0];
0289 rdesc->n_voltages = vsel_range[1] + 1;
0290 if (val & SLG51000_SEL_VRANGE_MASK)
0291 rdesc->min_uV = SLG51000_LDOHP_HV_MIN
0292 + (vsel_range[0]
0293 * rdesc->uV_step);
0294 else
0295 rdesc->min_uV = SLG51000_LDOHP_LV_MIN
0296 + (vsel_range[0]
0297 * rdesc->uV_step);
0298 break;
0299
0300 case SLG51000_REGULATOR_LDO5:
0301 case SLG51000_REGULATOR_LDO6:
0302 if (id == SLG51000_REGULATOR_LDO5)
0303 reg = SLG51000_LDO5_TRIM2;
0304 else
0305 reg = SLG51000_LDO6_TRIM2;
0306
0307 ret = regmap_read(chip->regmap, reg, &val);
0308 if (ret < 0) {
0309 dev_err(chip->dev,
0310 "Failed to read LDO mode register\n");
0311 return ret;
0312 }
0313
0314 if (val & SLG51000_SEL_BYP_MODE_MASK) {
0315 rdesc->ops = &slg51000_switch_ops;
0316 rdesc->n_voltages = 0;
0317 rdesc->min_uV = 0;
0318 rdesc->uV_step = 0;
0319 rdesc->linear_min_sel = 0;
0320 break;
0321 }
0322 fallthrough;
0323
0324 default:
0325 rdesc->linear_min_sel = vsel_range[0];
0326 rdesc->n_voltages = vsel_range[1] + 1;
0327 rdesc->min_uV = rdesc->min_uV
0328 + (vsel_range[0] * rdesc->uV_step);
0329 break;
0330 }
0331
0332 chip->rdev[id] = devm_regulator_register(chip->dev, rdesc,
0333 &config);
0334 if (IS_ERR(chip->rdev[id])) {
0335 ret = PTR_ERR(chip->rdev[id]);
0336 dev_err(chip->dev,
0337 "Failed to register regulator(%s):%d\n",
0338 chip->rdesc[id]->name, ret);
0339 return ret;
0340 }
0341 }
0342
0343 return 0;
0344 }
0345
0346 static irqreturn_t slg51000_irq_handler(int irq, void *data)
0347 {
0348 struct slg51000 *chip = data;
0349 struct regmap *regmap = chip->regmap;
0350 enum { R0 = 0, R1, R2, REG_MAX };
0351 u8 evt[SLG51000_MAX_EVT_REGISTER][REG_MAX];
0352 int ret, i, handled = IRQ_NONE;
0353 unsigned int evt_otp, mask_otp;
0354
0355
0356 for (i = 0; i < SLG51000_MAX_EVT_REGISTER; i++) {
0357 ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX);
0358 if (ret < 0) {
0359 dev_err(chip->dev,
0360 "Failed to read event registers(%d)\n", ret);
0361 return IRQ_NONE;
0362 }
0363 }
0364
0365 ret = regmap_read(regmap, SLG51000_OTP_EVENT, &evt_otp);
0366 if (ret < 0) {
0367 dev_err(chip->dev,
0368 "Failed to read otp event registers(%d)\n", ret);
0369 return IRQ_NONE;
0370 }
0371
0372 ret = regmap_read(regmap, SLG51000_OTP_IRQ_MASK, &mask_otp);
0373 if (ret < 0) {
0374 dev_err(chip->dev,
0375 "Failed to read otp mask register(%d)\n", ret);
0376 return IRQ_NONE;
0377 }
0378
0379 if ((evt_otp & SLG51000_EVT_CRC_MASK) &&
0380 !(mask_otp & SLG51000_IRQ_CRC_MASK)) {
0381 dev_info(chip->dev,
0382 "OTP has been read or OTP crc is not zero\n");
0383 handled = IRQ_HANDLED;
0384 }
0385
0386 for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
0387 if (!(evt[i][R2] & SLG51000_IRQ_ILIM_FLAG_MASK) &&
0388 (evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) {
0389 regulator_notifier_call_chain(chip->rdev[i],
0390 REGULATOR_EVENT_OVER_CURRENT, NULL);
0391
0392 if (evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK)
0393 dev_warn(chip->dev,
0394 "Over-current limit(ldo%d)\n", i + 1);
0395 handled = IRQ_HANDLED;
0396 }
0397 }
0398
0399 if (!(evt[SLG51000_SCTL_EVT][R2] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK) &&
0400 (evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) {
0401 for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
0402 if (!(evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK) &&
0403 (evt[i][R1] & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
0404 regulator_notifier_call_chain(chip->rdev[i],
0405 REGULATOR_EVENT_OVER_TEMP, NULL);
0406 }
0407 }
0408 handled = IRQ_HANDLED;
0409 if (evt[SLG51000_SCTL_EVT][R1] &
0410 SLG51000_STA_HIGH_TEMP_WARN_MASK)
0411 dev_warn(chip->dev, "High temperature warning!\n");
0412 }
0413
0414 return handled;
0415 }
0416
0417 static void slg51000_clear_fault_log(struct slg51000 *chip)
0418 {
0419 unsigned int val = 0;
0420 int ret = 0;
0421
0422 ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val);
0423 if (ret < 0) {
0424 dev_err(chip->dev, "Failed to read Fault log register\n");
0425 return;
0426 }
0427
0428 if (val & SLG51000_FLT_OVER_TEMP_MASK)
0429 dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n");
0430 if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK)
0431 dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
0432 if (val & SLG51000_FLT_RST_MASK)
0433 dev_dbg(chip->dev, "Fault log: FLT_RST\n");
0434 if (val & SLG51000_FLT_POR_MASK)
0435 dev_dbg(chip->dev, "Fault log: FLT_POR\n");
0436 }
0437
0438 static int slg51000_i2c_probe(struct i2c_client *client)
0439 {
0440 struct device *dev = &client->dev;
0441 struct slg51000 *chip;
0442 struct gpio_desc *cs_gpiod;
0443 int error, ret;
0444
0445 chip = devm_kzalloc(dev, sizeof(struct slg51000), GFP_KERNEL);
0446 if (!chip)
0447 return -ENOMEM;
0448
0449 cs_gpiod = devm_gpiod_get_optional(dev, "dlg,cs",
0450 GPIOD_OUT_HIGH |
0451 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
0452 if (IS_ERR(cs_gpiod))
0453 return PTR_ERR(cs_gpiod);
0454
0455 if (cs_gpiod) {
0456 dev_info(dev, "Found chip selector property\n");
0457 chip->cs_gpiod = cs_gpiod;
0458 }
0459
0460 i2c_set_clientdata(client, chip);
0461 chip->chip_irq = client->irq;
0462 chip->dev = dev;
0463 chip->regmap = devm_regmap_init_i2c(client, &slg51000_regmap_config);
0464 if (IS_ERR(chip->regmap)) {
0465 error = PTR_ERR(chip->regmap);
0466 dev_err(dev, "Failed to allocate register map: %d\n",
0467 error);
0468 return error;
0469 }
0470
0471 ret = slg51000_regulator_init(chip);
0472 if (ret < 0) {
0473 dev_err(chip->dev, "Failed to init regulator(%d)\n", ret);
0474 return ret;
0475 }
0476
0477 slg51000_clear_fault_log(chip);
0478
0479 if (chip->chip_irq) {
0480 ret = devm_request_threaded_irq(dev, chip->chip_irq, NULL,
0481 slg51000_irq_handler,
0482 (IRQF_TRIGGER_HIGH |
0483 IRQF_ONESHOT),
0484 "slg51000-irq", chip);
0485 if (ret != 0) {
0486 dev_err(dev, "Failed to request IRQ: %d\n",
0487 chip->chip_irq);
0488 return ret;
0489 }
0490 } else {
0491 dev_info(dev, "No IRQ configured\n");
0492 }
0493
0494 return ret;
0495 }
0496
0497 static const struct i2c_device_id slg51000_i2c_id[] = {
0498 {"slg51000", 0},
0499 {},
0500 };
0501 MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
0502
0503 static struct i2c_driver slg51000_regulator_driver = {
0504 .driver = {
0505 .name = "slg51000-regulator",
0506 },
0507 .probe_new = slg51000_i2c_probe,
0508 .id_table = slg51000_i2c_id,
0509 };
0510
0511 module_i2c_driver(slg51000_regulator_driver);
0512
0513 MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
0514 MODULE_DESCRIPTION("SLG51000 regulator driver");
0515 MODULE_LICENSE("GPL");
0516
