drivers/regulator/rtmv20-regulator.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002
0003 #include <linux/delay.h>
0004 #include <linux/gpio/consumer.h>
0005 #include <linux/i2c.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/property.h>
0010 #include <linux/regmap.h>
0011 #include <linux/regulator/driver.h>
0012
0013 #define RTMV20_REG_DEVINFO  0x00
0014 #define RTMV20_REG_PULSEDELAY   0x01
0015 #define RTMV20_REG_PULSEWIDTH   0x03
0016 #define RTMV20_REG_LDCTRL1  0x05
0017 #define RTMV20_REG_ESPULSEWIDTH 0x06
0018 #define RTMV20_REG_ESLDCTRL1    0x08
0019 #define RTMV20_REG_LBP      0x0A
0020 #define RTMV20_REG_LDCTRL2  0x0B
0021 #define RTMV20_REG_FSIN1CTRL1   0x0D
0022 #define RTMV20_REG_FSIN1CTRL3   0x0F
0023 #define RTMV20_REG_FSIN2CTRL1   0x10
0024 #define RTMV20_REG_FSIN2CTRL3   0x12
0025 #define RTMV20_REG_ENCTRL   0x13
0026 #define RTMV20_REG_STRBVSYNDLYL 0x29
0027 #define RTMV20_REG_LDIRQ    0x30
0028 #define RTMV20_REG_LDSTAT   0x40
0029 #define RTMV20_REG_LDMASK   0x50
0030 #define RTMV20_MAX_REGS     (RTMV20_REG_LDMASK + 1)
0031
0032 #define RTMV20_VID_MASK     GENMASK(7, 4)
0033 #define RICHTEK_VID     0x80
0034 #define RTMV20_LDCURR_MASK  GENMASK(7, 0)
0035 #define RTMV20_DELAY_MASK   GENMASK(9, 0)
0036 #define RTMV20_WIDTH_MASK   GENMASK(13, 0)
0037 #define RTMV20_WIDTH2_MASK  GENMASK(7, 0)
0038 #define RTMV20_LBPLVL_MASK  GENMASK(3, 0)
0039 #define RTMV20_LBPEN_MASK   BIT(7)
0040 #define RTMV20_STROBEPOL_MASK   BIT(0)
0041 #define RTMV20_VSYNPOL_MASK BIT(1)
0042 #define RTMV20_FSINEN_MASK  BIT(7)
0043 #define RTMV20_ESEN_MASK    BIT(6)
0044 #define RTMV20_FSINOUT_MASK BIT(2)
0045 #define LDENABLE_MASK       (BIT(3) | BIT(0))
0046
0047 #define OTPEVT_MASK     BIT(4)
0048 #define SHORTEVT_MASK       BIT(3)
0049 #define OPENEVT_MASK        BIT(2)
0050 #define LBPEVT_MASK     BIT(1)
0051 #define OCPEVT_MASK     BIT(0)
0052 #define FAILEVT_MASK        (SHORTEVT_MASK | OPENEVT_MASK | LBPEVT_MASK)
0053
0054 #define RTMV20_LSW_MINUA    0
0055 #define RTMV20_LSW_MAXUA    6000000
0056 #define RTMV20_LSW_STEPUA   30000
0057
0058 #define RTMV20_LSW_DEFAULTUA    3000000
0059
0060 #define RTMV20_I2CRDY_TIMEUS    200
0061 #define RTMV20_CSRDY_TIMEUS 2000
0062
0063 struct rtmv20_priv {
0064     struct device *dev;
0065     struct regmap *regmap;
0066     struct gpio_desc *enable_gpio;
0067     struct regulator_dev *rdev;
0068 };
0069
0070 static int rtmv20_lsw_enable(struct regulator_dev *rdev)
0071 {
0072     struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
0073     int ret;
0074
0075     gpiod_set_value(priv->enable_gpio, 1);
0076
0077     /* Wait for I2C can be accessed */
0078     usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
0079
0080     /* HW re-enable, disable cache only and sync regcache here */
0081     regcache_cache_only(priv->regmap, false);
0082     ret = regcache_sync(priv->regmap);
0083     if (ret)
0084         return ret;
0085
0086     return regulator_enable_regmap(rdev);
0087 }
0088
0089 static int rtmv20_lsw_disable(struct regulator_dev *rdev)
0090 {
0091     struct rtmv20_priv *priv = rdev_get_drvdata(rdev);
0092     int ret;
0093
0094     ret = regulator_disable_regmap(rdev);
0095     if (ret)
0096         return ret;
0097
0098     /* Mark the regcache as dirty and cache only before HW disabled */
0099     regcache_cache_only(priv->regmap, true);
0100     regcache_mark_dirty(priv->regmap);
0101
0102     gpiod_set_value(priv->enable_gpio, 0);
0103
0104     return 0;
0105 }
0106
0107 static int rtmv20_lsw_set_current_limit(struct regulator_dev *rdev, int min_uA,
0108                     int max_uA)
0109 {
0110     int sel;
0111
0112     if (min_uA > RTMV20_LSW_MAXUA || max_uA < RTMV20_LSW_MINUA)
0113         return -EINVAL;
0114
0115     if (max_uA > RTMV20_LSW_MAXUA)
0116         max_uA = RTMV20_LSW_MAXUA;
0117
0118     sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA;
0119
0120     /* Ensure the selected setting is still in range */
0121     if ((sel * RTMV20_LSW_STEPUA + RTMV20_LSW_MINUA) < min_uA)
0122         return -EINVAL;
0123
0124     sel <<= ffs(rdev->desc->csel_mask) - 1;
0125
0126     return regmap_update_bits(rdev->regmap, rdev->desc->csel_reg,
0127                   rdev->desc->csel_mask, sel);
0128 }
0129
0130 static int rtmv20_lsw_get_current_limit(struct regulator_dev *rdev)
0131 {
0132     unsigned int val;
0133     int ret;
0134
0135     ret = regmap_read(rdev->regmap, rdev->desc->csel_reg, &val);
0136     if (ret)
0137         return ret;
0138
0139     val &= rdev->desc->csel_mask;
0140     val >>= ffs(rdev->desc->csel_mask) - 1;
0141
0142     return val * RTMV20_LSW_STEPUA + RTMV20_LSW_MINUA;
0143 }
0144
0145 static const struct regulator_ops rtmv20_regulator_ops = {
0146     .set_current_limit = rtmv20_lsw_set_current_limit,
0147     .get_current_limit = rtmv20_lsw_get_current_limit,
0148     .enable = rtmv20_lsw_enable,
0149     .disable = rtmv20_lsw_disable,
0150     .is_enabled = regulator_is_enabled_regmap,
0151 };
0152
0153 static const struct regulator_desc rtmv20_lsw_desc = {
0154     .name = "rtmv20,lsw",
0155     .of_match = of_match_ptr("lsw"),
0156     .type = REGULATOR_CURRENT,
0157     .owner = THIS_MODULE,
0158     .ops = &rtmv20_regulator_ops,
0159     .csel_reg = RTMV20_REG_LDCTRL1,
0160     .csel_mask = RTMV20_LDCURR_MASK,
0161     .enable_reg = RTMV20_REG_ENCTRL,
0162     .enable_mask = LDENABLE_MASK,
0163     .enable_time = RTMV20_CSRDY_TIMEUS,
0164 };
0165
0166 static irqreturn_t rtmv20_irq_handler(int irq, void *data)
0167 {
0168     struct rtmv20_priv *priv = data;
0169     unsigned int val;
0170     int ret;
0171
0172     ret = regmap_read(priv->regmap, RTMV20_REG_LDIRQ, &val);
0173     if (ret) {
0174         dev_err(priv->dev, "Failed to get irq flags\n");
0175         return IRQ_NONE;
0176     }
0177
0178     if (val & OTPEVT_MASK)
0179         regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_TEMP, NULL);
0180
0181     if (val & OCPEVT_MASK)
0182         regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
0183
0184     if (val & FAILEVT_MASK)
0185         regulator_notifier_call_chain(priv->rdev, REGULATOR_EVENT_FAIL, NULL);
0186
0187     return IRQ_HANDLED;
0188 }
0189
0190 static u32 clamp_to_selector(u32 val, u32 min, u32 max, u32 step)
0191 {
0192     u32 retval = clamp_val(val, min, max);
0193
0194     return (retval - min) / step;
0195 }
0196
0197 static int rtmv20_properties_init(struct rtmv20_priv *priv)
0198 {
0199     const struct {
0200         const char *name;
0201         u32 def;
0202         u32 min;
0203         u32 max;
0204         u32 step;
0205         u32 addr;
0206         u32 mask;
0207     } props[] = {
0208         { "richtek,ld-pulse-delay-us", 0, 0, 100000, 100, RTMV20_REG_PULSEDELAY,
0209             RTMV20_DELAY_MASK },
0210         { "richtek,ld-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_PULSEWIDTH,
0211             RTMV20_WIDTH_MASK },
0212         { "richtek,fsin1-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN1CTRL1,
0213             RTMV20_DELAY_MASK },
0214         { "richtek,fsin1-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN1CTRL3,
0215             RTMV20_WIDTH2_MASK },
0216         { "richtek,fsin2-delay-us", 23000, 0, 100000, 100, RTMV20_REG_FSIN2CTRL1,
0217             RTMV20_DELAY_MASK },
0218         { "richtek,fsin2-width-us", 160, 40, 10000, 40, RTMV20_REG_FSIN2CTRL3,
0219             RTMV20_WIDTH2_MASK },
0220         { "richtek,es-pulse-width-us", 1200, 0, 10000, 1, RTMV20_REG_ESPULSEWIDTH,
0221             RTMV20_WIDTH_MASK },
0222         { "richtek,es-ld-current-microamp", 3000000, 0, 6000000, 30000,
0223             RTMV20_REG_ESLDCTRL1, RTMV20_LDCURR_MASK },
0224         { "richtek,lbp-level-microvolt", 2700000, 2400000, 3700000, 100000, RTMV20_REG_LBP,
0225             RTMV20_LBPLVL_MASK },
0226         { "richtek,lbp-enable", 0, 0, 1, 1, RTMV20_REG_LBP, RTMV20_LBPEN_MASK },
0227         { "richtek,strobe-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
0228             RTMV20_STROBEPOL_MASK },
0229         { "richtek,vsync-polarity-high", 1, 0, 1, 1, RTMV20_REG_LDCTRL2,
0230             RTMV20_VSYNPOL_MASK },
0231         { "richtek,fsin-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINEN_MASK },
0232         { "richtek,fsin-output", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_FSINOUT_MASK },
0233         { "richtek,es-enable", 0, 0, 1, 1, RTMV20_REG_ENCTRL, RTMV20_ESEN_MASK },
0234     };
0235     int i, ret;
0236
0237     for (i = 0; i < ARRAY_SIZE(props); i++) {
0238         __be16 bval16;
0239         u16 val16;
0240         u32 temp;
0241         int significant_bit = fls(props[i].mask);
0242         int shift = ffs(props[i].mask) - 1;
0243
0244         if (props[i].max > 1) {
0245             ret = device_property_read_u32(priv->dev, props[i].name, &temp);
0246             if (ret)
0247                 temp = props[i].def;
0248         } else
0249             temp = device_property_read_bool(priv->dev, props[i].name);
0250
0251         temp = clamp_to_selector(temp, props[i].min, props[i].max, props[i].step);
0252
0253         /* If significant bit is over 8, two byte access, others one */
0254         if (significant_bit > 8) {
0255             ret = regmap_raw_read(priv->regmap, props[i].addr, &bval16, sizeof(bval16));
0256             if (ret)
0257                 return ret;
0258
0259             val16 = be16_to_cpu(bval16);
0260             val16 &= ~props[i].mask;
0261             val16 |= (temp << shift);
0262             bval16 = cpu_to_be16(val16);
0263
0264             ret = regmap_raw_write(priv->regmap, props[i].addr, &bval16,
0265                            sizeof(bval16));
0266         } else {
0267             ret = regmap_update_bits(priv->regmap, props[i].addr, props[i].mask,
0268                          temp << shift);
0269         }
0270
0271         if (ret)
0272             return ret;
0273     }
0274
0275     return 0;
0276 }
0277
0278 static int rtmv20_check_chip_exist(struct rtmv20_priv *priv)
0279 {
0280     unsigned int val;
0281     int ret;
0282
0283     ret = regmap_read(priv->regmap, RTMV20_REG_DEVINFO, &val);
0284     if (ret)
0285         return ret;
0286
0287     if ((val & RTMV20_VID_MASK) != RICHTEK_VID)
0288         return -ENODEV;
0289
0290     return 0;
0291 }
0292
0293 static bool rtmv20_is_accessible_reg(struct device *dev, unsigned int reg)
0294 {
0295     switch (reg) {
0296     case RTMV20_REG_DEVINFO ... RTMV20_REG_STRBVSYNDLYL:
0297     case RTMV20_REG_LDIRQ:
0298     case RTMV20_REG_LDSTAT:
0299     case RTMV20_REG_LDMASK:
0300         return true;
0301     }
0302     return false;
0303 }
0304
0305 static bool rtmv20_is_volatile_reg(struct device *dev, unsigned int reg)
0306 {
0307     if (reg == RTMV20_REG_LDIRQ || reg == RTMV20_REG_LDSTAT)
0308         return true;
0309     return false;
0310 }
0311
0312 static const struct regmap_config rtmv20_regmap_config = {
0313     .reg_bits = 8,
0314     .val_bits = 8,
0315     .cache_type = REGCACHE_RBTREE,
0316     .max_register = RTMV20_REG_LDMASK,
0317     .num_reg_defaults_raw = RTMV20_MAX_REGS,
0318
0319     .writeable_reg = rtmv20_is_accessible_reg,
0320     .readable_reg = rtmv20_is_accessible_reg,
0321     .volatile_reg = rtmv20_is_volatile_reg,
0322 };
0323
0324 static int rtmv20_probe(struct i2c_client *i2c)
0325 {
0326     struct rtmv20_priv *priv;
0327     struct regulator_config config = {};
0328     int ret;
0329
0330     priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
0331     if (!priv)
0332         return -ENOMEM;
0333
0334     priv->dev = &i2c->dev;
0335
0336     /* Before regmap register, configure HW enable to make I2C accessible */
0337     priv->enable_gpio = devm_gpiod_get(&i2c->dev, "enable", GPIOD_OUT_HIGH);
0338     if (IS_ERR(priv->enable_gpio)) {
0339         dev_err(&i2c->dev, "Failed to get enable gpio\n");
0340         return PTR_ERR(priv->enable_gpio);
0341     }
0342
0343     /* Wait for I2C can be accessed */
0344     usleep_range(RTMV20_I2CRDY_TIMEUS, RTMV20_I2CRDY_TIMEUS + 100);
0345
0346     priv->regmap = devm_regmap_init_i2c(i2c, &rtmv20_regmap_config);
0347     if (IS_ERR(priv->regmap)) {
0348         dev_err(&i2c->dev, "Failed to allocate register map\n");
0349         return PTR_ERR(priv->regmap);
0350     }
0351
0352     ret = rtmv20_check_chip_exist(priv);
0353     if (ret) {
0354         dev_err(&i2c->dev, "Chip vendor info is not matched\n");
0355         return ret;
0356     }
0357
0358     ret = rtmv20_properties_init(priv);
0359     if (ret) {
0360         dev_err(&i2c->dev, "Failed to init properties\n");
0361         return ret;
0362     }
0363
0364     /*
0365      * keep in shutdown mode to minimize the current consumption
0366      * and also mark regcache as dirty
0367      */
0368     regcache_cache_only(priv->regmap, true);
0369     regcache_mark_dirty(priv->regmap);
0370     gpiod_set_value(priv->enable_gpio, 0);
0371
0372     config.dev = &i2c->dev;
0373     config.regmap = priv->regmap;
0374     config.driver_data = priv;
0375     priv->rdev = devm_regulator_register(&i2c->dev, &rtmv20_lsw_desc, &config);
0376     if (IS_ERR(priv->rdev)) {
0377         dev_err(&i2c->dev, "Failed to register regulator\n");
0378         return PTR_ERR(priv->rdev);
0379     }
0380
0381     /* Unmask all events before IRQ registered */
0382     ret = regmap_write(priv->regmap, RTMV20_REG_LDMASK, 0);
0383     if (ret)
0384         return ret;
0385
0386     return devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rtmv20_irq_handler,
0387                      IRQF_ONESHOT, dev_name(&i2c->dev), priv);
0388 }
0389
0390 static int __maybe_unused rtmv20_suspend(struct device *dev)
0391 {
0392     struct i2c_client *i2c = to_i2c_client(dev);
0393
0394     /*
0395      * When system suspend, disable irq to prevent interrupt trigger
0396      * during I2C bus suspend
0397      */
0398     disable_irq(i2c->irq);
0399     if (device_may_wakeup(dev))
0400         enable_irq_wake(i2c->irq);
0401
0402     return 0;
0403 }
0404
0405 static int __maybe_unused rtmv20_resume(struct device *dev)
0406 {
0407     struct i2c_client *i2c = to_i2c_client(dev);
0408
0409     /* Enable irq after I2C bus already resume */
0410     enable_irq(i2c->irq);
0411     if (device_may_wakeup(dev))
0412         disable_irq_wake(i2c->irq);
0413
0414     return 0;
0415 }
0416
0417 static SIMPLE_DEV_PM_OPS(rtmv20_pm, rtmv20_suspend, rtmv20_resume);
0418
0419 static const struct of_device_id __maybe_unused rtmv20_of_id[] = {
0420     { .compatible = "richtek,rtmv20", },
0421     {}
0422 };
0423 MODULE_DEVICE_TABLE(of, rtmv20_of_id);
0424
0425 static struct i2c_driver rtmv20_driver = {
0426     .driver = {
0427         .name = "rtmv20",
0428         .of_match_table = of_match_ptr(rtmv20_of_id),
0429         .pm = &rtmv20_pm,
0430     },
0431     .probe_new = rtmv20_probe,
0432 };
0433 module_i2c_driver(rtmv20_driver);
0434
0435 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
0436 MODULE_DESCRIPTION("Richtek RTMV20 Regulator Driver");
0437 MODULE_LICENSE("GPL v2");