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0007 #include <linux/module.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/of.h>
0010 #include <linux/of_device.h>
0011 #include <linux/regulator/driver.h>
0012 #include <linux/regulator/machine.h>
0013 #include <linux/regulator/of_regulator.h>
0014 #include <linux/mfd/qcom_rpm.h>
0015
0016 #include <dt-bindings/mfd/qcom-rpm.h>
0017
0018 #define MAX_REQUEST_LEN 2
0019
0020 struct request_member {
0021 int word;
0022 unsigned int mask;
0023 int shift;
0024 };
0025
0026 struct rpm_reg_parts {
0027 struct request_member mV;
0028 struct request_member uV;
0029 struct request_member ip;
0030 struct request_member pd;
0031 struct request_member ia;
0032 struct request_member fm;
0033 struct request_member pm;
0034 struct request_member pc;
0035 struct request_member pf;
0036 struct request_member enable_state;
0037 struct request_member comp_mode;
0038 struct request_member freq;
0039 struct request_member freq_clk_src;
0040 struct request_member hpm;
0041 int request_len;
0042 };
0043
0044 #define FORCE_MODE_IS_2_BITS(reg) \
0045 (((reg)->parts->fm.mask >> (reg)->parts->fm.shift) == 3)
0046
0047 struct qcom_rpm_reg {
0048 struct qcom_rpm *rpm;
0049
0050 struct mutex lock;
0051 struct device *dev;
0052 struct regulator_desc desc;
0053 const struct rpm_reg_parts *parts;
0054
0055 int resource;
0056 u32 val[MAX_REQUEST_LEN];
0057
0058 int uV;
0059 int is_enabled;
0060
0061 bool supports_force_mode_auto;
0062 bool supports_force_mode_bypass;
0063 };
0064
0065 static const struct rpm_reg_parts rpm8660_ldo_parts = {
0066 .request_len = 2,
0067 .mV = { 0, 0x00000FFF, 0 },
0068 .ip = { 0, 0x00FFF000, 12 },
0069 .fm = { 0, 0x03000000, 24 },
0070 .pc = { 0, 0x3C000000, 26 },
0071 .pf = { 0, 0xC0000000, 30 },
0072 .pd = { 1, 0x00000001, 0 },
0073 .ia = { 1, 0x00001FFE, 1 },
0074 };
0075
0076 static const struct rpm_reg_parts rpm8660_smps_parts = {
0077 .request_len = 2,
0078 .mV = { 0, 0x00000FFF, 0 },
0079 .ip = { 0, 0x00FFF000, 12 },
0080 .fm = { 0, 0x03000000, 24 },
0081 .pc = { 0, 0x3C000000, 26 },
0082 .pf = { 0, 0xC0000000, 30 },
0083 .pd = { 1, 0x00000001, 0 },
0084 .ia = { 1, 0x00001FFE, 1 },
0085 .freq = { 1, 0x001FE000, 13 },
0086 .freq_clk_src = { 1, 0x00600000, 21 },
0087 };
0088
0089 static const struct rpm_reg_parts rpm8660_switch_parts = {
0090 .request_len = 1,
0091 .enable_state = { 0, 0x00000001, 0 },
0092 .pd = { 0, 0x00000002, 1 },
0093 .pc = { 0, 0x0000003C, 2 },
0094 .pf = { 0, 0x000000C0, 6 },
0095 .hpm = { 0, 0x00000300, 8 },
0096 };
0097
0098 static const struct rpm_reg_parts rpm8660_ncp_parts = {
0099 .request_len = 1,
0100 .mV = { 0, 0x00000FFF, 0 },
0101 .enable_state = { 0, 0x00001000, 12 },
0102 .comp_mode = { 0, 0x00002000, 13 },
0103 .freq = { 0, 0x003FC000, 14 },
0104 };
0105
0106 static const struct rpm_reg_parts rpm8960_ldo_parts = {
0107 .request_len = 2,
0108 .uV = { 0, 0x007FFFFF, 0 },
0109 .pd = { 0, 0x00800000, 23 },
0110 .pc = { 0, 0x0F000000, 24 },
0111 .pf = { 0, 0xF0000000, 28 },
0112 .ip = { 1, 0x000003FF, 0 },
0113 .ia = { 1, 0x000FFC00, 10 },
0114 .fm = { 1, 0x00700000, 20 },
0115 };
0116
0117 static const struct rpm_reg_parts rpm8960_smps_parts = {
0118 .request_len = 2,
0119 .uV = { 0, 0x007FFFFF, 0 },
0120 .pd = { 0, 0x00800000, 23 },
0121 .pc = { 0, 0x0F000000, 24 },
0122 .pf = { 0, 0xF0000000, 28 },
0123 .ip = { 1, 0x000003FF, 0 },
0124 .ia = { 1, 0x000FFC00, 10 },
0125 .fm = { 1, 0x00700000, 20 },
0126 .pm = { 1, 0x00800000, 23 },
0127 .freq = { 1, 0x1F000000, 24 },
0128 .freq_clk_src = { 1, 0x60000000, 29 },
0129 };
0130
0131 static const struct rpm_reg_parts rpm8960_switch_parts = {
0132 .request_len = 1,
0133 .enable_state = { 0, 0x00000001, 0 },
0134 .pd = { 0, 0x00000002, 1 },
0135 .pc = { 0, 0x0000003C, 2 },
0136 .pf = { 0, 0x000003C0, 6 },
0137 .hpm = { 0, 0x00000C00, 10 },
0138 };
0139
0140 static const struct rpm_reg_parts rpm8960_ncp_parts = {
0141 .request_len = 1,
0142 .uV = { 0, 0x007FFFFF, 0 },
0143 .enable_state = { 0, 0x00800000, 23 },
0144 .comp_mode = { 0, 0x01000000, 24 },
0145 .freq = { 0, 0x3E000000, 25 },
0146 };
0147
0148
0149
0150
0151 static const struct linear_range pldo_ranges[] = {
0152 REGULATOR_LINEAR_RANGE( 750000, 0, 59, 12500),
0153 REGULATOR_LINEAR_RANGE(1500000, 60, 123, 25000),
0154 REGULATOR_LINEAR_RANGE(3100000, 124, 160, 50000),
0155 };
0156
0157 static const struct linear_range nldo_ranges[] = {
0158 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
0159 };
0160
0161 static const struct linear_range nldo1200_ranges[] = {
0162 REGULATOR_LINEAR_RANGE( 375000, 0, 59, 6250),
0163 REGULATOR_LINEAR_RANGE( 750000, 60, 123, 12500),
0164 };
0165
0166 static const struct linear_range smps_ranges[] = {
0167 REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500),
0168 REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
0169 REGULATOR_LINEAR_RANGE(1500000, 90, 153, 25000),
0170 };
0171
0172 static const struct linear_range ftsmps_ranges[] = {
0173 REGULATOR_LINEAR_RANGE( 350000, 0, 6, 50000),
0174 REGULATOR_LINEAR_RANGE( 700000, 7, 63, 12500),
0175 REGULATOR_LINEAR_RANGE(1500000, 64, 100, 50000),
0176 };
0177
0178 static const struct linear_range smb208_ranges[] = {
0179 REGULATOR_LINEAR_RANGE( 375000, 0, 29, 12500),
0180 REGULATOR_LINEAR_RANGE( 750000, 30, 89, 12500),
0181 REGULATOR_LINEAR_RANGE(1500000, 90, 153, 25000),
0182 REGULATOR_LINEAR_RANGE(3100000, 154, 234, 25000),
0183 };
0184
0185 static const struct linear_range ncp_ranges[] = {
0186 REGULATOR_LINEAR_RANGE(1500000, 0, 31, 50000),
0187 };
0188
0189 static int rpm_reg_write(struct qcom_rpm_reg *vreg,
0190 const struct request_member *req,
0191 const int value)
0192 {
0193 if (WARN_ON((value << req->shift) & ~req->mask))
0194 return -EINVAL;
0195
0196 vreg->val[req->word] &= ~req->mask;
0197 vreg->val[req->word] |= value << req->shift;
0198
0199 return qcom_rpm_write(vreg->rpm,
0200 QCOM_RPM_ACTIVE_STATE,
0201 vreg->resource,
0202 vreg->val,
0203 vreg->parts->request_len);
0204 }
0205
0206 static int rpm_reg_set_mV_sel(struct regulator_dev *rdev,
0207 unsigned selector)
0208 {
0209 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0210 const struct rpm_reg_parts *parts = vreg->parts;
0211 const struct request_member *req = &parts->mV;
0212 int ret = 0;
0213 int uV;
0214
0215 if (req->mask == 0)
0216 return -EINVAL;
0217
0218 uV = regulator_list_voltage_linear_range(rdev, selector);
0219 if (uV < 0)
0220 return uV;
0221
0222 mutex_lock(&vreg->lock);
0223 if (vreg->is_enabled)
0224 ret = rpm_reg_write(vreg, req, uV / 1000);
0225
0226 if (!ret)
0227 vreg->uV = uV;
0228 mutex_unlock(&vreg->lock);
0229
0230 return ret;
0231 }
0232
0233 static int rpm_reg_set_uV_sel(struct regulator_dev *rdev,
0234 unsigned selector)
0235 {
0236 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0237 const struct rpm_reg_parts *parts = vreg->parts;
0238 const struct request_member *req = &parts->uV;
0239 int ret = 0;
0240 int uV;
0241
0242 if (req->mask == 0)
0243 return -EINVAL;
0244
0245 uV = regulator_list_voltage_linear_range(rdev, selector);
0246 if (uV < 0)
0247 return uV;
0248
0249 mutex_lock(&vreg->lock);
0250 if (vreg->is_enabled)
0251 ret = rpm_reg_write(vreg, req, uV);
0252
0253 if (!ret)
0254 vreg->uV = uV;
0255 mutex_unlock(&vreg->lock);
0256
0257 return ret;
0258 }
0259
0260 static int rpm_reg_get_voltage(struct regulator_dev *rdev)
0261 {
0262 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0263
0264 return vreg->uV;
0265 }
0266
0267 static int rpm_reg_mV_enable(struct regulator_dev *rdev)
0268 {
0269 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0270 const struct rpm_reg_parts *parts = vreg->parts;
0271 const struct request_member *req = &parts->mV;
0272 int ret;
0273
0274 if (req->mask == 0)
0275 return -EINVAL;
0276
0277 mutex_lock(&vreg->lock);
0278 ret = rpm_reg_write(vreg, req, vreg->uV / 1000);
0279 if (!ret)
0280 vreg->is_enabled = 1;
0281 mutex_unlock(&vreg->lock);
0282
0283 return ret;
0284 }
0285
0286 static int rpm_reg_uV_enable(struct regulator_dev *rdev)
0287 {
0288 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0289 const struct rpm_reg_parts *parts = vreg->parts;
0290 const struct request_member *req = &parts->uV;
0291 int ret;
0292
0293 if (req->mask == 0)
0294 return -EINVAL;
0295
0296 mutex_lock(&vreg->lock);
0297 ret = rpm_reg_write(vreg, req, vreg->uV);
0298 if (!ret)
0299 vreg->is_enabled = 1;
0300 mutex_unlock(&vreg->lock);
0301
0302 return ret;
0303 }
0304
0305 static int rpm_reg_switch_enable(struct regulator_dev *rdev)
0306 {
0307 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0308 const struct rpm_reg_parts *parts = vreg->parts;
0309 const struct request_member *req = &parts->enable_state;
0310 int ret;
0311
0312 if (req->mask == 0)
0313 return -EINVAL;
0314
0315 mutex_lock(&vreg->lock);
0316 ret = rpm_reg_write(vreg, req, 1);
0317 if (!ret)
0318 vreg->is_enabled = 1;
0319 mutex_unlock(&vreg->lock);
0320
0321 return ret;
0322 }
0323
0324 static int rpm_reg_mV_disable(struct regulator_dev *rdev)
0325 {
0326 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0327 const struct rpm_reg_parts *parts = vreg->parts;
0328 const struct request_member *req = &parts->mV;
0329 int ret;
0330
0331 if (req->mask == 0)
0332 return -EINVAL;
0333
0334 mutex_lock(&vreg->lock);
0335 ret = rpm_reg_write(vreg, req, 0);
0336 if (!ret)
0337 vreg->is_enabled = 0;
0338 mutex_unlock(&vreg->lock);
0339
0340 return ret;
0341 }
0342
0343 static int rpm_reg_uV_disable(struct regulator_dev *rdev)
0344 {
0345 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0346 const struct rpm_reg_parts *parts = vreg->parts;
0347 const struct request_member *req = &parts->uV;
0348 int ret;
0349
0350 if (req->mask == 0)
0351 return -EINVAL;
0352
0353 mutex_lock(&vreg->lock);
0354 ret = rpm_reg_write(vreg, req, 0);
0355 if (!ret)
0356 vreg->is_enabled = 0;
0357 mutex_unlock(&vreg->lock);
0358
0359 return ret;
0360 }
0361
0362 static int rpm_reg_switch_disable(struct regulator_dev *rdev)
0363 {
0364 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0365 const struct rpm_reg_parts *parts = vreg->parts;
0366 const struct request_member *req = &parts->enable_state;
0367 int ret;
0368
0369 if (req->mask == 0)
0370 return -EINVAL;
0371
0372 mutex_lock(&vreg->lock);
0373 ret = rpm_reg_write(vreg, req, 0);
0374 if (!ret)
0375 vreg->is_enabled = 0;
0376 mutex_unlock(&vreg->lock);
0377
0378 return ret;
0379 }
0380
0381 static int rpm_reg_is_enabled(struct regulator_dev *rdev)
0382 {
0383 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0384
0385 return vreg->is_enabled;
0386 }
0387
0388 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
0389 {
0390 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
0391 const struct rpm_reg_parts *parts = vreg->parts;
0392 const struct request_member *req = &parts->ia;
0393 int load_mA = load_uA / 1000;
0394 int max_mA = req->mask >> req->shift;
0395 int ret;
0396
0397 if (req->mask == 0)
0398 return -EINVAL;
0399
0400 if (load_mA > max_mA)
0401 load_mA = max_mA;
0402
0403 mutex_lock(&vreg->lock);
0404 ret = rpm_reg_write(vreg, req, load_mA);
0405 mutex_unlock(&vreg->lock);
0406
0407 return ret;
0408 }
0409
0410 static const struct regulator_ops uV_ops = {
0411 .list_voltage = regulator_list_voltage_linear_range,
0412
0413 .set_voltage_sel = rpm_reg_set_uV_sel,
0414 .get_voltage = rpm_reg_get_voltage,
0415
0416 .enable = rpm_reg_uV_enable,
0417 .disable = rpm_reg_uV_disable,
0418 .is_enabled = rpm_reg_is_enabled,
0419
0420 .set_load = rpm_reg_set_load,
0421 };
0422
0423 static const struct regulator_ops mV_ops = {
0424 .list_voltage = regulator_list_voltage_linear_range,
0425
0426 .set_voltage_sel = rpm_reg_set_mV_sel,
0427 .get_voltage = rpm_reg_get_voltage,
0428
0429 .enable = rpm_reg_mV_enable,
0430 .disable = rpm_reg_mV_disable,
0431 .is_enabled = rpm_reg_is_enabled,
0432
0433 .set_load = rpm_reg_set_load,
0434 };
0435
0436 static const struct regulator_ops switch_ops = {
0437 .enable = rpm_reg_switch_enable,
0438 .disable = rpm_reg_switch_disable,
0439 .is_enabled = rpm_reg_is_enabled,
0440 };
0441
0442
0443
0444
0445 static const struct qcom_rpm_reg pm8018_pldo = {
0446 .desc.linear_ranges = pldo_ranges,
0447 .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
0448 .desc.n_voltages = 161,
0449 .desc.ops = &uV_ops,
0450 .parts = &rpm8960_ldo_parts,
0451 .supports_force_mode_auto = false,
0452 .supports_force_mode_bypass = false,
0453 };
0454
0455 static const struct qcom_rpm_reg pm8018_nldo = {
0456 .desc.linear_ranges = nldo_ranges,
0457 .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
0458 .desc.n_voltages = 64,
0459 .desc.ops = &uV_ops,
0460 .parts = &rpm8960_ldo_parts,
0461 .supports_force_mode_auto = false,
0462 .supports_force_mode_bypass = false,
0463 };
0464
0465 static const struct qcom_rpm_reg pm8018_smps = {
0466 .desc.linear_ranges = smps_ranges,
0467 .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
0468 .desc.n_voltages = 154,
0469 .desc.ops = &uV_ops,
0470 .parts = &rpm8960_smps_parts,
0471 .supports_force_mode_auto = false,
0472 .supports_force_mode_bypass = false,
0473 };
0474
0475 static const struct qcom_rpm_reg pm8018_switch = {
0476 .desc.ops = &switch_ops,
0477 .parts = &rpm8960_switch_parts,
0478 };
0479
0480
0481
0482
0483 static const struct qcom_rpm_reg pm8058_pldo = {
0484 .desc.linear_ranges = pldo_ranges,
0485 .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
0486 .desc.n_voltages = 161,
0487 .desc.ops = &mV_ops,
0488 .parts = &rpm8660_ldo_parts,
0489 .supports_force_mode_auto = false,
0490 .supports_force_mode_bypass = false,
0491 };
0492
0493 static const struct qcom_rpm_reg pm8058_nldo = {
0494 .desc.linear_ranges = nldo_ranges,
0495 .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
0496 .desc.n_voltages = 64,
0497 .desc.ops = &mV_ops,
0498 .parts = &rpm8660_ldo_parts,
0499 .supports_force_mode_auto = false,
0500 .supports_force_mode_bypass = false,
0501 };
0502
0503 static const struct qcom_rpm_reg pm8058_smps = {
0504 .desc.linear_ranges = smps_ranges,
0505 .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
0506 .desc.n_voltages = 154,
0507 .desc.ops = &mV_ops,
0508 .parts = &rpm8660_smps_parts,
0509 .supports_force_mode_auto = false,
0510 .supports_force_mode_bypass = false,
0511 };
0512
0513 static const struct qcom_rpm_reg pm8058_ncp = {
0514 .desc.linear_ranges = ncp_ranges,
0515 .desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
0516 .desc.n_voltages = 32,
0517 .desc.ops = &mV_ops,
0518 .parts = &rpm8660_ncp_parts,
0519 };
0520
0521 static const struct qcom_rpm_reg pm8058_switch = {
0522 .desc.ops = &switch_ops,
0523 .parts = &rpm8660_switch_parts,
0524 };
0525
0526
0527
0528
0529 static const struct qcom_rpm_reg pm8901_pldo = {
0530 .desc.linear_ranges = pldo_ranges,
0531 .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
0532 .desc.n_voltages = 161,
0533 .desc.ops = &mV_ops,
0534 .parts = &rpm8660_ldo_parts,
0535 .supports_force_mode_auto = false,
0536 .supports_force_mode_bypass = true,
0537 };
0538
0539 static const struct qcom_rpm_reg pm8901_nldo = {
0540 .desc.linear_ranges = nldo_ranges,
0541 .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
0542 .desc.n_voltages = 64,
0543 .desc.ops = &mV_ops,
0544 .parts = &rpm8660_ldo_parts,
0545 .supports_force_mode_auto = false,
0546 .supports_force_mode_bypass = true,
0547 };
0548
0549 static const struct qcom_rpm_reg pm8901_ftsmps = {
0550 .desc.linear_ranges = ftsmps_ranges,
0551 .desc.n_linear_ranges = ARRAY_SIZE(ftsmps_ranges),
0552 .desc.n_voltages = 101,
0553 .desc.ops = &mV_ops,
0554 .parts = &rpm8660_smps_parts,
0555 .supports_force_mode_auto = true,
0556 .supports_force_mode_bypass = false,
0557 };
0558
0559 static const struct qcom_rpm_reg pm8901_switch = {
0560 .desc.ops = &switch_ops,
0561 .parts = &rpm8660_switch_parts,
0562 };
0563
0564
0565
0566
0567 static const struct qcom_rpm_reg pm8921_pldo = {
0568 .desc.linear_ranges = pldo_ranges,
0569 .desc.n_linear_ranges = ARRAY_SIZE(pldo_ranges),
0570 .desc.n_voltages = 161,
0571 .desc.ops = &uV_ops,
0572 .parts = &rpm8960_ldo_parts,
0573 .supports_force_mode_auto = false,
0574 .supports_force_mode_bypass = true,
0575 };
0576
0577 static const struct qcom_rpm_reg pm8921_nldo = {
0578 .desc.linear_ranges = nldo_ranges,
0579 .desc.n_linear_ranges = ARRAY_SIZE(nldo_ranges),
0580 .desc.n_voltages = 64,
0581 .desc.ops = &uV_ops,
0582 .parts = &rpm8960_ldo_parts,
0583 .supports_force_mode_auto = false,
0584 .supports_force_mode_bypass = true,
0585 };
0586
0587 static const struct qcom_rpm_reg pm8921_nldo1200 = {
0588 .desc.linear_ranges = nldo1200_ranges,
0589 .desc.n_linear_ranges = ARRAY_SIZE(nldo1200_ranges),
0590 .desc.n_voltages = 124,
0591 .desc.ops = &uV_ops,
0592 .parts = &rpm8960_ldo_parts,
0593 .supports_force_mode_auto = false,
0594 .supports_force_mode_bypass = true,
0595 };
0596
0597 static const struct qcom_rpm_reg pm8921_smps = {
0598 .desc.linear_ranges = smps_ranges,
0599 .desc.n_linear_ranges = ARRAY_SIZE(smps_ranges),
0600 .desc.n_voltages = 154,
0601 .desc.ops = &uV_ops,
0602 .parts = &rpm8960_smps_parts,
0603 .supports_force_mode_auto = true,
0604 .supports_force_mode_bypass = false,
0605 };
0606
0607 static const struct qcom_rpm_reg pm8921_ncp = {
0608 .desc.linear_ranges = ncp_ranges,
0609 .desc.n_linear_ranges = ARRAY_SIZE(ncp_ranges),
0610 .desc.n_voltages = 32,
0611 .desc.ops = &uV_ops,
0612 .parts = &rpm8960_ncp_parts,
0613 };
0614
0615 static const struct qcom_rpm_reg pm8921_switch = {
0616 .desc.ops = &switch_ops,
0617 .parts = &rpm8960_switch_parts,
0618 };
0619
0620 static const struct qcom_rpm_reg smb208_smps = {
0621 .desc.linear_ranges = smb208_ranges,
0622 .desc.n_linear_ranges = ARRAY_SIZE(smb208_ranges),
0623 .desc.n_voltages = 235,
0624 .desc.ops = &uV_ops,
0625 .parts = &rpm8960_smps_parts,
0626 .supports_force_mode_auto = false,
0627 .supports_force_mode_bypass = false,
0628 };
0629
0630 static int rpm_reg_set(struct qcom_rpm_reg *vreg,
0631 const struct request_member *req,
0632 const int value)
0633 {
0634 if (req->mask == 0 || (value << req->shift) & ~req->mask)
0635 return -EINVAL;
0636
0637 vreg->val[req->word] &= ~req->mask;
0638 vreg->val[req->word] |= value << req->shift;
0639
0640 return 0;
0641 }
0642
0643 static int rpm_reg_of_parse_freq(struct device *dev,
0644 struct device_node *node,
0645 struct qcom_rpm_reg *vreg)
0646 {
0647 static const int freq_table[] = {
0648 19200000, 9600000, 6400000, 4800000, 3840000, 3200000, 2740000,
0649 2400000, 2130000, 1920000, 1750000, 1600000, 1480000, 1370000,
0650 1280000, 1200000,
0651
0652 };
0653 const char *key;
0654 u32 freq;
0655 int ret;
0656 int i;
0657
0658 key = "qcom,switch-mode-frequency";
0659 ret = of_property_read_u32(node, key, &freq);
0660 if (ret) {
0661 dev_err(dev, "regulator requires %s property\n", key);
0662 return -EINVAL;
0663 }
0664
0665 for (i = 0; i < ARRAY_SIZE(freq_table); i++) {
0666 if (freq == freq_table[i]) {
0667 rpm_reg_set(vreg, &vreg->parts->freq, i + 1);
0668 return 0;
0669 }
0670 }
0671
0672 dev_err(dev, "invalid frequency %d\n", freq);
0673 return -EINVAL;
0674 }
0675
0676 static int rpm_reg_of_parse(struct device_node *node,
0677 const struct regulator_desc *desc,
0678 struct regulator_config *config)
0679 {
0680 struct qcom_rpm_reg *vreg = config->driver_data;
0681 struct device *dev = config->dev;
0682 const char *key;
0683 u32 force_mode;
0684 bool pwm;
0685 u32 val;
0686 int ret;
0687
0688 key = "bias-pull-down";
0689 if (of_property_read_bool(node, key)) {
0690 ret = rpm_reg_set(vreg, &vreg->parts->pd, 1);
0691 if (ret) {
0692 dev_err(dev, "%s is invalid", key);
0693 return ret;
0694 }
0695 }
0696
0697 if (vreg->parts->freq.mask) {
0698 ret = rpm_reg_of_parse_freq(dev, node, vreg);
0699 if (ret < 0)
0700 return ret;
0701 }
0702
0703 if (vreg->parts->pm.mask) {
0704 key = "qcom,power-mode-hysteretic";
0705 pwm = !of_property_read_bool(node, key);
0706
0707 ret = rpm_reg_set(vreg, &vreg->parts->pm, pwm);
0708 if (ret) {
0709 dev_err(dev, "failed to set power mode\n");
0710 return ret;
0711 }
0712 }
0713
0714 if (vreg->parts->fm.mask) {
0715 force_mode = -1;
0716
0717 key = "qcom,force-mode";
0718 ret = of_property_read_u32(node, key, &val);
0719 if (ret == -EINVAL) {
0720 val = QCOM_RPM_FORCE_MODE_NONE;
0721 } else if (ret < 0) {
0722 dev_err(dev, "failed to read %s\n", key);
0723 return ret;
0724 }
0725
0726
0727
0728
0729
0730
0731
0732
0733 switch (val) {
0734 case QCOM_RPM_FORCE_MODE_NONE:
0735 force_mode = 0;
0736 break;
0737 case QCOM_RPM_FORCE_MODE_LPM:
0738 force_mode = 1;
0739 break;
0740 case QCOM_RPM_FORCE_MODE_HPM:
0741 if (FORCE_MODE_IS_2_BITS(vreg))
0742 force_mode = 2;
0743 else
0744 force_mode = 3;
0745 break;
0746 case QCOM_RPM_FORCE_MODE_AUTO:
0747 if (vreg->supports_force_mode_auto)
0748 force_mode = 2;
0749 break;
0750 case QCOM_RPM_FORCE_MODE_BYPASS:
0751 if (vreg->supports_force_mode_bypass)
0752 force_mode = 4;
0753 break;
0754 }
0755
0756 if (force_mode == -1) {
0757 dev_err(dev, "invalid force mode\n");
0758 return -EINVAL;
0759 }
0760
0761 ret = rpm_reg_set(vreg, &vreg->parts->fm, force_mode);
0762 if (ret) {
0763 dev_err(dev, "failed to set force mode\n");
0764 return ret;
0765 }
0766 }
0767
0768 return 0;
0769 }
0770
0771 struct rpm_regulator_data {
0772 const char *name;
0773 int resource;
0774 const struct qcom_rpm_reg *template;
0775 const char *supply;
0776 };
0777
0778 static const struct rpm_regulator_data rpm_pm8018_regulators[] = {
0779 { "s1", QCOM_RPM_PM8018_SMPS1, &pm8018_smps, "vdd_s1" },
0780 { "s2", QCOM_RPM_PM8018_SMPS2, &pm8018_smps, "vdd_s2" },
0781 { "s3", QCOM_RPM_PM8018_SMPS3, &pm8018_smps, "vdd_s3" },
0782 { "s4", QCOM_RPM_PM8018_SMPS4, &pm8018_smps, "vdd_s4" },
0783 { "s5", QCOM_RPM_PM8018_SMPS5, &pm8018_smps, "vdd_s5" },
0784
0785 { "l2", QCOM_RPM_PM8018_LDO2, &pm8018_pldo, "vdd_l2" },
0786 { "l3", QCOM_RPM_PM8018_LDO3, &pm8018_pldo, "vdd_l3" },
0787 { "l4", QCOM_RPM_PM8018_LDO4, &pm8018_pldo, "vdd_l4" },
0788 { "l5", QCOM_RPM_PM8018_LDO5, &pm8018_pldo, "vdd_l5" },
0789 { "l6", QCOM_RPM_PM8018_LDO6, &pm8018_pldo, "vdd_l7" },
0790 { "l7", QCOM_RPM_PM8018_LDO7, &pm8018_pldo, "vdd_l7" },
0791 { "l8", QCOM_RPM_PM8018_LDO8, &pm8018_nldo, "vdd_l8" },
0792 { "l9", QCOM_RPM_PM8018_LDO9, &pm8921_nldo1200,
0793 "vdd_l9_l10_l11_l12" },
0794 { "l10", QCOM_RPM_PM8018_LDO10, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
0795 { "l11", QCOM_RPM_PM8018_LDO11, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
0796 { "l12", QCOM_RPM_PM8018_LDO12, &pm8018_nldo, "vdd_l9_l10_l11_l12" },
0797 { "l14", QCOM_RPM_PM8018_LDO14, &pm8018_pldo, "vdd_l14" },
0798
0799 { "lvs1", QCOM_RPM_PM8018_LVS1, &pm8018_switch, "lvs1_in" },
0800
0801 { }
0802 };
0803
0804 static const struct rpm_regulator_data rpm_pm8058_regulators[] = {
0805 { "l0", QCOM_RPM_PM8058_LDO0, &pm8058_nldo, "vdd_l0_l1_lvs" },
0806 { "l1", QCOM_RPM_PM8058_LDO1, &pm8058_nldo, "vdd_l0_l1_lvs" },
0807 { "l2", QCOM_RPM_PM8058_LDO2, &pm8058_pldo, "vdd_l2_l11_l12" },
0808 { "l3", QCOM_RPM_PM8058_LDO3, &pm8058_pldo, "vdd_l3_l4_l5" },
0809 { "l4", QCOM_RPM_PM8058_LDO4, &pm8058_pldo, "vdd_l3_l4_l5" },
0810 { "l5", QCOM_RPM_PM8058_LDO5, &pm8058_pldo, "vdd_l3_l4_l5" },
0811 { "l6", QCOM_RPM_PM8058_LDO6, &pm8058_pldo, "vdd_l6_l7" },
0812 { "l7", QCOM_RPM_PM8058_LDO7, &pm8058_pldo, "vdd_l6_l7" },
0813 { "l8", QCOM_RPM_PM8058_LDO8, &pm8058_pldo, "vdd_l8" },
0814 { "l9", QCOM_RPM_PM8058_LDO9, &pm8058_pldo, "vdd_l9" },
0815 { "l10", QCOM_RPM_PM8058_LDO10, &pm8058_pldo, "vdd_l10" },
0816 { "l11", QCOM_RPM_PM8058_LDO11, &pm8058_pldo, "vdd_l2_l11_l12" },
0817 { "l12", QCOM_RPM_PM8058_LDO12, &pm8058_pldo, "vdd_l2_l11_l12" },
0818 { "l13", QCOM_RPM_PM8058_LDO13, &pm8058_pldo, "vdd_l13_l16" },
0819 { "l14", QCOM_RPM_PM8058_LDO14, &pm8058_pldo, "vdd_l14_l15" },
0820 { "l15", QCOM_RPM_PM8058_LDO15, &pm8058_pldo, "vdd_l14_l15" },
0821 { "l16", QCOM_RPM_PM8058_LDO16, &pm8058_pldo, "vdd_l13_l16" },
0822 { "l17", QCOM_RPM_PM8058_LDO17, &pm8058_pldo, "vdd_l17_l18" },
0823 { "l18", QCOM_RPM_PM8058_LDO18, &pm8058_pldo, "vdd_l17_l18" },
0824 { "l19", QCOM_RPM_PM8058_LDO19, &pm8058_pldo, "vdd_l19_l20" },
0825 { "l20", QCOM_RPM_PM8058_LDO20, &pm8058_pldo, "vdd_l19_l20" },
0826 { "l21", QCOM_RPM_PM8058_LDO21, &pm8058_nldo, "vdd_l21" },
0827 { "l22", QCOM_RPM_PM8058_LDO22, &pm8058_nldo, "vdd_l22" },
0828 { "l23", QCOM_RPM_PM8058_LDO23, &pm8058_nldo, "vdd_l23_l24_l25" },
0829 { "l24", QCOM_RPM_PM8058_LDO24, &pm8058_nldo, "vdd_l23_l24_l25" },
0830 { "l25", QCOM_RPM_PM8058_LDO25, &pm8058_nldo, "vdd_l23_l24_l25" },
0831
0832 { "s0", QCOM_RPM_PM8058_SMPS0, &pm8058_smps, "vdd_s0" },
0833 { "s1", QCOM_RPM_PM8058_SMPS1, &pm8058_smps, "vdd_s1" },
0834 { "s2", QCOM_RPM_PM8058_SMPS2, &pm8058_smps, "vdd_s2" },
0835 { "s3", QCOM_RPM_PM8058_SMPS3, &pm8058_smps, "vdd_s3" },
0836 { "s4", QCOM_RPM_PM8058_SMPS4, &pm8058_smps, "vdd_s4" },
0837
0838 { "lvs0", QCOM_RPM_PM8058_LVS0, &pm8058_switch, "vdd_l0_l1_lvs" },
0839 { "lvs1", QCOM_RPM_PM8058_LVS1, &pm8058_switch, "vdd_l0_l1_lvs" },
0840
0841 { "ncp", QCOM_RPM_PM8058_NCP, &pm8058_ncp, "vdd_ncp" },
0842 { }
0843 };
0844
0845 static const struct rpm_regulator_data rpm_pm8901_regulators[] = {
0846 { "l0", QCOM_RPM_PM8901_LDO0, &pm8901_nldo, "vdd_l0" },
0847 { "l1", QCOM_RPM_PM8901_LDO1, &pm8901_pldo, "vdd_l1" },
0848 { "l2", QCOM_RPM_PM8901_LDO2, &pm8901_pldo, "vdd_l2" },
0849 { "l3", QCOM_RPM_PM8901_LDO3, &pm8901_pldo, "vdd_l3" },
0850 { "l4", QCOM_RPM_PM8901_LDO4, &pm8901_pldo, "vdd_l4" },
0851 { "l5", QCOM_RPM_PM8901_LDO5, &pm8901_pldo, "vdd_l5" },
0852 { "l6", QCOM_RPM_PM8901_LDO6, &pm8901_pldo, "vdd_l6" },
0853
0854 { "s0", QCOM_RPM_PM8901_SMPS0, &pm8901_ftsmps, "vdd_s0" },
0855 { "s1", QCOM_RPM_PM8901_SMPS1, &pm8901_ftsmps, "vdd_s1" },
0856 { "s2", QCOM_RPM_PM8901_SMPS2, &pm8901_ftsmps, "vdd_s2" },
0857 { "s3", QCOM_RPM_PM8901_SMPS3, &pm8901_ftsmps, "vdd_s3" },
0858 { "s4", QCOM_RPM_PM8901_SMPS4, &pm8901_ftsmps, "vdd_s4" },
0859
0860 { "lvs0", QCOM_RPM_PM8901_LVS0, &pm8901_switch, "lvs0_in" },
0861 { "lvs1", QCOM_RPM_PM8901_LVS1, &pm8901_switch, "lvs1_in" },
0862 { "lvs2", QCOM_RPM_PM8901_LVS2, &pm8901_switch, "lvs2_in" },
0863 { "lvs3", QCOM_RPM_PM8901_LVS3, &pm8901_switch, "lvs3_in" },
0864
0865 { "mvs", QCOM_RPM_PM8901_MVS, &pm8901_switch, "mvs_in" },
0866 { }
0867 };
0868
0869 static const struct rpm_regulator_data rpm_pm8921_regulators[] = {
0870 { "s1", QCOM_RPM_PM8921_SMPS1, &pm8921_smps, "vdd_s1" },
0871 { "s2", QCOM_RPM_PM8921_SMPS2, &pm8921_smps, "vdd_s2" },
0872 { "s3", QCOM_RPM_PM8921_SMPS3, &pm8921_smps },
0873 { "s4", QCOM_RPM_PM8921_SMPS4, &pm8921_smps, "vdd_s4" },
0874 { "s7", QCOM_RPM_PM8921_SMPS7, &pm8921_smps, "vdd_s7" },
0875 { "s8", QCOM_RPM_PM8921_SMPS8, &pm8921_smps, "vdd_s8" },
0876
0877 { "l1", QCOM_RPM_PM8921_LDO1, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
0878 { "l2", QCOM_RPM_PM8921_LDO2, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
0879 { "l3", QCOM_RPM_PM8921_LDO3, &pm8921_pldo, "vdd_l3_l15_l17" },
0880 { "l4", QCOM_RPM_PM8921_LDO4, &pm8921_pldo, "vdd_l4_l14" },
0881 { "l5", QCOM_RPM_PM8921_LDO5, &pm8921_pldo, "vdd_l5_l8_l16" },
0882 { "l6", QCOM_RPM_PM8921_LDO6, &pm8921_pldo, "vdd_l6_l7" },
0883 { "l7", QCOM_RPM_PM8921_LDO7, &pm8921_pldo, "vdd_l6_l7" },
0884 { "l8", QCOM_RPM_PM8921_LDO8, &pm8921_pldo, "vdd_l5_l8_l16" },
0885 { "l9", QCOM_RPM_PM8921_LDO9, &pm8921_pldo, "vdd_l9_l11" },
0886 { "l10", QCOM_RPM_PM8921_LDO10, &pm8921_pldo, "vdd_l10_l22" },
0887 { "l11", QCOM_RPM_PM8921_LDO11, &pm8921_pldo, "vdd_l9_l11" },
0888 { "l12", QCOM_RPM_PM8921_LDO12, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
0889 { "l14", QCOM_RPM_PM8921_LDO14, &pm8921_pldo, "vdd_l4_l14" },
0890 { "l15", QCOM_RPM_PM8921_LDO15, &pm8921_pldo, "vdd_l3_l15_l17" },
0891 { "l16", QCOM_RPM_PM8921_LDO16, &pm8921_pldo, "vdd_l5_l8_l16" },
0892 { "l17", QCOM_RPM_PM8921_LDO17, &pm8921_pldo, "vdd_l3_l15_l17" },
0893 { "l18", QCOM_RPM_PM8921_LDO18, &pm8921_nldo, "vdd_l1_l2_l12_l18" },
0894 { "l21", QCOM_RPM_PM8921_LDO21, &pm8921_pldo, "vdd_l21_l23_l29" },
0895 { "l22", QCOM_RPM_PM8921_LDO22, &pm8921_pldo, "vdd_l10_l22" },
0896 { "l23", QCOM_RPM_PM8921_LDO23, &pm8921_pldo, "vdd_l21_l23_l29" },
0897 { "l24", QCOM_RPM_PM8921_LDO24, &pm8921_nldo1200, "vdd_l24" },
0898 { "l25", QCOM_RPM_PM8921_LDO25, &pm8921_nldo1200, "vdd_l25" },
0899 { "l26", QCOM_RPM_PM8921_LDO26, &pm8921_nldo1200, "vdd_l26" },
0900 { "l27", QCOM_RPM_PM8921_LDO27, &pm8921_nldo1200, "vdd_l27" },
0901 { "l28", QCOM_RPM_PM8921_LDO28, &pm8921_nldo1200, "vdd_l28" },
0902 { "l29", QCOM_RPM_PM8921_LDO29, &pm8921_pldo, "vdd_l21_l23_l29" },
0903
0904 { "lvs1", QCOM_RPM_PM8921_LVS1, &pm8921_switch, "vin_lvs1_3_6" },
0905 { "lvs2", QCOM_RPM_PM8921_LVS2, &pm8921_switch, "vin_lvs2" },
0906 { "lvs3", QCOM_RPM_PM8921_LVS3, &pm8921_switch, "vin_lvs1_3_6" },
0907 { "lvs4", QCOM_RPM_PM8921_LVS4, &pm8921_switch, "vin_lvs4_5_7" },
0908 { "lvs5", QCOM_RPM_PM8921_LVS5, &pm8921_switch, "vin_lvs4_5_7" },
0909 { "lvs6", QCOM_RPM_PM8921_LVS6, &pm8921_switch, "vin_lvs1_3_6" },
0910 { "lvs7", QCOM_RPM_PM8921_LVS7, &pm8921_switch, "vin_lvs4_5_7" },
0911
0912 { "usb-switch", QCOM_RPM_USB_OTG_SWITCH, &pm8921_switch, "vin_5vs" },
0913 { "hdmi-switch", QCOM_RPM_HDMI_SWITCH, &pm8921_switch, "vin_5vs" },
0914 { "ncp", QCOM_RPM_PM8921_NCP, &pm8921_ncp, "vdd_ncp" },
0915 { }
0916 };
0917
0918 static const struct rpm_regulator_data rpm_smb208_regulators[] = {
0919 { "s1a", QCOM_RPM_SMB208_S1a, &smb208_smps, "vin_s1a" },
0920 { "s1b", QCOM_RPM_SMB208_S1b, &smb208_smps, "vin_s1b" },
0921 { "s2a", QCOM_RPM_SMB208_S2a, &smb208_smps, "vin_s2a" },
0922 { "s2b", QCOM_RPM_SMB208_S2b, &smb208_smps, "vin_s2b" },
0923 { }
0924 };
0925
0926 static const struct of_device_id rpm_of_match[] = {
0927 { .compatible = "qcom,rpm-pm8018-regulators",
0928 .data = &rpm_pm8018_regulators },
0929 { .compatible = "qcom,rpm-pm8058-regulators", .data = &rpm_pm8058_regulators },
0930 { .compatible = "qcom,rpm-pm8901-regulators", .data = &rpm_pm8901_regulators },
0931 { .compatible = "qcom,rpm-pm8921-regulators", .data = &rpm_pm8921_regulators },
0932 { .compatible = "qcom,rpm-smb208-regulators", .data = &rpm_smb208_regulators },
0933 { }
0934 };
0935 MODULE_DEVICE_TABLE(of, rpm_of_match);
0936
0937 static int rpm_reg_probe(struct platform_device *pdev)
0938 {
0939 const struct rpm_regulator_data *reg;
0940 const struct of_device_id *match;
0941 struct regulator_config config = { };
0942 struct regulator_dev *rdev;
0943 struct qcom_rpm_reg *vreg;
0944 struct qcom_rpm *rpm;
0945
0946 rpm = dev_get_drvdata(pdev->dev.parent);
0947 if (!rpm) {
0948 dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
0949 return -ENODEV;
0950 }
0951
0952 match = of_match_device(rpm_of_match, &pdev->dev);
0953 if (!match) {
0954 dev_err(&pdev->dev, "failed to match device\n");
0955 return -ENODEV;
0956 }
0957
0958 for (reg = match->data; reg->name; reg++) {
0959 vreg = devm_kmalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
0960 if (!vreg)
0961 return -ENOMEM;
0962
0963 memcpy(vreg, reg->template, sizeof(*vreg));
0964 mutex_init(&vreg->lock);
0965
0966 vreg->dev = &pdev->dev;
0967 vreg->resource = reg->resource;
0968 vreg->rpm = rpm;
0969
0970 vreg->desc.id = -1;
0971 vreg->desc.owner = THIS_MODULE;
0972 vreg->desc.type = REGULATOR_VOLTAGE;
0973 vreg->desc.name = reg->name;
0974 vreg->desc.supply_name = reg->supply;
0975 vreg->desc.of_match = reg->name;
0976 vreg->desc.of_parse_cb = rpm_reg_of_parse;
0977
0978 config.dev = &pdev->dev;
0979 config.driver_data = vreg;
0980 rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
0981 if (IS_ERR(rdev)) {
0982 dev_err(&pdev->dev, "failed to register %s\n", reg->name);
0983 return PTR_ERR(rdev);
0984 }
0985 }
0986
0987 return 0;
0988 }
0989
0990 static struct platform_driver rpm_reg_driver = {
0991 .probe = rpm_reg_probe,
0992 .driver = {
0993 .name = "qcom_rpm_reg",
0994 .of_match_table = of_match_ptr(rpm_of_match),
0995 },
0996 };
0997
0998 static int __init rpm_reg_init(void)
0999 {
1000 return platform_driver_register(&rpm_reg_driver);
1001 }
1002 subsys_initcall(rpm_reg_init);
1003
1004 static void __exit rpm_reg_exit(void)
1005 {
1006 platform_driver_unregister(&rpm_reg_driver);
1007 }
1008 module_exit(rpm_reg_exit)
1009
1010 MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1011 MODULE_LICENSE("GPL v2");