drivers/regulator/pv88090-regulator.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * pv88090-regulator.h - Regulator definitions for PV88090
0004  * Copyright (C) 2015 Powerventure Semiconductor Ltd.
0005  */
0006
0007 #ifndef __PV88090_REGISTERS_H__
0008 #define __PV88090_REGISTERS_H__
0009
0010 /* System Control and Event Registers */
0011 #define PV88090_REG_EVENT_A         0x03
0012 #define PV88090_REG_MASK_A          0x06
0013 #define PV88090_REG_MASK_B          0x07
0014
0015 /* Regulator Registers */
0016 #define PV88090_REG_BUCK1_CONF0         0x18
0017 #define PV88090_REG_BUCK1_CONF1         0x19
0018 #define PV88090_REG_BUCK1_CONF2         0x1a
0019 #define PV88090_REG_BUCK2_CONF0         0x1b
0020 #define PV88090_REG_BUCK2_CONF1         0x1c
0021 #define PV88090_REG_BUCK2_CONF2         0x58
0022 #define PV88090_REG_BUCK3_CONF0         0x1d
0023 #define PV88090_REG_BUCK3_CONF1         0x1e
0024 #define PV88090_REG_BUCK3_CONF2         0x5c
0025
0026 #define PV88090_REG_LDO1_CONT           0x1f
0027 #define PV88090_REG_LDO2_CONT           0x20
0028 #define PV88090_REG_LDO3_CONT           0x21
0029 #define PV88090_REG_BUCK_FOLD_RANGE         0x61
0030
0031 /* PV88090_REG_EVENT_A (addr=0x03) */
0032 #define PV88090_E_VDD_FLT               0x01
0033 #define PV88090_E_OVER_TEMP         0x02
0034
0035 /* PV88090_REG_MASK_A (addr=0x06) */
0036 #define PV88090_M_VDD_FLT               0x01
0037 #define PV88090_M_OVER_TEMP         0x02
0038
0039 /* PV88090_REG_BUCK1_CONF0 (addr=0x18) */
0040 #define PV88090_BUCK1_EN                0x80
0041 #define PV88090_VBUCK1_MASK         0x7F
0042 /* PV88090_REG_BUCK2_CONF0 (addr=0x1b) */
0043 #define PV88090_BUCK2_EN                0x80
0044 #define PV88090_VBUCK2_MASK         0x7F
0045 /* PV88090_REG_BUCK3_CONF0 (addr=0x1d) */
0046 #define PV88090_BUCK3_EN                0x80
0047 #define PV88090_VBUCK3_MASK         0x7F
0048 /* PV88090_REG_LDO1_CONT (addr=0x1f) */
0049 #define PV88090_LDO1_EN             0x40
0050 #define PV88090_VLDO1_MASK          0x3F
0051 /* PV88090_REG_LDO2_CONT (addr=0x20) */
0052 #define PV88090_LDO2_EN             0x40
0053 #define PV88090_VLDO2_MASK          0x3F
0054
0055 /* PV88090_REG_BUCK1_CONF1 (addr=0x19) */
0056 #define PV88090_BUCK1_ILIM_SHIFT            2
0057 #define PV88090_BUCK1_ILIM_MASK         0x7C
0058 #define PV88090_BUCK1_MODE_MASK         0x03
0059
0060 /* PV88090_REG_BUCK2_CONF1 (addr=0x1c) */
0061 #define PV88090_BUCK2_ILIM_SHIFT            2
0062 #define PV88090_BUCK2_ILIM_MASK         0x0C
0063 #define PV88090_BUCK2_MODE_MASK         0x03
0064
0065 /* PV88090_REG_BUCK3_CONF1 (addr=0x1e) */
0066 #define PV88090_BUCK3_ILIM_SHIFT            2
0067 #define PV88090_BUCK3_ILIM_MASK         0x0C
0068 #define PV88090_BUCK3_MODE_MASK         0x03
0069
0070 #define PV88090_BUCK_MODE_SLEEP         0x00
0071 #define PV88090_BUCK_MODE_AUTO          0x01
0072 #define PV88090_BUCK_MODE_SYNC          0x02
0073
0074 /* PV88090_REG_BUCK2_CONF2 (addr=0x58) */
0075 /* PV88090_REG_BUCK3_CONF2 (addr=0x5c) */
0076 #define PV88090_BUCK_VDAC_RANGE_SHIFT           7
0077 #define PV88090_BUCK_VDAC_RANGE_MASK            0x01
0078
0079 #define PV88090_BUCK_VDAC_RANGE_1           0x00
0080 #define PV88090_BUCK_VDAC_RANGE_2           0x01
0081
0082 /* PV88090_REG_BUCK_FOLD_RANGE (addr=0x61) */
0083 #define PV88090_BUCK_VRANGE_GAIN_SHIFT          3
0084 #define PV88090_BUCK_VRANGE_GAIN_MASK           0x01
0085
0086 #define PV88090_BUCK_VRANGE_GAIN_1          0x00
0087 #define PV88090_BUCK_VRANGE_GAIN_2          0x01
0088
0089 #endif  /* __PV88090_REGISTERS_H__ */